JPS58206155A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS58206155A JPS58206155A JP8856882A JP8856882A JPS58206155A JP S58206155 A JPS58206155 A JP S58206155A JP 8856882 A JP8856882 A JP 8856882A JP 8856882 A JP8856882 A JP 8856882A JP S58206155 A JPS58206155 A JP S58206155A
- Authority
- JP
- Japan
- Prior art keywords
- bevel
- layer
- emitter
- etching
- edge
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 31
- 238000003754 machining Methods 0.000 claims 1
- 238000005530 etching Methods 0.000 abstract description 7
- 238000000034 method Methods 0.000 abstract description 7
- 230000006866 deterioration Effects 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract description 3
- 239000003223 protective agent Substances 0.000 abstract 1
- 238000003466 welding Methods 0.000 abstract 1
- 230000002093 peripheral effect Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 241000555745 Sciuridae Species 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000001154 acute effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000010297 mechanical methods and process Methods 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 239000003755 preservative agent Substances 0.000 description 1
- 230000002335 preservative effect Effects 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 238000005488 sandblasting Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
- Thyristors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は大電力用のトランジスタやサイリスタ等のベ
ベル構造を有する半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device having a bevel structure, such as a high-power transistor or a thyristor.
大電力用のトランジスタとしてｗｃ１図に示すようなエ
ミ、り圧接構造を有するトランジスタが使用されている
・
このようなトランジスタの半導体素子本体１０は下層か
ら）ｖＡにＮ型基板７、Ｐ型ベース層８およびＮ＋型エ
ミ、り層９を有する半導体ウェーハの上面のＮ＋層９を
ケミカルエツチングして、図のよりなＮ＋ＰＮＩ＋型ト
ランノスタのエミッタ領域となる凸部１１．１１・・・
と、ペース領域の篇出し次低ｆＩ５１２，１２・・・全
形成したものである。As a transistor for high power, a transistor having an emitter/pressure contact structure as shown in figure WC1 is used.The semiconductor element body 10 of such a transistor consists of an N-type substrate 7, a P-type base layer, and By chemically etching the N+ layer 9 on the upper surface of the semiconductor wafer having the N+ type emitter layer 9 and the N+ type emitter layer 9, the convex portions 11, 11, . . .
And, the pace area's set-up next low fI512, 12... is completely formed.
この半導体素子本体１０の凸部１１．１１・・・上面に
はエミ、り電極１３，１３・・・を低部１２゜１２・・
・にはペース電極１４．１４・・・をそれぞれシリコン
酸化膜１５のコンタクトホール上に形成する。そして、
上記エミッタ電極１３．１３・・・にこのエミ、り電極
１３．１３を棲う程度の大きさの圧接電極板１６全圧接
し、上記半導体素子本体Ｊ１面にはコレクタ電極板１７
ｔ−圧接する。The convex portions 11, 11, . . . of the semiconductor element body 10 have emitter electrodes 13, 13, .
*, space electrodes 14, 14, . . . are formed on the contact holes of the silicon oxide film 15, respectively. and,
The emitter electrodes 13.13... are in full pressure contact with a press-contact electrode plate 16 of a size large enough to accommodate the emitter electrodes 13.13, and a collector electrode plate 17 is attached to the J1 surface of the semiconductor element main body.
T-press.
また、上記半導体素子本体１０の燭囲には表面電界強度
を弱め耐圧を向上させる目的で傾斜した切り牌なるベベ
ル１８を形成し、このベベル１８を表面体−剤１９で埋
め込む。Further, an inclined bevel 18 is formed around the candle of the semiconductor element body 10 for the purpose of weakening the surface electric field strength and improving the withstand voltage, and this bevel 18 is filled with a surface agent 19.
第２図はこのベベル１８付近を拡大して７Ｊりす図で、
ＰＮ従合部が逆バイアスさ扛ると、図の破勝２０Ｐ、２
ＯＮ’Ｃ小す領域に空乏層２０が発生し、（ペル表面で
の空乏ｒ＠２０の広がりｔｊＰＮ接合の低一度側（Ｎ世
＋１ ）に大きく曲がったものとなる。ここで、ベベル
構造を採用することにより、ＰＮ接合表血での電界’洩
Ｉｆを弱め、ベベル表面での空乏層２０の広がりを上記
のようなものとして素子の耐圧を向上せしめる。Figure 2 is an enlarged 7J squirrel diagram of the vicinity of this bevel 18,
When the PN follower is reverse biased, the result is 20P, 2 in the figure.
A depletion layer 20 is generated in the ON'C region, and the depletion r@20 on the surface of the pel is greatly curved toward the low degree side (N+1) of the PN junction. By employing this, the electric field leakage If at the PN junction surface is weakened, and the depletion layer 20 spreads on the bevel surface as described above, thereby improving the breakdown voltage of the device.
しかし、ベベル形成１根では、半導体素子本体１０の周
縁部に、ダイヤモンド等の薄歯で削るグレード法や微粉
本１ｒ＾圧簡速噴射して削る１、ようなサンドブラスト
法等の機械的方法によって、＃ｌ斜した切り溝を形成す
ることから、第２図の円２１内で示すベベリングエツジ
付近にクラック（ひひ）やかけ（欠けた部分）が生じた
り、ベベリングエツジの先端がきれいな鋭角にならずに
丸みを１ひた「だれ」のあるものとなる。However, in the case of bevel formation, the periphery of the semiconductor element body 10 is polished by a mechanical method such as a grading method in which the peripheral edge of the semiconductor element body 10 is shaved with thin teeth such as diamond, or a sandblasting method in which the periphery of the semiconductor element body 10 is shaved by a high-speed jet of fine powder. , #l Since the oblique cut groove is formed, cracks or chips may occur near the beveling edge shown in circle 21 in Figure 2, or the tip of the beveling edge may have a clean acute angle. It becomes one with a roundness without becoming rounded.
一方、半導体の凸部１１．１１・・・上のエミ。On the other hand, the emitters on the convex portions 11, 11... of the semiconductor.
夕電極１３．１３・・・に圧接電極板１６を圧巌する構
ｆｆ１（エミッタ圧接構造）を有する半導体素子では、
凸部１１．１１・・・（低部１２，１２・・）を形成す
るためのエツチング工程において、エミ、り領域等の活
性領域を囲むベベル１８の形成される付近のＮ”ｌ−も
不安なものとして除去する。In a semiconductor element having a structure ff1 (emitter press-contact structure) in which the press-contact electrode plate 16 is pressed against the emitter electrodes 13, 13...
In the etching process for forming the convex parts 11, 11... (low parts 12, 12, etc.), N"l- is also unstable near where the bevel 18 surrounding the active region such as the emitter region is formed. remove as something.
このため、これらのクラック、かけ或は「だれ」が例え
ば第２図の破線２２で示すように発生した場合、ベベリ
ングエツジと空乏層領域とが嵌しベベル１８表面の耐圧
が劣化し、素子の耐圧不良を招いて、歩留が悪いもので
めった。For this reason, if these cracks, breaks, or "drops" occur, for example, as shown by the broken line 22 in FIG. This resulted in poor withstand voltage, resulting in poor yields.
この発明は上記のような点に鑑みなされたもので、ベベ
リングエツジのクラック、かけ、［−だれ」等の機械的
損傷の形番による耐圧劣化の低減された半導体装ｔ’を
提供し、製造歩留の向上を図るものである。The present invention has been made in view of the above points, and provides a semiconductor device t' in which breakdown voltage deterioration due to mechanical damage such as cracks, chips, and droop on the bevelling edge is reduced, The aim is to improve manufacturing yield.
すなわち、この発明に係る半導体装ｔＪＩｔは、半導体
素子本体表面をエツチングし圧接電極板と接続される凸
部を形成する工程において、−寸ペルの形成される付近
の半導体素子本体表ｒｋＪはエツチングせず１．ｈＷ己
くベル周辺は、上記のエツチングにより形成きれた四部
よりも高くして、ベベリングエツジと空乏層の発生する
ＰＮ接合向との間に充分な間隔′ｆｃ設定するようにし
、クラ、り、かけ、「だ扛」等の機械的損傷の影＊１低
減させたものである。That is, in the semiconductor device tJIt according to the present invention, in the step of etching the surface of the semiconductor element body to form a convex portion connected to the pressure contact electrode plate, the semiconductor element body surface rkJ in the vicinity where the -dimension pel is formed is not etched. 1. The area around the bell should be made higher than the four parts completely formed by the etching described above, and a sufficient distance fc should be set between the bevel edge and the direction of the PN junction where the depletion layer is generated. This reduces the effects of mechanical damage*1 such as , hanging, and ``dappaku''.
以下図面を診照してこの発明の一実施例につき説明する
。第３図（Ａ） 、 （Ｂ）はエミッタ圧接構造を有す
るＮＰＮ トランジスタを製造過程順にそのベベル付近
を中心にηくした図である。An embodiment of the present invention will be described below with reference to the drawings. FIGS. 3(A) and 3(B) are diagrams of an NPN transistor having an emitter press-contact structure in the order of the manufacturing process, with η centered around the bevel.
まず、第３図（４）に示すように、このようなトランジ
スタの半導体素子本体３０＃ｉ、下層から順にコレクタ
層となるＮ＋啼３１およびＮ＠３２を構成する半導体基
板上に、ペース層となる２層３３およびエミ、りｊ曽と
なるＮ”１９７３４の形成さ扛た半導体ピ゛エーハを用
意し、このウェーノ・上（８）にベース１−となる２層
３３に運−する榎数の凹部Ｊ ５ 、 Ｊ ５をメサエ
ッチングｉ＋こより形成する。チタ、エツチング除去さ
７１．ずに残っｆｔ１−ｒ４己Ｎ＋ｌ＠ ３４は、上記
凹部３５，３５で分割さｎたエミッタ領域となるａｈの
凸部３６．３６ｆｔ形成する。First, as shown in FIG. 3(4), a paste layer and a semiconductor substrate are formed on the semiconductor element body 30#i of such a transistor, which constitutes the collector layer N+ layer 31 and N@32 in order from the bottom layer. Prepare a semiconductor wafer with two layers 33 and 19734 layers formed on it, and on this wafer (8), the number of layers to be transferred to the two layers 33 that will become the base 1-. The recesses J 5 and J 5 are formed by mesa etching.The titanium is etched away and remains ft1-r4selfN+l@34 is the emitter region divided by the recesses 35 and 35. A convex portion of 36.36ft is formed.
この場合、半導体素子本体３０のベベルの形成されるべ
き周縁部のＮ＋ＩＷｊＪ ４はエツチング除去せずに残
しておく。その後、第３図（Ｂ）に２Ｊりすように、エ
ミッタおよびペースのｔ憔取り出し口となるコンタクト
ホールの開口したシリコン酸化膜３７を形成し、各四部
３５．３５のコンタクトホールにはベース１！惨３８．
３８を・ンターニングし、同様に各凸部３６．３６のコ
ンタクトホールにはエミッタ′ｔｊＬ極３９にノ’ター
二／グする。In this case, the peripheral portion N+IWjJ 4 of the semiconductor element body 30 where the bevel is to be formed is left without being etched away. Thereafter, as shown in FIG. 3(B), a silicon oxide film 37 with contact holes that will serve as emitter and paste extraction ports is formed, and the base 1! Misery 38.
38, and in the same way, the emitter 'tjL pole 39 is marked in the contact hole of each convex part 36.36.
また、エミ、り饋城となる凸部３６．３６の形成され活
性領域となる半導体素子本体３ｏの中心部を囲むように
、半導体素子周辺部のＮ＋１ｄ３４の形成きれている上
面からグレード法政ｅ、１サンドゲラスト法によってＰ
Ｎ接合而面切断して切リＩ′４を入ｔ１づτル４０を形
成する。さらに、このベベル４０に一保護１４１１４０
１１ ｆｃ埋め込んで、上すに凸部３６ 、 、？ ６
Ｌｎｕ ｋ（つ形成されたエミッタ１極３９には、第
１図の一台とＩＬ〕］様に圧接電極板４１’（圧接する
。In addition, from the upper surface where N+1d34 of the peripheral part of the semiconductor element has been completely formed, grade Hosei e, 1 P by Sandgerast method
Cut the N joint surface and insert the cut I'4 to form a hole 40 by t1. Furthermore, this bevel 40 has one protection 141140
11 Embed fc and have convex part 36 on top? 6
The pressure-contact electrode plate 41' is pressure-contacted to the formed emitter one pole 39 (the one shown in FIG. 1 and IL)].
この場合、半導体素子本体３０の周縁部はエミッタ領域
となる凸部３６．３６とｔｌは同じ＾さ、すなわち同一
半面に形成されるが、圧接電極板４１は仮数の凸部３６
．３６を櫟う程度の形状と大きさであるため、上記周縁
部とこの圧接電極板４）が接触する恐れはない。In this case, the periphery of the semiconductor element body 30 has the same height as the convex portion 36.36 serving as the emitter region, that is, is formed on the same half surface, but the press-contact electrode plate 41 has the convex portion 36 of the mantissa.
．． 36, so there is no fear that the peripheral edge portion and this press-contact electrode plate 4) will come into contact with each other.
また、図の４２でろくすベベリングエツソＨガ■と、破
線４３Ｐ、４３Ｎで示す空乏層４３の拡がっている領域
との間隔が、Ｎ＋層３４の存在のために従来のものより
広くなっている。In addition, the distance between the beveled groove H gas marked at 42 in the figure and the region where the depletion layer 43 is expanding, indicated by broken lines 43P and 43N, is wider than that of the conventional one due to the presence of the N+ layer 34. .
このためクラック、かけ、「だれ」がベペリングエ、ツ
ノ付近に兄生じても、こ扛らの損傷が空乏＃４３にまで
及ふことか少なくなシ、ベベル４０でのｌＩｊ圧劣化に
よる製造参賀のはトを、特に汲雑な上程ヲ施さなくとも
防ぐことができる。For this reason, even if cracks, chips, or "someone" occur near the bevel ring or horn, it is unlikely that the damage will extend to the depletion #43. It is possible to prevent this without any particularly complicated treatment.
なお、上記実施例では、ベベリングエツジ４２の位＆を
扁くするためにエミッタとなるＮ＋層３４を残す場合に
ついて述べたが、半導体装”子表面に凸部を形成するた
めの工、チング工程において、ベベル４０の形成さする
べき素子周縁部を工、チングされないようにすれば、他
の半導体素子の場合でも同様の効果の得られることは明
らかである。In the above embodiment, a case was described in which the N+ layer 34 serving as an emitter was left in order to flatten the bevelling edge 42. It is clear that the same effect can be obtained in the case of other semiconductor devices as long as the peripheral edge of the device where the bevel 40 is to be formed is not etched or chipped in the process.
従って、第３図と同一構成分には四−符号を付してその
説明を省略するが、例えば第４図に示すように、Ｎ＋層
３４がベベリングエツジ４２付近にまで及ばないような
構造を有する半導体素子に適用できることは勿論のこと
、圧接を極に圧接される凸部を有し、ベベルの形成さ扛
る半導体素子であれば、ＰＮＰ ）ランジスタや、サイ
リスタ等の各種９半導体素子にも適用できる。Therefore, the same components as in FIG. 3 are given 4- symbols and their explanations are omitted. For example, as shown in FIG. 4, the N+ layer 34 does not extend to the vicinity of the beveling edge 42. Of course, it can be applied to semiconductor devices with PNP transistors, thyristors, etc., as long as the semiconductor device has a convex part that is pressed against the pole and does not have a bevel formed. can also be applied.
以上のようにこの発明によれば、特に俵雑な工程を付加
することなくベベリングエツジと空乏層の発生フるＰＮ
に＞ ９面との間ｅこ充分な間隔を設定することによ
り、ベベリングエツジ付近での機械的損傷の影響ＶＣＬ
る１土劣化の防かれ六半導体装置を提供することができ
、製造参賀の同上が図れる。As described above, according to the present invention, a bevelling edge and a depletion layer can be generated without adding any particularly complicated process.
By setting a sufficient distance between the VCL and the 9th surface, the influence of mechanical damage near the beveling edge can be reduced.
Therefore, it is possible to provide a semiconductor device which is prevented from deterioration, and the manufacturing process can be improved.
第１図は従来の半導体装置を示す断１図、第２図は第１
図をべくル付近を中上・に拡大してＩｆ＜す図、第３図
（Ａ） 、 （Ｂ）はそれぞ扛この発明に係る半導体装
置゛をその製造工程と共に示す断面図、第４図はこの発
明の他の実施例を下す図である。
９．３４・・・Ｎカ曽、１０．３０・・・半導体素子本
体、Ｉ Ｊ 、 、９６・・・凸部、１６．４１・・・
圧接電極板、１１１．４０・・・くペル、１９．４０＆
・・・保饋剤、３５・・・凹部、４２・・・ベベリング
エツジ。Figure 1 is a cross-sectional view of a conventional semiconductor device, and Figure 2 is a cross-sectional view of a conventional semiconductor device.
FIGS. 3A and 3B are cross-sectional views showing the semiconductor device according to the present invention together with its manufacturing process, and FIGS. The figure shows another embodiment of the invention. 9.34...N Kaso, 10.30...Semiconductor element body, IJ, ,96...Protrusion, 16.41...
Pressure contact electrode plate, 111.40...Kupel, 19.40&
. . . Preservative, 35 . . . Recessed portion, 42 . . . Beveling edge.
Claims (1)
を囲む凸部と、この凸部を含む活性領域を囲むベベルと
を具備し、上記ベベル周辺は上記凹部より高くしたこと
を％儀とする半導体装置。The upper surface has nine concave portions formed by machining and chiming, a convex portion surrounding the concave portion, and a bevel surrounding the active region including the convex portion, and the area around the bevel is higher than the concave portion. Semiconductor equipment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8856882A JPS58206155A (en) | 1982-05-25 | 1982-05-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8856882A JPS58206155A (en) | 1982-05-25 | 1982-05-25 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58206155A true JPS58206155A (en) | 1983-12-01 |
| JPH0429223B2 JPH0429223B2 (en) | 1992-05-18 |
Family
ID=13946461
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8856882A Granted JPS58206155A (en) | 1982-05-25 | 1982-05-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58206155A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60154564A (en) * | 1984-01-24 | 1985-08-14 | Fuji Electric Corp Res & Dev Ltd | Semiconductor device |
| JP2011124325A (en) * | 2009-12-09 | 2011-06-23 | Renesas Electronics Corp | Semiconductor device and method for manufacturing the same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5285481A (en) * | 1976-01-06 | 1977-07-15 | Westinghouse Electric Corp | Transistor |
| JPS5412268A (en) * | 1977-06-28 | 1979-01-29 | Mitsubishi Electric Corp | Production of semiconductor device |
| JPS5665667U (en) * | 1979-10-24 | 1981-06-01 |
-
1982
- 1982-05-25 JP JP8856882A patent/JPS58206155A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5285481A (en) * | 1976-01-06 | 1977-07-15 | Westinghouse Electric Corp | Transistor |
| JPS5412268A (en) * | 1977-06-28 | 1979-01-29 | Mitsubishi Electric Corp | Production of semiconductor device |
| JPS5665667U (en) * | 1979-10-24 | 1981-06-01 |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60154564A (en) * | 1984-01-24 | 1985-08-14 | Fuji Electric Corp Res & Dev Ltd | Semiconductor device |
| JP2011124325A (en) * | 2009-12-09 | 2011-06-23 | Renesas Electronics Corp | Semiconductor device and method for manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0429223B2 (en) | 1992-05-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109478561B (en) | Semiconductor device and method for manufacturing the same | |
| US3994011A (en) | High withstand voltage-semiconductor device with shallow grooves between semiconductor region and field limiting rings | |
| US4524376A (en) | Corrugated semiconductor device | |
| JP3117506B2 (en) | Semiconductor rectifier | |
| JPS58206155A (en) | Semiconductor device | |
| CA1148270A (en) | Mesa type semiconductor device with guard ring | |
| US4255757A (en) | High reverse voltage semiconductor device with fast recovery time with central depression | |
| US4074303A (en) | Semiconductor rectifier device | |
| JP2005183891A (en) | Structure of bidirectional block type planar device and method of manufacturing the same | |
| JPS6016105B2 (en) | Semiconductor controlled rectifier | |
| US3495138A (en) | Semi-conductor rectifiers with edgegeometry for reducing leakage current | |
| JPH0629557A (en) | Manufacture of semiconductor device | |
| JPS58121673A (en) | Inactivated semiconductor device and method of producing same | |
| US3270255A (en) | Silicon rectifying junction structures for electric power and process of production thereof | |
| JPS61144871A (en) | Beveled structure of semiconductor element | |
| JPH0580834B2 (en) | ||
| JPS6272163A (en) | Semiconductor device | |
| JPS6112069A (en) | Semiconductor device | |
| US3532946A (en) | Semiconductor element having pnpn structure and bevelled lateral surface | |
| KR100283808B1 (en) | Method for producing a twoside blocking power semiconductor | |
| GB1214151A (en) | Improvements in and relating to semiconductor devices | |
| JPH07273313A (en) | Semiconductor device with anode-side gettering | |
| JPS6151970A (en) | Semiconductor device | |
| JPS60154564A (en) | Semiconductor device | |
| JPS62232165A (en) | Bonding-surface machining method for semiconductor element |