JPS62232165A - Bonding-surface machining method for semiconductor element - Google Patents
Bonding-surface machining method for semiconductor elementInfo
- Publication number
- JPS62232165A JPS62232165A JP7482486A JP7482486A JPS62232165A JP S62232165 A JPS62232165 A JP S62232165A JP 7482486 A JP7482486 A JP 7482486A JP 7482486 A JP7482486 A JP 7482486A JP S62232165 A JPS62232165 A JP S62232165A
- Authority
- JP
- Japan
- Prior art keywords
- groove
- layer
- bevel
- depth
- dug
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 14
- 239000004065 semiconductor Substances 0.000 title claims description 6
- 238000003754 machining Methods 0.000 title abstract description 4
- 238000005530 etching Methods 0.000 claims abstract description 9
- 238000005488 sandblasting Methods 0.000 abstract description 8
- 230000015556 catabolic process Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000004576 sand Substances 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 238000003672 processing method Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000009412 basement excavation Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000005304 joining Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229920001296 polysiloxane Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000002966 varnish Substances 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000007514 turning Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
- Thyristors (AREA)
Abstract
Description
【発明の詳細な説明】
A、産業上のflI用分野
本発明は、電力用半導体素子の接合表面加工方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION A. FIELD OF INDUSTRIAL FLI APPLICATIONS The present invention relates to a method for processing a bonding surface of a power semiconductor device.
B1発明の概要
本発明は、PN接合を有する電力用半導体素子の接合表
面をベベル溝加工するにおいて、溝加工の掘込表面を予
め所定深さまで除去した後に溝加工の聞込みを行うこと
により、確実な114加工ができるようにしたしのであ
る。B1 Summary of the Invention The present invention provides a method for processing bevel grooves on the bonding surface of a power semiconductor element having a PN junction, by removing the excavated surface of the groove to a predetermined depth and then performing the groove processing. This allows for reliable 114 machining.
C従来の技術
サイリスタやトランジスタ等の電力用半導体素子はその
性能の1つとしての耐圧向上が要求され、従来からPN
接合表面に一定の傾斜角度を持たせろベベル溝を形成し
たものが知られている。C Conventional technology Power semiconductor devices such as thyristors and transistors are required to have improved breakdown voltage as one of their performance characteristics, and have traditionally been
It is known that a bevel groove is formed on the joining surface with a certain angle of inclination.
第4図は従来の電力用サイリスタの断面構造を示ず。P
、、 N、、 P、、N、からなろ4層3接合構造のシ
リコンに、そのP1層表面にはアルミニウムを主体とす
るロウ材1を使ってタングステン板(アノード電極)2
が合金後管され、またN7層表面にはアルミ電極(カソ
ード電極)3が、Pt層表面にはアルミ電極(ゲート電
極)4が接着される。このようなサイリスク構造におい
て、電極2.3間に印加する電圧、いわゆる阻止電圧を
100OV以上持たせるためには、順逆方向耐圧すなわ
ちN+P+、 N1Pt接合の逆耐圧を高めるよう素子
周辺P7層表面からN、P、接合表面に至る深さのベベ
ル溝5を掘込み、この溝5の回込角度になろN、Pt、
N、P、接合の切断面角度θ1(通常45°)を得る
ことでN、P、、 N、Pl接合で逆耐圧を上げるよう
にしている。なお、ベベル溝5はサンドブラストによっ
て掘込み形成し、!i’I¥内にはシリコンワニスが充
填されろ。FIG. 4 does not show the cross-sectional structure of a conventional power thyristor. P
A tungsten plate (anode electrode) 2 is formed on the surface of the P1 layer using a brazing material 1 mainly made of aluminum on the silicon with a 4-layer 3-junction structure made of N, P, ,N.
An aluminum electrode (cathode electrode) 3 is bonded to the surface of the N7 layer, and an aluminum electrode (gate electrode) 4 is bonded to the surface of the Pt layer. In such a cyrisk structure, in order to have a voltage applied between the electrodes 2.3, the so-called blocking voltage, of 100 OV or more, N is removed from the surface of the P7 layer around the element to increase the forward and reverse breakdown voltage, that is, the reverse breakdown voltage of the N+P+, N1Pt junction. , P, dig a bevel groove 5 deep enough to reach the joint surface, and make the turning angle of this groove 5 N, Pt,
By obtaining the cut plane angle θ1 (usually 45°) of the N, P, and N, P junctions, the reverse withstand voltage is increased in the N, P, N, and Pl junctions. Note that the bevel groove 5 is formed by digging by sandblasting. Fill i'I\ with silicone varnish.
03発明か解決しようとする問題点
従来の加工方法では、ベベル溝5の形成によって砂粒を
掘込方向に吹付けるが、このとき溝5の深さか大きくな
るはと、第5図に拡大図で示すように、最深部(斜線領
域A)てi74形状か所期の乙のと異なる変形をし、P
、N、接合表面の溝角度θ1が得られないことがある。03 Problems to be Solved by the Invention In the conventional machining method, sand grains are sprayed in the digging direction by forming the beveled groove 5, but at this time the depth of the groove 5 increases, as shown in an enlarged view in Fig. 5. As shown, the i74 shape at the deepest part (shaded area A) is deformed differently from the original shape, and P
, N, the groove angle θ1 of the bonding surface may not be obtained.
また、最深部の変形がその後のシリコンワニスの塗布、
充填に気泡か発生したり、エツチングや洗浄が不十分で
溝部での漏れiXX流会起こすことがあった。In addition, the deformation of the deepest part can be prevented by the subsequent application of silicone varnish.
Air bubbles were generated during filling, and etching and cleaning were insufficient, causing leakage in the grooves.
また、第5図に示すように、ベベル溝5が深いときには
その掘込口部に21層等の欠けやN1Pt接合を破損し
て所期の耐圧が得られなくなって歩溜まりを低下させる
原因になることがあった。In addition, as shown in Fig. 5, when the bevel groove 5 is deep, the 21st layer or the like may be chipped at the excavation opening, and the N1Pt junction may be damaged, making it impossible to obtain the desired withstand voltage and reducing the yield. Something happened.
E1問題点を解決するための手段
本発明は上記問題点に鑑みてなされたもので、ベベル溝
加工の掘込表面を予め所定深さエツチングによって除去
し、この除去した素子表面からベベル溝加工の掘込みを
行う加工方法とし、サンドブラストによる掘込深さを小
さくして層表面の欠けや溝変形を無くした加工を得る。E1 Means for Solving Problems The present invention has been made in view of the above-mentioned problems, and involves removing the excavated surface of the bevel groove by etching to a predetermined depth in advance, and then removing the etched surface of the bevel groove from the removed element surface. The processing method involves digging, and the depth of digging by sandblasting is reduced to obtain processing that eliminates chipping and groove deformation on the layer surface.
F 実施例
第1図は本発明方法の一実施例を示す要部拡大図である
。電力用サイリスクの周辺Pt層表面からP、FJに達
するベベル溝5をサンドブラスト法で掘込むにおいて、
溝掘込み前に27層の掘込み位置をN1層に達しない深
さhlまてエツチングによって除去されろ。この後、除
去部分(破線領域)のP、層表面からサンドブラスト法
によってベベル溝5を掘込む。F. Embodiment FIG. 1 is an enlarged view of essential parts showing an embodiment of the method of the present invention. In digging a bevel groove 5 reaching P and FJ from the peripheral Pt layer surface of the power SIRISK by sandblasting method,
Before digging the trench, remove the 27th layer by etching to a depth hl that does not reach the N1 layer. Thereafter, a bevel groove 5 is dug from the layer surface of the removed portion (dashed line area) by sandblasting.
こうした加工方法により、ベベル溝5の掘込深さは、そ
の前工程での除去部分深さhlだけ浅くなり、iM 5
の最深部及び掘込口共に欠けや変形を少なく又は完全に
無くすことができる。結果的に、P、N、接合及びN、
P、接合表面共に所期の角度を得ることかできる。With this processing method, the digging depth of the bevel groove 5 is reduced by the depth hl of the removed portion in the previous process, and the iM 5
It is possible to reduce or completely eliminate chipping and deformation both at the deepest part of the tunnel and at the excavation entrance. As a result, P, N, junction and N,
It is possible to obtain the desired angle for both P and joint surfaces.
また、従来方法ではベベル溝5を形成するとき、初期の
サンドブラストに素子表面に砂粒が飛散してNtPt接
合表面等を傷付ける恐れがあったが、本実施例のように
エツチング除去部がサンドブラストの吹付口として作用
することで砂粒の飛散を少なくする。この点について、
従来方法ではNyPt接合を砂粒から保護するために、
素子周面に保護材を塗布しておくが、本実施例ではこの
工程を省略また簡易にすることができる。In addition, in the conventional method, when forming the bevel groove 5, there was a risk that sand grains would scatter on the element surface during the initial sandblasting and damage the NtPt bonding surface, etc. However, in this embodiment, the etching removal part is removed by the sandblasting. By acting as a mouth, it reduces the scattering of sand grains. in this regard,
In the conventional method, in order to protect the NyPt joint from sand grains,
Although a protective material is applied to the peripheral surface of the element, this step can be omitted or simplified in this embodiment.
なお、エツチングによる除去にもベベル溝深さが大きく
なるとき、第2図に示すようにエツチング深さをN1層
に達する値り、まで行い、ベベル溝5の形成にN、P、
接合表面も切込むようにする。これによって、ベヘル溝
深さを一層浅くしなからP、N、。Note that when the bevel groove depth becomes large even when removing by etching, the etching depth is increased to a value reaching the N1 layer as shown in FIG.
Make sure to also cut the joining surface. This makes the depth of the Beher groove even shallower.
N、P、接合共にヘベル角度を持た仕ることができる。Both N, P and joints can have a Hevel angle.
また、実施例において、サイリスクの高耐圧化でシリコ
ン基板が厚くなるとき、P、N、接合の角度0、(例え
ば45°)も持つ構造にするとき、第3図に示すように
素子周面に傾斜θ、を持たせた2段へベル構造にしても
良い。このとき、素子の順(N1Pt接合)と逆(PI
N、接合)の両方の耐圧向上にしながらヘヘル+7+〒
形成さらには周面切削を容易にずろ。In addition, in the example, when the silicon substrate becomes thick due to the high withstand voltage of SiRisk, when a structure with P, N, and junction angles of 0 (for example, 45°) is created, the element peripheral surface as shown in FIG. A two-stage bell structure having an inclination θ may also be used. At this time, the order of the elements (N1Pt junction) and the reverse (PI
N, junction) while improving the withstand voltage of both +7+〒
Easy to form and even cut the circumferential surface.
なお、実施例は電力用サイリスクに適用した場合で示す
が、これはGTOサイリスク、パワートランジスタ、ダ
イオード等にら適用して同等の作用効果を得ろことがで
きる。Note that although the embodiment is shown in the case where the present invention is applied to a power thyristor, it can be applied to a GTO thyristor, a power transistor, a diode, etc. to obtain the same effect.
G 発明の効果
以上のとおり、本発明方法によれば、ヘヘル’tl+1
1の掘込みに際して掘込口をエツチング除去しておき、
ベヘルiM Ia込み深さを小さくする加工方法とした
ため、ベベル11η掘込みに層の欠け、溝変形を少なく
してベベル角度ら所期のものを得ることができ、素子耐
圧の向上を容易にして歩溜まり良く製造できろ効果があ
る。G Effect of the invention As described above, according to the method of the present invention, Heher'tl+1
When digging in step 1, remove the digging opening by etching,
By using a processing method that reduces the depth of bevel iM Ia, it is possible to obtain the desired bevel angle by reducing layer chipping and groove deformation in the bevel 11η digging, making it easier to improve the element withstand voltage. It has the effect of being able to manufacture products with good yields.
第1図は本発明方法の一実施例を示す要部断面構造図、
第2図及び第3図は本発明の他の実施例を示ず要部断面
構造図、第4図はベベル溝加工をした電力用サイリスク
構造図、第5図は従来のベベル溝構造図である。
2・・・アノード電極、3・・・カソード電極、4・・
・ゲート電極、5・・・ベベル溝。
第1図 第2図
第3図FIG. 1 is a cross-sectional structural diagram of main parts showing an embodiment of the method of the present invention;
Figures 2 and 3 are cross-sectional structural diagrams of the main parts without showing other embodiments of the present invention, Figure 4 is a diagram of the structure of a power silisk with bevel grooves, and Figure 5 is a diagram of the conventional bevel groove structure. be. 2... Anode electrode, 3... Cathode electrode, 4...
- Gate electrode, 5... bevel groove. Figure 1 Figure 2 Figure 3
Claims (1)
おいて、ベベル溝加工の掘込表面を予め所定深さエッチ
ングによって除去し、この除去した素子表面からベベル
溝加工の掘込みを行うようにしたことを特徴とする半導
体素子の接合表面加工方法。When processing a bevel groove on a PN junction surface of a power semiconductor element, the surface into which the bevel groove is to be processed is removed by etching to a predetermined depth in advance, and the bevel groove is dug from the removed element surface. A method for processing a bonding surface of a semiconductor device, characterized by:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7482486A JPS62232165A (en) | 1986-04-01 | 1986-04-01 | Bonding-surface machining method for semiconductor element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7482486A JPS62232165A (en) | 1986-04-01 | 1986-04-01 | Bonding-surface machining method for semiconductor element |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62232165A true JPS62232165A (en) | 1987-10-12 |
Family
ID=13558449
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7482486A Pending JPS62232165A (en) | 1986-04-01 | 1986-04-01 | Bonding-surface machining method for semiconductor element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62232165A (en) |
-
1986
- 1986-04-01 JP JP7482486A patent/JPS62232165A/en active Pending
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