JP3253372B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
JP3253372B2
JP3253372B2 JP28364192A JP28364192A JP3253372B2 JP 3253372 B2 JP3253372 B2 JP 3253372B2 JP 28364192 A JP28364192 A JP 28364192A JP 28364192 A JP28364192 A JP 28364192A JP 3253372 B2 JP3253372 B2 JP 3253372B2
Authority
JP
Japan
Prior art keywords
semiconductor substrate
semiconductor device
bevel
end surface
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP28364192A
Other languages
Japanese (ja)
Other versions
JPH06120483A (en
Inventor
洋明 坂本
Original Assignee
日本インター株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本インター株式会社 filed Critical 日本インター株式会社
Priority to JP28364192A priority Critical patent/JP3253372B2/en
Publication of JPH06120483A publication Critical patent/JPH06120483A/en
Application granted granted Critical
Publication of JP3253372B2 publication Critical patent/JP3253372B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Thyristors (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、ポジティブベベルを有
する半導体装置の製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device having a positive bevel.

【0002】[0002]

【従来の技術】高耐圧ゲートターンオフサイリスタ(以
下、高耐圧GTOと略記する。)等の電力用半導体装置
においては、シリコン半導体基板表面の空乏層をできる
だけ広げるようにポジティブベベル構造を採用してい
る。この構造を備えた半導体装置の一例を図5に示す。
図5において、シリコン半導体基板1には、PNPNの
4層が周知の拡散工程等を経て形成され、高耐圧GTO
構造となっている。このシリコン半導体基板1の一方の
主面側には、アノード電極となる温度補償板2が合金・
固着されている。また、シリコン半導体基板1の他方の
主面側には、カソード電極となる温度補償板3が載置さ
れる。上記シリコン半導体基板1の他方の主表面から所
定の角度(ベベル角度)でベベル溝4が切り込まれてい
る。このベベル加工方法としては、サンドブラスト法、
ダイヤモンドソーによる切削加工法等があり、これらの
方法によりPN接合部の空乏層を広げるためにベベル溝
4が形成される。
2. Description of the Related Art In a power semiconductor device such as a high-breakdown-voltage gate turn-off thyristor (hereinafter abbreviated as a high-breakdown-voltage GTO), a positive bevel structure is adopted so that a depletion layer on the surface of a silicon semiconductor substrate is expanded as much as possible. . FIG. 5 shows an example of a semiconductor device having this structure.
In FIG. 5, four layers of PNPN are formed on a silicon semiconductor substrate 1 through a well-known diffusion process and the like, and a high breakdown voltage GTO is formed.
It has a structure. On one main surface side of the silicon semiconductor substrate 1, a temperature compensating plate 2 serving as an anode electrode is made of an alloy.
It is fixed. On the other main surface side of the silicon semiconductor substrate 1, a temperature compensating plate 3 serving as a cathode electrode is mounted. A bevel groove 4 is cut at a predetermined angle (bevel angle) from the other main surface of the silicon semiconductor substrate 1. As this bevel processing method, sand blast method,
There is a cutting method using a diamond saw, etc., and the bevel groove 4 is formed by these methods in order to widen the depletion layer at the PN junction.

【0003】[0003]

【発明が解決しようとする課題】従来では、上記のベベ
ル溝4を形成するのに、一般にサンドブラスト法あるい
はダイヤモンドソーによる切削加工法を利用するために
次のような問題があった。すなわち、サンドブラスト法
よってベベル溝4を形成する場合には、その方法を実施
するために使用する研磨材の跳ね返り等により形状不安
定要素があり、図6に示すように、ベベル溝4の口縁部
5A,5Bのだれが生じる欠点があった また、ダイヤ
モンドソーを利用する切削加工法にあっては、ダイヤモ
ンドソーの欠損及び磨耗等により表面からの観察では異
常がみられないが、図7に示すようにベベル溝4の内部
にはソーマーク6が形成されたり、劈開部7が生じたり
する。このため、高電圧印加時に異常な電界分布が生じ
半導体装置が破壊され易いという解決すべき課題があっ
た。
Heretofore, the following problems have conventionally been encountered because the above-described bevel groove 4 is generally formed by a sandblasting method or a cutting method using a diamond saw. That is, in the case of forming a bevel groove 4 I'm sandblast method, there is a shape instability by rebound or the like of the abrasive material used for implementing the method, as shown in FIG. 6, the rim of the bevel groove 4 Department
5A and 5B had a disadvantage . In the cutting method using a diamond saw, no abnormality is observed from the surface due to chipping or wear of the diamond saw, but a saw mark 6 is provided inside the bevel groove 4 as shown in FIG. Is formed, or the cleavage portion 7 is generated. Therefore, there is a problem to be solved that an abnormal electric field distribution occurs when a high voltage is applied, and the semiconductor device is easily broken.

【0006】[0006]

【発明の目的】本発明は、上記のような課題を解決する
ためになされたもので、ベベル溝内にソーマークや劈開
部が形成されるおそれがなく、高電圧印加時においても
異常な電界分布を生じず、高耐圧、高信頼性を長期間安
定して保持できる半導体装置の製造方法を提供すること
を目的とするものである。
SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and has no fear that a saw mark or a cleavage portion is formed in a bevel groove, and an abnormal electric field distribution even when a high voltage is applied. It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of maintaining high breakdown voltage and high reliability stably for a long time without causing the problem.

【0007】[0007]

【問題点を解決する手段】本発明の半導体装置の第1の
製造方法は、ポジティブベベル構造を有する半導体装置
の製造方法において、シリコン半導体基板端面のベベル
角度よりも小さな傾斜角度を有するように端面を傾斜さ
せた温度補償板を該半導体基板と合金・固着させた後、
該半導体基板の端面を研磨手段によりベベリング加工す
ることを特徴とするものである。本発明の半導体装置の
第2の製造方法は、ポジティブベベル構造を有する半導
体装置の製造方法において、シリコン半導体基板端面の
ベベル角度よりも小さな傾斜角度を有するように端面を
傾斜させ、かつ、該端面の傾斜面に連続して段差部を形
成した温度補償板を該半導体基板と合金・固着させた
後、該半導体基板の端面を研磨手段によりベベリング加
工することを特徴とするものである。
A first method of manufacturing a semiconductor device according to the present invention is directed to a method of manufacturing a semiconductor device having a positive bevel structure, wherein an end surface of the silicon semiconductor substrate has an inclination angle smaller than a bevel angle of the end surface. After bonding the semiconductor substrate and the semiconductor substrate with the temperature compensating plate inclined,
The end face of the semiconductor substrate is beveled by a polishing means. The second method of manufacturing a semiconductor device of the present invention is a method of manufacturing a semiconductor device having a positive bevel structure, it is inclined end face so as to have a smaller inclination angle than the bevel angle of the silicon semiconductor substrate end face and the end face Steps are formed continuously on the inclined surface of
After the formed temperature compensating plate is alloyed and fixed to the semiconductor substrate, the end face of the semiconductor substrate is beveled by a polishing means.

【0008】[0008]

【作用】本発明の半導体装置の第1及び第2の製造方法
においては、あらかじめ温度補償板の端面に所定の傾斜
角度を付してあるので、研磨手段により表面のきわめて
滑らかな傾斜面を形成することができ、電界集中による
半導体装置の破壊等が避けられ、高耐圧、高信頼性を長
期間維持することができる。
In the first and second manufacturing methods of the semiconductor device according to the present invention, since the end surface of the temperature compensating plate is given a predetermined inclination angle in advance, an extremely smooth inclined surface is formed by the polishing means. Thus, breakdown of the semiconductor device due to electric field concentration can be avoided, and high breakdown voltage and high reliability can be maintained for a long time.

【0009】[0009]

【実施例】以下に、本発明の実施例を説明する。本発明
では、図1に示すようにシリコン半導体基板1にアルミ
箔8を介して合金・固着させるモリブデン等からなる温
度補償板2の外周面を、あらかじめ傾斜面2aとなるよ
うに加工しておくことを特徴とするものである。この傾
斜加工によって付された傾斜角度をここではθ1とす
る。次に、上記の温度補償板2を通常のようにアルミ箔
2を介して合金・固着させる。その後、例えば、図2に
示すようなレンズ研磨時に使用されるベベリング皿9を
用いて研磨材10を供給しながらシリコン半導体基板1
の端面を所定の傾斜角θ2となるように研磨する。この
場合、θ1<θ2とすることにより温度補償板2の外周
面がベベリング皿9の内壁に接触しないため、シリコン
半導体基板1の端面のみの表面を滑らかなベベル加工面
1aとすることができる。
Embodiments of the present invention will be described below. In the present invention, as shown in FIG. 1, the outer peripheral surface of a temperature compensating plate 2 made of molybdenum or the like to be alloyed and fixed to a silicon semiconductor substrate 1 via an aluminum foil 8 is processed in advance so as to be an inclined surface 2a. It is characterized by the following. Here, the inclination angle given by the inclination processing is set to θ1. Next, the temperature compensating plate 2 is alloyed and fixed via the aluminum foil 2 as usual. Thereafter, for example, the silicon semiconductor substrate 1 is supplied while supplying an abrasive 10 using a beveling dish 9 used at the time of lens polishing as shown in FIG.
Is polished so as to have a predetermined inclination angle θ2. In this case, since θ1 <θ2, the outer peripheral surface of the temperature compensating plate 2 does not contact the inner wall of the beveling plate 9, so that only the end surface of the silicon semiconductor substrate 1 can be a smooth beveled surface 1a.

【0010】上記の方法でシリコン半導体基板1を加工
した後の半導体装置を図3に示す。この半導体装置は、
PE層、NB層、PB層、NE層の4層構造を有する高
耐圧GTOである。なお、図中、11はPE層からNB
層に突き抜けるように選択拡散により形成したアノード
ショート部である。また、上記の傾斜角度θ1は、温度
補償板の板厚によって適宜決定されるが、本発明の第1
の実施例の場合、θ1<40度とした。この場合に、シ
リコン半導体基板1に対するベベリング加工による傾斜
角度θ2は45度とした。以上によりシリコン半導体基
板1の外周面には所期の傾斜角度θ2を付すことがで
き、従来のような切削加工によるベベル溝の形成と異な
り、きわめて表面の滑らかな端面研磨加工ができるた
め、電界集中による半導体装置の破壊等が効果的に防止
される。次に、本発明の第2の実施例を図4に示す。こ
の実施例では、温度補償板2の外周面に傾斜角度θ1を
持つ傾斜面2aに連続して段差部2bを形成し、ベベリ
ング皿9の湾曲内周面に対する逃げをより大きくとるよ
うにしたものである。この場合においてもθ1<θ2の
関係を有する。これによりシリコン半導体基板1の端面
研磨が容易となる利点を有する。なお、上記第1及び第
2の実施例において、シリコン半導体基板1の端面研磨
手段としてベベリング皿9を使用する方法を示したが、
必ずしもベベリング皿によることなく表面が滑らかに仕
上げることができる他の研磨手段であっても良い。
FIG. 3 shows a semiconductor device after processing the silicon semiconductor substrate 1 by the above method. This semiconductor device
It is a high breakdown voltage GTO having a four-layer structure of a PE layer, an NB layer, a PB layer, and an NE layer. In the figure, 11 is the NB from the PE layer .
An anode short portion formed by selective diffusion so as to penetrate the layer . Further, the above-mentioned inclination angle θ1 is appropriately determined depending on the thickness of the temperature compensating plate.
In the case of the embodiment, θ1 <40 degrees. In this case, the inclination angle θ2 of the silicon semiconductor substrate 1 by beveling was set to 45 degrees. As described above, the desired inclination angle θ2 can be given to the outer peripheral surface of the silicon semiconductor substrate 1, and unlike the conventional formation of bevel grooves by cutting, extremely smooth end surface polishing can be performed. Destruction of the semiconductor device due to concentration is effectively prevented. Next, a second embodiment of the present invention is shown in FIG. In this embodiment, a step portion 2b is formed on the outer peripheral surface of the temperature compensating plate 2 continuously with the inclined surface 2a having the inclination angle θ1, so that the relief of the beveling plate 9 from the curved inner peripheral surface is made larger. It is. Also in this case, there is a relationship of θ1 <θ2. Thereby, there is an advantage that polishing of the end face of the silicon semiconductor substrate 1 becomes easy. In the first and second embodiments, the method using the beveling plate 9 as the end surface polishing means of the silicon semiconductor substrate 1 has been described.
Other polishing means that can finish the surface smoothly without necessarily using a beveling dish may be used.

【0011】[0011]

【発明の効果】以上のように、本発明によれば、ポジテ
ィブベベル構造を有する半導体装置の製造方法におい
て、シリコン半導体基板のベベル角度よりも小さな角度
に端面を傾斜させた温度補償板若しくは同じく端面を傾
斜させるとともに、外周部に段差部を形成した温度補償
板を合金・固着させた後、シリコン半導体基板の端面を
ベベリング皿等の研磨手段によりベベリング加工するよ
うにしたので、表面のきわめて滑らかな傾斜面を形成す
ることができ、電界集中による半導体装置の破壊等が避
けられ、高耐圧、高信頼性を長期間維持することができ
半導体装置が得られる。
As described above, according to the present invention, in a method of manufacturing a semiconductor device having a positive bevel structure, a temperature compensating plate whose end face is inclined to an angle smaller than the bevel angle of a silicon semiconductor substrate, or a similar end face is used. Tilt
After the temperature compensating plate having a stepped portion formed on the outer periphery is alloyed and fixed, the end face of the silicon semiconductor substrate is beveled by a polishing means such as a beveling dish, so that the surface has a very smooth slope. A surface can be formed, the semiconductor device can be prevented from being broken due to electric field concentration, and a semiconductor device which can maintain high breakdown voltage and high reliability for a long time can be obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の半導体装置の製造方法を実施するため
に温度補償板の外周部に傾斜角度を付した状態の第1の
実施例を示す側面図を示す。
FIG. 1 is a side view showing a first embodiment in which an outer peripheral portion of a temperature compensating plate is provided with an inclination angle in order to carry out a method of manufacturing a semiconductor device of the present invention.

【図2】上記温度補償板を合金・固着させたシリコン半
導体基板の端面に傾斜角度を付すためにベベリング皿を
用いて研磨加工する状態の断面図を示す。
FIG. 2 is a cross-sectional view showing a state in which a polishing process is performed using a beveling dish in order to give an inclination angle to an end surface of a silicon semiconductor substrate on which the temperature compensation plate is alloyed and fixed.

【図3】ベベリング皿により研磨加工した後の半導体装
置の側面図を示す。
FIG. 3 is a side view of the semiconductor device after being polished by a beveling dish.

【図4】温度補償板の外周面に傾斜角度及び段差部を設
けた本発明の第2の実施例の側面図を示す。
FIG. 4 is a side view of a second embodiment of the present invention in which an inclination angle and a step portion are provided on an outer peripheral surface of a temperature compensating plate.

【図5】 従来のベベル加工方法を説明するための側面図
を示す。
FIG. 5 is a side view for explaining a conventional bevel processing method.

【図6】 従来のサンドブラスト法によって形成されたベ
ベル溝のだれを説明するための側面図を示す。
FIG. 6 is a side view for explaining the droop of a bevel groove formed by a conventional sandblast method.

【図7】 従来の切削加工法によって形成されたベベル溝
内のソーマーク及び劈開部を説明するための側面図を示
す。
Figure 7 shows a side view for explaining a saw marks and cleavage of a conventional cutting method thus formed bevel groove.

【符号の説明】[Explanation of symbols]

1 シリコン半導体基板 1a ベベル加工面 2 温度補償板 2a 傾斜面 3 温度補償板 4 ベベル溝5a,5b 口縁部 6 ソーマーク 7 劈開部 8 アルミ箔 9 ベベリング皿 10 研磨材 θ1 温度補償板2の外周面に付された傾斜角度 θ2 シリコン半導体基板1の外周面に付されたベベル
角度
DESCRIPTION OF SYMBOLS 1 Silicon semiconductor substrate 1a Bevel processing surface 2 Temperature compensator 2a Inclined surface 3 Temperature compensator 4 Edge of bevel groove 5a, 5b 6 Saw mark 7 Cleavage part 8 Aluminum foil 9 Beveling dish 10 Abrasive material Outer peripheral surface of temperature compensator 2 The bevel angle attached to the outer peripheral surface of the silicon semiconductor substrate 1

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】ポジティブベベル構造を有する半導体装置
の製造方法において、 シリコン半導体基板端面のベベル角度よりも小さな傾斜
角度を有するように端面を傾斜させた温度補償板を該半
導体基板と合金・固着させた後、該半導体基板の端面を
研磨手段によりベベリング加工することを特徴とする半
導体装置の製造方法。
In a method of manufacturing a semiconductor device having a positive bevel structure, a temperature compensating plate whose end surface is inclined so as to have an inclination angle smaller than a bevel angle of an end surface of a silicon semiconductor substrate is alloyed and fixed to the semiconductor substrate. And then subjecting the end face of the semiconductor substrate to beveling processing by a polishing means.
【請求項2】ポジティブベベル構造を有する半導体装置
の製造方法において、 シリコン半導体基板端面のベベル角度よりも小さな傾斜
角度を有するように端面を傾斜させ、かつ、該端面の傾
斜面に連続して段差部を形成した温度補償板を該半導体
基板と合金・固着させた後、該半導体基板の端面を研磨
手段によりベベリング加工することを特徴とする請求項
1に記載の半導体装置の製造方法。
2. A method of manufacturing a semiconductor device having a positive bevel structure, comprising: tilting an end surface of a silicon semiconductor substrate so as to have an inclination angle smaller than a bevel angle of the end surface;
2. The semiconductor device according to claim 1, wherein a temperature compensating plate having a step portion formed continuously on the slope is alloyed and fixed to the semiconductor substrate, and then the end surface of the semiconductor substrate is beveled by polishing means. Manufacturing method.
JP28364192A 1992-09-30 1992-09-30 Method for manufacturing semiconductor device Expired - Lifetime JP3253372B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28364192A JP3253372B2 (en) 1992-09-30 1992-09-30 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28364192A JP3253372B2 (en) 1992-09-30 1992-09-30 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH06120483A JPH06120483A (en) 1994-04-28
JP3253372B2 true JP3253372B2 (en) 2002-02-04

Family

ID=17668155

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28364192A Expired - Lifetime JP3253372B2 (en) 1992-09-30 1992-09-30 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP3253372B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6232229B1 (en) * 1999-11-19 2001-05-15 Micron Technology, Inc. Microelectronic device fabricating method, integrated circuit, and intermediate construction

Also Published As

Publication number Publication date
JPH06120483A (en) 1994-04-28

Similar Documents

Publication Publication Date Title
US7964475B2 (en) Semiconductor wafer, method of manufacturing the same and semiconductor device
US6342433B1 (en) Composite member its separation method and preparation method of semiconductor substrate by utilization thereof
US4325182A (en) Fast isolation diffusion
US5110764A (en) Method of making a beveled semiconductor silicon wafer
CN1255237A (en) Controlled cleavage process
US11848225B2 (en) Apparatus for edge trimming of semiconductor wafers
US4822757A (en) Semiconductor device and method of manufacturing the same
EP0354449A2 (en) Semiconductor single crystal substrate
US20230330769A1 (en) Parent Substrate, Wafer Composite and Methods of Manufacturing Crystalline Substrates and Semiconductor Devices
JP2010016188A (en) Method of manufacturing semiconductor device, and semiconductor device
JP2023519165A (en) Method for manufacturing a composite structure comprising a thin layer made of monocrystalline SiC on a carrier substrate made of SiC
US4097310A (en) Method of forming silicon solar energy cells
US20040121557A1 (en) Method of smoothing the outline of a useful layer of material transferred onto a support substrate
JP3352129B2 (en) Semiconductor substrate manufacturing method
JP3253372B2 (en) Method for manufacturing semiconductor device
US7956441B2 (en) Method of increasing the area of a useful layer of material transferred onto a support
JPH05226305A (en) Manufacture of laminated wafer
JP2011054914A (en) Manufacturing method of semiconductor device and semiconductor wafer
JP2001177096A (en) Vertical semiconductor device, and manufacturing method thereof
JP7429080B1 (en) Semiconductor crystal wafer manufacturing equipment and manufacturing method
EP1523773B1 (en) Method of smoothing the outline of a useful layer of material transferred onto a support substrate
JPH0246716A (en) Silicon wafer
JPH0342853A (en) Manufacture of semiconductor device for power, and core drill for parting semiconductor chip
JP2886271B2 (en) Method of manufacturing semiconductor device and grinding wheel
JP2024066612A (en) Wafer processing method

Legal Events

Date Code Title Description
R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101122

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111122

Year of fee payment: 10

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121122

Year of fee payment: 11

EXPY Cancellation because of completion of term