WO2023286692A1 - Semiconductor wafer - Google Patents
Semiconductor wafer Download PDFInfo
- Publication number
- WO2023286692A1 WO2023286692A1 PCT/JP2022/027018 JP2022027018W WO2023286692A1 WO 2023286692 A1 WO2023286692 A1 WO 2023286692A1 JP 2022027018 W JP2022027018 W JP 2022027018W WO 2023286692 A1 WO2023286692 A1 WO 2023286692A1
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- WO
- WIPO (PCT)
- Prior art keywords
- protective film
- semiconductor wafer
- semiconductor substrate
- semiconductor
- outer edge
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 148
- 230000001681 protective effect Effects 0.000 claims abstract description 100
- 239000004020 conductor Substances 0.000 claims abstract description 63
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 239000011229 interlayer Substances 0.000 claims abstract description 29
- 238000005530 etching Methods 0.000 claims description 20
- 239000010410 layer Substances 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 238000007747 plating Methods 0.000 description 40
- 238000000034 method Methods 0.000 description 39
- 239000000126 substance Substances 0.000 description 21
- 238000004519 manufacturing process Methods 0.000 description 18
- 230000002093 peripheral effect Effects 0.000 description 11
- 230000015572 biosynthetic process Effects 0.000 description 8
- 230000004048 modification Effects 0.000 description 7
- 238000012986 modification Methods 0.000 description 7
- 239000000853 adhesive Substances 0.000 description 5
- 230000001070 adhesive effect Effects 0.000 description 5
- 230000007547 defect Effects 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 239000004743 Polypropylene Substances 0.000 description 2
- 239000012467 final product Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 229920000139 polyethylene terephthalate Polymers 0.000 description 2
- 239000005020 polyethylene terephthalate Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- -1 polypropylene Polymers 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 229920001971 elastomer Polymers 0.000 description 1
- 239000000806 elastomer Substances 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229920001155 polypropylene Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Images
Classifications
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/02—Electroplating of selected surface areas
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D7/00—Electroplating characterised by the article coated
- C25D7/12—Semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Definitions
- the present disclosure relates to a semiconductor wafer with semiconductor elements.
- the surface of the semiconductor wafer is covered with a protective film such as polyimide, and then plating is performed to form a metal plating layer on the surface of the electrodes. ing. Since the permeation of the chemical solution may occur at the outer edge of the semiconductor wafer during the plating process, the permeation of the chemical solution is suppressed by attaching a protective tape to the outer edge of the semiconductor wafer (see Patent Document 1).
- the present disclosure provides a semiconductor wafer having a structure that does not require an additional step, can be easily peeled off after plating, and can accurately suppress permeation of a chemical solution during plating, and a semiconductor device using the same.
- the object is to provide a manufacturing method.
- a semiconductor wafer includes a semiconductor substrate on which semiconductor elements are formed, and an interlayer insulating film formed on the semiconductor substrate and having a plurality of contact holes at least partially connected to predetermined positions of the semiconductor elements. a film, a plurality of conductor plugs embedded in a plurality of contact holes, a surface electrode formed inside an outer edge of a semiconductor substrate and connected to at least a portion of the plurality of conductor plugs, and one of the surface electrodes.
- the protective film covering the interlayer insulating film and the conductor plug outside the surface electrode, the outer peripheral edge of the semiconductor substrate, and the outer edge of the semiconductor substrate.
- the film has a side protection tape attached to the outer edge of the protective film at the outer edge, and a plated layer formed on the surface of the portion of the surface electrode exposed from the protective film.
- the area of the protective film that is attached to the side surface protective tape is outside the area that covers the surface electrode of the protective film.
- the area of the protective film attached to the side surface protective tape is outside the area covering the surface electrode of the protective film, thereby preventing the outer edge of the protective film and the side surface of the protective film. It can be adhered to the protective tape without gaps.
- FIG. 3 is a cross-sectional view of the outer peripheral side of the semiconductor wafer according to the first embodiment;
- FIG. 4 is a flow chart showing a manufacturing process of a semiconductor device;
- FIG. 3 is a cross-sectional view of the outer peripheral side of a semiconductor wafer shown as a comparative example;
- FIG. 10 is a cross-sectional view showing a structure in which a contact hole in which a conductor plug is arranged is stopped by a low etching rate member according to the second embodiment; It is sectional drawing at the time of separating and arrange
- FIG. 11 is an enlarged cross-sectional view of the vicinity of a conductor plug according to a modification of the second embodiment;
- FIG. 11 is an enlarged cross-sectional view of the vicinity of a conductor plug according to a modification of the second embodiment;
- FIG. 11 is an enlarged cross-sectional view of the vicinity of a conductor plug according to a modification of the
- the configuration of a semiconductor wafer 1 according to this embodiment will be described with reference to FIG. It should be noted that the semiconductor wafer 1 shown in FIG. 1 has been plated, and is in a state in which a side surface protection tape 70, which will be described later, is attached to the outer edge. In other words, it shows the semiconductor wafer 1 at an intermediate stage when a semiconductor device manufacturing process, which will be described later, is performed, and the semiconductor device is manufactured by performing the remaining part of the manufacturing process.
- a semiconductor wafer 1 includes a semiconductor substrate 10 in which semiconductor elements (not shown) are formed, an interlayer insulating film 20 and conductor plugs 30 formed on the semiconductor substrate 10, a surface electrode 40 and a protective film 50. , a plating layer 60 and a side protection tape 70 .
- the semiconductor substrate 10 is in the form of a wafer, and semiconductor elements are formed by performing a semiconductor element manufacturing process in advance. Although the detailed structure is not shown here, semiconductor elements are formed in a predetermined layout in effective regions taken out as chips from the semiconductor wafer 1 . Although any semiconductor element may be formed on the semiconductor substrate 10, for example, a vertical MOSFET having a trench gate structure is formed. When a vertical MOSFET having a trench gate structure is formed as a semiconductor element, each chip arranged in the effective region has a vertical trench gate structure in which a plurality of trench gate structures are arranged in stripes with one direction being the longitudinal direction. A type MOSFET is formed.
- the interlayer insulating film 20 is formed so as to cover the surface side of the semiconductor substrate 10 on which semiconductor elements are formed, and is composed of a silicon oxide film or the like.
- a plurality of contact holes 21 are formed in the interlayer insulating film 20, and at least some of them expose predetermined positions of the semiconductor element.
- the contact hole 21 is formed as a source contact hole leading to a high-concentration p-type contact layer in the n-type source region or the base region.
- gate contact holes are also formed as contact holes 21 leading to gate liners drawn out from the gate electrodes provided in each trench gate structure.
- the conductor plugs 30 are embedded in the plurality of contact holes 21 and electrically connected to each exposed portion in the contact holes 21 .
- the conductor plug 30 is made of a metal conductor such as tungsten (W), and is formed from the surface of the interlayer insulating film 20 in which the contact hole 21 is formed to the surface of the semiconductor substrate 10 .
- the conductor plugs 30 are separated from each other by being surrounded by the interlayer insulating film 20 .
- the surface electrodes 40 are various electrodes that are electrically connected to predetermined positions of the semiconductor element by being electrically connected to the conductor plugs 30, and are made of an Al (aluminum)-based electrode material, for example.
- Al aluminum
- a gate pad including a source electrode and a gate wiring layer is formed as the surface electrode 40, and the surface electrode 40 is formed into a predetermined shape so that these are electrically separated. Patterned.
- the surface electrode 40 is formed in an effective region of the semiconductor wafer 1 to be taken out as a chip, and is not formed at least in the vicinity of the outer edge of the semiconductor wafer 1 .
- the area within a predetermined distance from the outer peripheral edge of the semiconductor wafer 1 is a region where the surface electrode 40 is not formed. In regions where the surface electrodes 40 are not formed, the interlayer insulating film 20 and the conductor plugs 30 are exposed from the surface electrodes 40 .
- the protective film 50 covers at least a portion of the surface electrode 40 and covers and protects the portions of the interlayer insulating film 20 and the conductor plugs 30 exposed from the surface electrode 40, and is made of polyimide, for example. be done.
- the protective film 50 is formed so as to cover the outer edge of each surface electrode 40 formed in the effective area of the semiconductor wafer 1 .
- the protective film 50 is also formed in an ineffective area of the semiconductor wafer 1 which is not taken out as a chip, that is, an area arranged so as to surround the effective area. In the effective region, the surface electrode 40 and other patterns are formed to form unevenness on the surface.
- the protective film 50 directly covers the interlayer insulating film 20 and the conductor plugs 30, and the surface of the protective film 50 is almost flat with no unevenness.
- the flat surface without unevenness means that there is no unevenness due to the thickness of the surface electrode 40, and the variation in film thickness that occurs when forming the protective film 50 and the interlayer insulating film 20 and the interlayer insulating film 20 This does not mean that there is no unevenness due to the surface roughness of the conductor plug 30 .
- the surface without unevenness caused by the thickness of the surface electrode 40 is called a flat surface without unevenness.
- the protective film 50 may be formed up to the outer peripheral edge of the semiconductor wafer 1 , but here the outer peripheral edge of the protective film 50 is located inside the outer peripheral edge of the semiconductor wafer 1 .
- the plated layer 60 is formed on the surface of the portion of the surface electrode 40 exposed from the protective film 50 .
- the plating layer 60 is formed by plating, for example, a barrier metal material or a material that improves bonding properties.
- the plating layer 60 is made of Ni (nickel).
- the plating layer 60 is formed in a state in which the side surface of the semiconductor substrate 10 and the outer edge of the protective film 50 are covered with a side surface protective tape 70 or the like.
- the side surface protection tape 70 is attached to the semiconductor substrate 10 so as to cover the side surface of the semiconductor substrate 10 , that is, the outer peripheral edge and the predetermined range of the outer edge portion, and the entire circumference of the inner peripheral portion is attached to the protective film 50 .
- the side protection tape 70 may be made of any material that is used for semiconductor plating, such as elastomer composition, PP (polypropylene), PET (polyethylene terephthalate), silicone, and UV tape. .
- the side protection tape 70 is applied to the outer edge of the semiconductor substrate 10, the exposed portions at the outer edge of the interlayer insulating film 20 and the conductor plugs 30, and the predetermined range of the outer edge located inside from the outer edge of the protective film 50. are kept in close contact.
- the inner peripheral side of the side surface protective tape 70 is in close contact with the outer edge portion of the protective film 50 having a flat surface, and only the region of the protective film 50 where no pattern is formed. It is in close contact and is not in close contact with the region where the pattern is formed. That is, the area of the protective film 50 to which the side surface protective tape 70 is attached is only the area outside the portion of the protective film 50 covering the surface electrode 40 . Therefore, the side surface protective tape 70 is in close contact with the area of the protective film 50 where there is no unevenness on the surface.
- a surface element structure forming step is performed. That is, a manufacturing process for forming semiconductor elements is performed on the semiconductor substrate 10 in the form of a wafer, and various processes are performed on the front surface side of the semiconductor substrate 10 . If an n-channel type vertical MOSFET is to be formed as a semiconductor element, the formation process of each part for constituting the vertical MOSFET is performed.
- an n-type semiconductor substrate 10 formation of an n-type drift layer, formation of a p-type base region, formation of an n-type source region and a high-concentration p-type contact layer, formation of a gate trench, formation of a gate insulating film, formation of a gate electrode, and Various processes such as forming are performed. Thereby, a semiconductor element is formed on the semiconductor substrate 10 . Further, steps of forming the interlayer insulating film 20 and the conductor plugs 30, forming the surface electrodes 40, and further forming the protective film 50 are performed.
- step S105 a step of attaching a surface protection tape (not shown) is performed. That is, the surface protection tape is attached so as to cover the entire surface of the semiconductor wafer 1 .
- step S110 the back side of the semiconductor wafer 1 is ground by a predetermined thickness to reduce the thickness of the semiconductor wafer 1 by performing a back grinding step.
- the back side etching process of the semiconductor wafer 1 is performed as step S115 to planarize the back side of the semiconductor wafer 1 and remove damage.
- a surface protective tape peeling step is performed as step S120 to peel the surface protective tape from the surface of the semiconductor wafer 1.
- step S125 the sample is placed in a sputtering device or the like, and a back surface electrode forming step of forming an electrode on the back surface of the semiconductor wafer 1 is performed. If a vertical MOSFET is formed as a semiconductor element, this back surface electrode becomes a drain electrode.
- step S130 a step of attaching a back surface protective tape (not shown) is performed. That is, the back surface protective tape is attached to the back surface of the semiconductor wafer 1 . Further, in step S135, a step of attaching the side surface protection tape is performed to attach the side surface protection tape 70 so as to cover the side surface of the semiconductor wafer 1, that is, the outer peripheral edge and the outer edge portion of the protective film 50. FIG. At this time, the protective film 50 and the side protective tape 70 are in close contact with each other without a gap.
- step S140 the surface plating process is performed while the side surface and the back surface of the semiconductor wafer 1 are covered with the side surface protection tape 70 and the back surface protection tape.
- the plated layer 60 of Ni layer is formed on the surface of the portion of the surface electrode 40 exposed from the protective film 50 .
- FIG. 1 shows the state in which the plating layer 60 is formed in this manner.
- the sample is immersed in a chemical solution during the surface plating treatment, but since the protective film 50 and the side surface protective tape 70 are in close contact with each other without any gap, the chemical solution penetrates into the side surface protective tape 70. can be suppressed precisely.
- such permeation suppression of the chemical solution is performed only by making the outer edge portion of the protective film 50 a structure without unevenness and pattern formation. For this reason, unlike the technique of improving adhesion by vacuuming after the side surface protective tape 70 is attached, no additional processing is required.
- step S145 a peeling process of the side surface protective tape 70 and a peeling process of the back surface protective tape are performed in order.
- step S155 the process of attaching the back surface protective tape is performed again to attach the dicing tape to the back surface of the semiconductor wafer 1.
- step S160 a dicing process is performed as step S160 to divide the semiconductor wafer 1 into chips, and then a back surface protective tape peeling process is performed as step S165 to peel off the respective chips from the back surface protective tape to separate the chips. is formed.
- a chipped semiconductor device can be manufactured.
- the outer edge portion to which the side protective tape 70 is attached is a flat surface on which no pattern is formed. Therefore, the outer edge portion of the protective film 50 and the side surface protective tape 70 can be brought into close contact without any gap.
- FIG. 3 shows that the surface electrode 40 is formed all over the surface with the same thickness, it is actually patterned to form unevenness corresponding to the thickness.
- the side surface protection tape 70 is attached to the protective film 50 having no irregularities on the surface, the outer edge portion of the protection film 50 and the side surface protection tape 70 are closely attached without any gap. Let me.
- the semiconductor wafer 1 can have a structure that does not require an additional step, can be easily peeled off after the plating process, and can accurately suppress penetration of the chemical solution during the plating process. By manufacturing a semiconductor device using such a semiconductor wafer 1, it is possible to suppress the occurrence of defects due to permeation of the chemical during plating, such as chemical residue.
- the permeation of the chemical solution at the outer edge of the semiconductor wafer 1 is suppressed during the plating process.
- defects during the plating process are prevented. Suppress.
- the inner region of the semiconductor wafer 1 is formed on the scribe line so that dicing can be easily performed and residue generated during dicing can be prevented from adhering to the final product and causing defects. should be as low as possible. Therefore, it is preferable not to form the surface electrode 40 or to eliminate the protective film 50 on the scribe line. In this case, the interlayer insulating film 20 and the conductor plugs 30 are exposed to the chemical solution on the scribe line during the plating process.
- the conductor plug 30 was exposed to the chemical solution, the plating sometimes adhered to the exposed portion of the conductor plug 30, which could cause the generation of residue in the post-process. It is difficult for the plating to adhere to the surface of the conductor plug 30, but when the plating adheres, it is easy to come off due to its low adhesion and tends to become a residue in the post-process.
- the conductor plugs 30 are not formed on the scribe lines as much as possible, if the alignment marks cannot be formed inside the chip, the alignment marks using the material of the conductor plugs 30 must be formed on the scribe lines.
- the alignment marks formed by the conductor plugs 30 exposed on the scribe lines are electrically connected to the semiconductor substrate 10 during the plating process. As a result, it has been found that plating adheres to the exposed surface of the conductor plug 30 .
- the exposed conductor plug 30 and the semiconductor substrate 10 are separated from each other so that the conductor plug 30 does not come into contact with the semiconductor substrate 10 .
- the conductor plug 30 is separated from the semiconductor substrate 10 and is in an electrically floating state.
- a low etching rate member 22 is placed at the position where the conductor plug 30 is to be formed. I have. By doing so, the contact hole 21 can be prevented from reaching the semiconductor substrate 10 , and the low etching rate member 22 is arranged between the conductor plug 30 and the semiconductor substrate 10 .
- the alignment mark 41 made of the material of the surface electrode 40 and the conductor plug 30 whose surface is exposed are not electrically connected through the semiconductor substrate 10 . Therefore, the adhesion of plating to the exposed surface of the conductor plug 30 is suppressed. Therefore, it is possible to suppress the generation of residues, and it is possible to suppress the occurrence of defects due to the residues adhering to the final product.
- Such a low etching rate member 22 can be made of, for example, polysilicon or SiN (silicon nitride film).
- the method for manufacturing the low etching rate member 22 is arbitrary, and for example, after forming a part of the interlayer insulating film 20, only the low etching rate member 22 is formed and patterned. can.
- the low etching rate member 22 can be formed by sharing the process for forming another portion used for forming the semiconductor element. For example, when forming a vertical MOSFET as a semiconductor element, after forming a gate insulating film on the surface of the semiconductor substrate 10, when forming a gate electrode made of polysilicon thereon, the polysilicon is subjected to low etching. A rate member 22 is formed.
- interlayer insulating film 20 is formed after that, another process used for forming the semiconductor element and the manufacturing process of the low etching rate member 22 can be made common, suppressing an increase in the number of manufacturing processes and shortening the manufacturing process. Simplification can be achieved.
- the protective film 50 is formed on the interlayer insulating film 20 and the conductor plugs 30, the protective film 50 is arranged up to the outer edge of the semiconductor wafer 1, and the side surface protective tape 70 covers the protective film 50. It is designed to be affixed to any surface. This is because, as described above, the side surface protection tape 70 can be adhered to the smooth surface of the protection film 50 without gaps. It is also conceivable to have a structure that does not include up to. In this way, the side protective tape 70 can be adhered to the interlayer insulating film 20 and the conductor plug 30 with little unevenness, so that the side protective tape 70 can be adhered without gaps.
- the protective film 50 is arranged up to the outer edge of the semiconductor wafer 1 as in the first embodiment, and the side surface protective tape 70 is attached to the surface of the protective film 50. It is preferable to do so.
- the low etching rate member 22 is formed on the surface of the semiconductor substrate 10 via a part of the interlayer insulating film 20 or an insulating film such as a gate insulating film. You can also
- the low etching rate member 22 when forming a vertical MOSFET with a trench gate structure as a semiconductor element, can also be configured using a trench gate structure similar to the vertical MOSFET. Specifically, as shown in FIG. 6A, trenches 11 are formed from the surface of the semiconductor substrate 10 at positions where the conductor plugs 30 are to be formed. A low etching rate member 22 made of a polysilicon layer having the same structure as the gate electrode is provided in the trench 11 . In this way, the low etching rate member 22 can be configured with a structure similar to the trench gate structure. Also in this way, another process used for forming the semiconductor element and the manufacturing process of the low etching rate member 22 can be shared, and the manufacturing process can be simplified by suppressing an increase in the number of manufacturing processes.
- a structure in which the trench 11 is formed at the position where the conductor plug 30 is to be formed at the same time as the trench gate structure and the polysilicon layer is not formed in the trench 11 may be employed. That is, the inside of the trench 11 is partially filled with the gate insulating film and the interlayer insulating film 20 so that the thickness of the insulating film substantially becomes thicker at the position where the conductor plug 30 is to be formed than at the portion other than the trench 11 . to In this way, the aspect ratio of the conductor plug 30 until it reaches the semiconductor substrate 10, that is, the ratio of depth to width, can be increased, and the conductor plug 30 can be prevented from coming into contact with the semiconductor substrate 10. You can get the same effect as the form.
- the width dimension of the contact hole 21 is narrowed to reduce the aspect ratio so that the conductor plug 30 formed in the scribe line is narrower than the conductor plug 30 formed in the chip. It should be large, that is, it should have a high aspect ratio. In this way, when the contact hole 21 is formed in the interlayer insulating film 20, the depth of the contact hole 21 formed in the scribe line is greater than that formed in the chip due to the microloading phenomenon. becomes shallower. Therefore, when the conductor plugs 30 are formed, the conductor plugs 30 formed in the scribe line can be prevented from coming into contact with the semiconductor substrate 10, and the same effect as in the second embodiment can be obtained.
- a vertical MOSFET is taken as an example of a semiconductor element, but the semiconductor element is not limited to this, and may be another semiconductor element, or a horizontal semiconductor element that is not a vertical semiconductor element.
- the semiconductor element is not limited to this, and may be another semiconductor element, or a horizontal semiconductor element that is not a vertical semiconductor element.
- a vertical IGBT having a trench gate structure is formed as a semiconductor element, an effect can be obtained that the structures shown in FIGS. 4, 6A and 6B can be formed by sharing the steps in forming the trench gate structure. be done.
- the exposed region where the interlayer insulating film 20 and the conductor plug 30 are exposed from the protective film 50 has been described by taking the region on the scribe line as an example. However, if there is an exposed region other than the region on the scribe line, it is possible to prevent the conductor plug 30 from coming into contact with the semiconductor substrate 10 as the structure shown in the second embodiment and its modification for the exposed region. preferable.
- the method for manufacturing a semiconductor device has been described based on the flowchart shown in FIG. 2, but it is not necessary to perform all the processes shown here.
- the back surface of the semiconductor substrate 10 is not ground, the back surface grinding process and the back surface etching process may be omitted.
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Abstract
According to the present invention, a protective film (50) is formed so as to cover a part of a surface electrode (40) and to extend beyond the surface electrode toward the outer edge of a semiconductor substrate (10); and the protective film (50) is formed so as to cover an interlayer insulating film (20) and a conductor plug (30) on the outside of the surface electrode. The present invention is also provided with a lateral surface protection tape (70) that is bonded to the outer edge of the protective film at the outer periphery of the semiconductor substrate and the outer edge of the semiconductor substrate. In addition, the region of the protective film, the region being bonded to the lateral surface protection tape, is positioned outside a portion of the protective film, the portion covering the surface electrode.
Description
本出願は、２０２１年７月１４日に出願された日本特許出願番号２０２１－１１６５０６号に基づくもので、ここにその記載内容が参照により組み入れられる。
This application is based on Japanese Patent Application No. 2021-116506 filed on July 14, 2021, the contents of which are incorporated herein by reference.
本開示は、半導体素子を備えた半導体ウェハに関するものである。
The present disclosure relates to a semiconductor wafer with semiconductor elements.
従来より、半導体素子を作り込んだ半導体ウェハの表面側に電極を形成したのち、半導体ウェハの表面をポリイミドなどの保護膜で覆い、さらにめっき処理を行って電極の表面に金属めっき層を形成している。めっき処理の際に半導体ウェハの外縁部で薬液の染み込みが生じ得ることから、半導体ウェハの外縁部に保護テープを貼り付け、薬液の染み込みを抑制している（特許文献１参照）。
Conventionally, after forming electrodes on the surface side of a semiconductor wafer on which semiconductor elements are built, the surface of the semiconductor wafer is covered with a protective film such as polyimide, and then plating is performed to form a metal plating layer on the surface of the electrodes. ing. Since the permeation of the chemical solution may occur at the outer edge of the semiconductor wafer during the plating process, the permeation of the chemical solution is suppressed by attaching a protective tape to the outer edge of the semiconductor wafer (see Patent Document 1).
しかしながら、半導体ウェハの表面の凹凸、例えば電極が露出している場所や、保護膜によって覆われている場所、さらには保護膜のみの場所それぞれの間で段差が生じ、その影響で保護テープと半導体ウェハの表面との間に隙間が生じる。このため、保護テープを貼り付けても薬液の染み込みを的確に抑制できない。
However, unevenness on the surface of the semiconductor wafer, for example, a step between the exposed electrode, the protective film, and the protective film alone, causes the protective tape and the semiconductor to become uneven. A gap is generated between the surface of the wafer. For this reason, even if the protective tape is attached, the permeation of the chemical solution cannot be suppressed accurately.
これに対し、保護テープ貼り付け後に真空引き処理を行うことで密着性を向上する手法、テープの糊材質の密着性を増加させる手法などにより、保護テープ内への薬液の染み込みを抑制することが考えられる。しかし、追加の処理のための専用設備が必要となるし、密着性増加により剥離時に糊が残りやすくなるという問題が生じる。
On the other hand, it is possible to suppress the permeation of the chemical solution into the protective tape by improving the adhesiveness by vacuuming after attaching the protective tape, or by increasing the adhesiveness of the adhesive material of the tape. Conceivable. However, there is a problem that dedicated equipment for additional treatment is required, and the increased adhesiveness tends to leave adhesive behind when peeled off.
本開示は、追加の工程を必要としなくてもよく、かつ、めっき処理後の剥離も容易で、めっき処理時の薬液の染み込みを的確に抑制できる構造の半導体ウェハおよびそれを用いた半導体装置の製造方法を提供することを目的とする。
The present disclosure provides a semiconductor wafer having a structure that does not require an additional step, can be easily peeled off after plating, and can accurately suppress permeation of a chemical solution during plating, and a semiconductor device using the same. The object is to provide a manufacturing method.
本開示の１つの観点における半導体ウェハは、半導体素子が形成された半導体基板と、半導体基板の上に形成され、少なくとも一部が半導体素子の所定位置に繋がる複数のコンタクトホールが形成された層間絶縁膜と、複数のコンタクトホール内に埋め込まれた複数の導体プラグと、半導体基板における外縁部よりも内側に形成され、複数の導体プラグの少なくとも一部と接続された表面電極と、表面電極の一部を覆いつつ、表面電極よりも半導体基板の外縁側まで形成されることで、表面電極よりも外側において層間絶縁膜および導体プラグを覆った保護膜と、半導体基板の外周端および該半導体基板の外縁部において保護膜の外縁部と貼り付けられた側面保護テープと、表面電極のうち保護膜から露出している部分の表面に形成されためっき層と、を有している。そして、保護膜のうち側面保護テープに貼り付けられた領域は、該保護膜のうち表面電極を覆っている部分よりも外側の領域とされている。
A semiconductor wafer according to one aspect of the present disclosure includes a semiconductor substrate on which semiconductor elements are formed, and an interlayer insulating film formed on the semiconductor substrate and having a plurality of contact holes at least partially connected to predetermined positions of the semiconductor elements. a film, a plurality of conductor plugs embedded in a plurality of contact holes, a surface electrode formed inside an outer edge of a semiconductor substrate and connected to at least a portion of the plurality of conductor plugs, and one of the surface electrodes. The protective film covering the interlayer insulating film and the conductor plug outside the surface electrode, the outer peripheral edge of the semiconductor substrate, and the outer edge of the semiconductor substrate. It has a side protection tape attached to the outer edge of the protective film at the outer edge, and a plated layer formed on the surface of the portion of the surface electrode exposed from the protective film. The area of the protective film that is attached to the side surface protective tape is outside the area that covers the surface electrode of the protective film.
このように、保護膜のうち側面保護テープに貼り付けられた領域が保護膜のうちの表面電極を覆っている部分よりも外側の領域となるようにすることで、保護膜の外縁部と側面保護テープとを隙間なく密着させられる。
In this way, the area of the protective film attached to the side surface protective tape is outside the area covering the surface electrode of the protective film, thereby preventing the outer edge of the protective film and the side surface of the protective film. It can be adhered to the protective tape without gaps.
したがって、表面電極の表面にめっき処理を行うときに、薬液が側面保護テープの内部に染み込むことを的確に抑制できる。よって、追加の工程を必要としなくてもよく、かつ、めっき処理後の剥離も容易で、めっき処理時の薬液の染み込みを的確に抑制できる構造の半導体ウェハとすることができる。
Therefore, when the surface of the surface electrode is plated, it is possible to accurately prevent the chemical solution from penetrating into the side protective tape. Therefore, it is possible to obtain a semiconductor wafer having a structure that does not require an additional step, can be easily peeled off after the plating process, and can accurately suppress permeation of the chemical solution during the plating process.
なお、各構成要素等に付された括弧付きの参照符号は、その構成要素等と後述する実施形態に記載の具体的な構成要素等との対応関係の一例を示すものである。
It should be noted that the reference numerals in parentheses attached to each component etc. indicate an example of the correspondence relationship between the component etc. and the specific component etc. described in the embodiment described later.
以下、本開示の実施形態について図に基づいて説明する。なお、以下の各実施形態相互において、互いに同一もしくは均等である部分には、同一符号を付して説明を行う。
Hereinafter, embodiments of the present disclosure will be described based on the drawings. In addition, in each of the following embodiments, portions that are the same or equivalent to each other will be described with the same reference numerals.
（第１実施形態）
第１実施形態について説明する。ここでは、めっき処理時の薬液の染み込みの抑制に適した構造の半導体ウェハと、その半導体ウェハを用いた半導体装置の製造方法について説明する。 (First embodiment)
A first embodiment will be described. Here, a semiconductor wafer having a structure suitable for suppressing permeation of a chemical solution during plating and a method of manufacturing a semiconductor device using the semiconductor wafer will be described.
第１実施形態について説明する。ここでは、めっき処理時の薬液の染み込みの抑制に適した構造の半導体ウェハと、その半導体ウェハを用いた半導体装置の製造方法について説明する。 (First embodiment)
A first embodiment will be described. Here, a semiconductor wafer having a structure suitable for suppressing permeation of a chemical solution during plating and a method of manufacturing a semiconductor device using the semiconductor wafer will be described.
まず、図１を参照して、本実施形態にかかる半導体ウェハ１の構成について説明する。なお、図１に示す半導体ウェハ１は、めっき処理を行った後のものであり、外縁部に後述する側面保護テープ７０が貼り付けられた状態となっている。つまり、後述する半導体装置の製造プロセスを実施する際の途中の段階での半導体ウェハ１を示したものであり、製造プロセスの残りの部分を実施することで、半導体装置が製造される。
First, the configuration of a semiconductor wafer 1 according to this embodiment will be described with reference to FIG. It should be noted that the semiconductor wafer 1 shown in FIG. 1 has been plated, and is in a state in which a side surface protection tape 70, which will be described later, is attached to the outer edge. In other words, it shows the semiconductor wafer 1 at an intermediate stage when a semiconductor device manufacturing process, which will be described later, is performed, and the semiconductor device is manufactured by performing the remaining part of the manufacturing process.
図１に示すように、半導体ウェハ１は、図示しない半導体素子が作り込まれた半導体基板１０、半導体基板１０の上に形成された層間絶縁膜２０および導体プラグ３０、表面電極４０、保護膜５０、めっき層６０、側面保護テープ７０を備える。
As shown in FIG. 1, a semiconductor wafer 1 includes a semiconductor substrate 10 in which semiconductor elements (not shown) are formed, an interlayer insulating film 20 and conductor plugs 30 formed on the semiconductor substrate 10, a surface electrode 40 and a protective film 50. , a plating layer 60 and a side protection tape 70 .
半導体基板１０は、ウェハ状とされており、予め半導体素子の製造プロセスが実施されることで半導体素子が形成されている。ここでは詳細構造を示していないが、半導体ウェハ１のうちのチップとして取り出される有効領域に所定のレイアウトで半導体素子が形成されている。半導体基板１０に対してどのような半導体素子を形成しても良いが、例えばトレンチゲート構造の縦型のＭＯＳＦＥＴなどを形成している。半導体素子としてトレンチゲート構造の縦型のＭＯＳＦＥＴを形成する場合、有効領域に配置される各チップそれぞれに対して、一方向を長手方向として複数本がストライプ状に並べられたトレンチゲート構造を有する縦型ＭＯＳＦＥＴが形成される。
The semiconductor substrate 10 is in the form of a wafer, and semiconductor elements are formed by performing a semiconductor element manufacturing process in advance. Although the detailed structure is not shown here, semiconductor elements are formed in a predetermined layout in effective regions taken out as chips from the semiconductor wafer 1 . Although any semiconductor element may be formed on the semiconductor substrate 10, for example, a vertical MOSFET having a trench gate structure is formed. When a vertical MOSFET having a trench gate structure is formed as a semiconductor element, each chip arranged in the effective region has a vertical trench gate structure in which a plurality of trench gate structures are arranged in stripes with one direction being the longitudinal direction. A type MOSFET is formed.
層間絶縁膜２０は、半導体素子が形成された半導体基板１０の表面側を覆うように形成され、シリコン酸化膜などによって構成されている。層間絶縁膜２０には複数のコンタクトホール２１が形成されており、少なくとも一部が半導体素子の所定位置を露出させている。例えば、半導体素子として縦型のＭＯＳＦＥＴを形成する場合には、コンタクトホール２１として、ｎ型ソース領域やベース領域における高濃度ｐ型コンタクト層に繋がるソースコンタクトホールが形成される。また、ソースコンタクトホールとは別に、コンタクトホール２１として、各トレンチゲート構造に備えられるゲート電極から引き出されたゲートライナーに繋がるゲートコンタクトホールも形成される。
The interlayer insulating film 20 is formed so as to cover the surface side of the semiconductor substrate 10 on which semiconductor elements are formed, and is composed of a silicon oxide film or the like. A plurality of contact holes 21 are formed in the interlayer insulating film 20, and at least some of them expose predetermined positions of the semiconductor element. For example, when a vertical MOSFET is formed as a semiconductor element, the contact hole 21 is formed as a source contact hole leading to a high-concentration p-type contact layer in the n-type source region or the base region. In addition to the source contact holes, gate contact holes are also formed as contact holes 21 leading to gate liners drawn out from the gate electrodes provided in each trench gate structure.
導体プラグ３０は、複数のコンタクトホール２１内に埋め込まれ、コンタクトホール２１内において露出させられた各部と電気的に接続される。導体プラグ３０は、金属導体、例えばＷ（タングステン）などによって構成されており、コンタクトホール２１が形成された層間絶縁膜２０の表面から半導体基板１０の表面まで形成されている。そして、層間絶縁膜２０によって囲まれることで、各導体プラグ３０が互いに分離した状態になっている。
The conductor plugs 30 are embedded in the plurality of contact holes 21 and electrically connected to each exposed portion in the contact holes 21 . The conductor plug 30 is made of a metal conductor such as tungsten (W), and is formed from the surface of the interlayer insulating film 20 in which the contact hole 21 is formed to the surface of the semiconductor substrate 10 . The conductor plugs 30 are separated from each other by being surrounded by the interlayer insulating film 20 .
表面電極４０は、導体プラグ３０と電気的に接続されることで、半導体素子の所定位置と電気的に接続される各種電極であり、例えばＡｌ（アルミニウム）系の電極材料などで構成される。例えば、半導体素子として縦型のＭＯＳＦＥＴを形成する場合、表面電極４０としてソース電極やゲート配線層を含むゲートパッドが形成され、これらが電気的に分離されるように、表面電極４０が所定形状にパターニングされている。表面電極４０は、半導体ウェハ１におけるチップとして取り出される有効領域に形成されており、少なくも半導体ウェハ１における外縁部の近傍においては形成されていない。つまり、半導体ウェハ１における外周端から所定距離の範囲内は表面電極４０が形成されていない領域とされている。そして、この表面電極４０が形成されていない領域では、層間絶縁膜２０および導体プラグ３０が表面電極４０から露出された状態となっている。
The surface electrodes 40 are various electrodes that are electrically connected to predetermined positions of the semiconductor element by being electrically connected to the conductor plugs 30, and are made of an Al (aluminum)-based electrode material, for example. For example, when a vertical MOSFET is formed as a semiconductor element, a gate pad including a source electrode and a gate wiring layer is formed as the surface electrode 40, and the surface electrode 40 is formed into a predetermined shape so that these are electrically separated. Patterned. The surface electrode 40 is formed in an effective region of the semiconductor wafer 1 to be taken out as a chip, and is not formed at least in the vicinity of the outer edge of the semiconductor wafer 1 . That is, the area within a predetermined distance from the outer peripheral edge of the semiconductor wafer 1 is a region where the surface electrode 40 is not formed. In regions where the surface electrodes 40 are not formed, the interlayer insulating film 20 and the conductor plugs 30 are exposed from the surface electrodes 40 .
保護膜５０は、表面電極４０の少なくとも一部を覆うと共に、層間絶縁膜２０および導体プラグ３０のうち表面電極４０から露出された部分を覆って保護する役割を果たすもので、例えばポリイミドなどで構成される。保護膜５０は、半導体ウェハ１の有効領域に形成された各表面電極４０の外縁部などを覆うように形成されている。また、保護膜５０は、半導体ウェハ１のうちチップとして取り出されない無効領域、つまり有効領域の周囲を囲むように配置される領域にも形成されている。そして、有効領域においては、表面電極４０などのパターンが形成されることで表面に凹凸が形成されているため、その表面に形成される保護膜５０についても凹凸を有するパターンが形成された状態になっている。ただし、無効領域においては、表面電極４０などのパターンが形成されておらず、表面電極４０より外側に位置する層間絶縁膜２０および導体プラグ３０が露出した状態になっている。このため、表面電極４０よりも外側の領域では、保護膜５０が層間絶縁膜２０および導体プラグ３０を直接覆った構造となり、保護膜５０の表面が殆ど凹凸のない平坦面になっている。
The protective film 50 covers at least a portion of the surface electrode 40 and covers and protects the portions of the interlayer insulating film 20 and the conductor plugs 30 exposed from the surface electrode 40, and is made of polyimide, for example. be done. The protective film 50 is formed so as to cover the outer edge of each surface electrode 40 formed in the effective area of the semiconductor wafer 1 . In addition, the protective film 50 is also formed in an ineffective area of the semiconductor wafer 1 which is not taken out as a chip, that is, an area arranged so as to surround the effective area. In the effective region, the surface electrode 40 and other patterns are formed to form unevenness on the surface. It's becoming However, in the invalid region, no pattern such as the surface electrode 40 is formed, and the interlayer insulating film 20 and the conductor plug 30 located outside the surface electrode 40 are exposed. Therefore, in the region outside the surface electrode 40, the protective film 50 directly covers the interlayer insulating film 20 and the conductor plugs 30, and the surface of the protective film 50 is almost flat with no unevenness.
なお、ここでいう凹凸のない平坦面とは、表面電極４０の厚みに起因する凹凸が無いことを意味し、保護膜５０を成膜する際に発生する膜厚ばらつきや、層間絶縁膜２０および導体プラグ３０の表面粗さに起因する凹凸が無いという意味ではない。保護膜５０のみが層間絶縁膜２０および導体プラグ３０の上に形成された状態で、表面電極４０の厚みに起因する凹凸がない表面のことを、凹凸のない平坦面と言っている。
Here, the flat surface without unevenness means that there is no unevenness due to the thickness of the surface electrode 40, and the variation in film thickness that occurs when forming the protective film 50 and the interlayer insulating film 20 and the interlayer insulating film 20 This does not mean that there is no unevenness due to the surface roughness of the conductor plug 30 . When only the protective film 50 is formed on the interlayer insulating film 20 and the conductor plugs 30 , the surface without unevenness caused by the thickness of the surface electrode 40 is called a flat surface without unevenness.
保護膜５０については、半導体ウェハ１の外周端まで形成されていても良いが、ここでは保護膜５０の外周端が半導体ウェハ１の外周端よりも内側に位置した状態になっている。
The protective film 50 may be formed up to the outer peripheral edge of the semiconductor wafer 1 , but here the outer peripheral edge of the protective film 50 is located inside the outer peripheral edge of the semiconductor wafer 1 .
めっき層６０は、表面電極４０のうち保護膜５０から露出した部分の表面に形成されている。めっき層６０は、例えばバリアメタル材料やボンディング性を向上させる材料などをめっき処理によって形成したものである。ここでは、めっき層６０をＮｉ（ニッケル）によって構成している。めっき層６０は、側面保護テープ７０などによって半導体基板１０の側面や保護膜５０の外縁部を覆った状態で形成される。
The plated layer 60 is formed on the surface of the portion of the surface electrode 40 exposed from the protective film 50 . The plating layer 60 is formed by plating, for example, a barrier metal material or a material that improves bonding properties. Here, the plating layer 60 is made of Ni (nickel). The plating layer 60 is formed in a state in which the side surface of the semiconductor substrate 10 and the outer edge of the protective film 50 are covered with a side surface protective tape 70 or the like.
側面保護テープ７０は、半導体基板１０の側面、つまり外周端および外縁部の所定範囲を覆うように半導体基板１０に対して貼り付けられており、内周部分の一周全域が保護膜５０に貼り付けられている。側面保護テープ７０は、例えばエラストマー組成、ＰＰ（ポリプロピレン）、ＰＥＴ（ポリエチレンテレフタレート）、シリコーン、ＵＶテープなどの半導体のめっき処理に使用されるものであれば、どのような材質ものであっても良い。側面保護テープ７０は、半導体基板１０の外周端や、層間絶縁膜２０および導体プラグ３０の外縁部での露出箇所、さらには保護膜５０の外周端からその内側に位置する外縁部の所定範囲に密着させられている。そして、側面保護テープ７０のうちの内周側は、保護膜５０のうち表面が平坦面となっている外縁部と密着していて、保護膜５０のうちのパターンが形成されていない領域とだけ密着し、パターンが形成されている領域とは密着していない。つまり、保護膜５０のうち側面保護テープ７０が貼り付けられた領域が、保護膜５０のうち表面電極４０を覆っている部分よりも外側の領域のみとなるようにしてある。このため、側面保護テープ７０は保護膜５０のうち表面に凹凸が無い領域と隙間なく密着させられた状態になっている。
The side surface protection tape 70 is attached to the semiconductor substrate 10 so as to cover the side surface of the semiconductor substrate 10 , that is, the outer peripheral edge and the predetermined range of the outer edge portion, and the entire circumference of the inner peripheral portion is attached to the protective film 50 . It is The side protection tape 70 may be made of any material that is used for semiconductor plating, such as elastomer composition, PP (polypropylene), PET (polyethylene terephthalate), silicone, and UV tape. . The side protection tape 70 is applied to the outer edge of the semiconductor substrate 10, the exposed portions at the outer edge of the interlayer insulating film 20 and the conductor plugs 30, and the predetermined range of the outer edge located inside from the outer edge of the protective film 50. are kept in close contact. The inner peripheral side of the side surface protective tape 70 is in close contact with the outer edge portion of the protective film 50 having a flat surface, and only the region of the protective film 50 where no pattern is formed. It is in close contact and is not in close contact with the region where the pattern is formed. That is, the area of the protective film 50 to which the side surface protective tape 70 is attached is only the area outside the portion of the protective film 50 covering the surface electrode 40 . Therefore, the side surface protective tape 70 is in close contact with the area of the protective film 50 where there is no unevenness on the surface.
続いて、上記のように構成された半導体ウェハ１の製造プロセスを含む、半導体装置の製造方法について、図２に示すフローチャートを参照して説明する。
Next, a method of manufacturing a semiconductor device, including the manufacturing process of the semiconductor wafer 1 configured as described above, will be described with reference to the flowchart shown in FIG.
まず、図２のステップＳ１００として表面素子構造形成工程を行う。すなわち、ウェハ状の半導体基板１０に対して半導体素子を形成する製造プロセスを行うと共に、半導体基板１０のうちの表面側に対して実施する各種プロセスを行う。半導体素子としてｎチャネル型の縦型ＭＯＳＦＥＴを形成するのであれば、縦型ＭＯＳＦＥＴを構成するための各部の形成工程を行う。すなわち、ｎ型の半導体基板１０に対してｎ型ドリフト層の形成、ｐ型ベース領域の形成、ｎ型ソース領域および高濃度ｐ型コンタクト層の形成、ゲートトレンチ形成、ゲート絶縁膜形成、ゲート電極形成などの各種工程を行う。これにより、半導体基板１０に対して半導体素子が形成される。さらに、層間絶縁膜２０および導体プラグ３０の形成工程や表面電極４０の形成工程、さらには保護膜５０の形成工程まで行う。
First, as step S100 in FIG. 2, a surface element structure forming step is performed. That is, a manufacturing process for forming semiconductor elements is performed on the semiconductor substrate 10 in the form of a wafer, and various processes are performed on the front surface side of the semiconductor substrate 10 . If an n-channel type vertical MOSFET is to be formed as a semiconductor element, the formation process of each part for constituting the vertical MOSFET is performed. That is, for an n-type semiconductor substrate 10, formation of an n-type drift layer, formation of a p-type base region, formation of an n-type source region and a high-concentration p-type contact layer, formation of a gate trench, formation of a gate insulating film, formation of a gate electrode, and Various processes such as forming are performed. Thereby, a semiconductor element is formed on the semiconductor substrate 10 . Further, steps of forming the interlayer insulating film 20 and the conductor plugs 30, forming the surface electrodes 40, and further forming the protective film 50 are performed.
次に、ステップＳ１０５として図示しない表面保護テープの貼り付け工程を行う。つまり、半導体ウェハ１のうちの表面側を全面覆うように表面保護テープを貼り付ける。そして、ステップＳ１１０として裏面研削工程を行うことで、半導体ウェハ１の裏面側を所定厚さ削り、半導体ウェハ１の薄厚化を行う。また、半導体ウェハ１の裏面側の研削工程が終わったら、ステップＳ１１５として半導体ウェハ１の裏面エッチング工程を行い、半導体ウェハ１の裏面の平坦化やダメージ除去を行う。
Next, as step S105, a step of attaching a surface protection tape (not shown) is performed. That is, the surface protection tape is attached so as to cover the entire surface of the semiconductor wafer 1 . Then, in step S110, the back side of the semiconductor wafer 1 is ground by a predetermined thickness to reduce the thickness of the semiconductor wafer 1 by performing a back grinding step. After the grinding process of the back side of the semiconductor wafer 1 is finished, the back side etching process of the semiconductor wafer 1 is performed as step S115 to planarize the back side of the semiconductor wafer 1 and remove damage.
その後、ステップＳ１２０として表面保護テープ剥離工程を行って表面保護テープを半導体ウェハ１の表面から剥離させる。また、ステップＳ１２５として試料をスパッタ装置などに設置して、半導体ウェハ１の裏面に電極を形成する裏面電極形成工程を行う。半導体素子として縦型ＭＯＳＦＥＴを形成するのであれば、この裏面電極がドレイン電極となる。
After that, a surface protective tape peeling step is performed as step S120 to peel the surface protective tape from the surface of the semiconductor wafer 1. Further, in step S125, the sample is placed in a sputtering device or the like, and a back surface electrode forming step of forming an electrode on the back surface of the semiconductor wafer 1 is performed. If a vertical MOSFET is formed as a semiconductor element, this back surface electrode becomes a drain electrode.
続いて、ステップＳ１３０として図示しない裏面保護テープの貼り付け工程を行う。つまり、半導体ウェハ１の裏面に対して裏面保護テープを貼り付ける。さらに、ステップＳ１３５として側面保護テープの貼り付け工程を行うことで、半導体ウェハ１の側面、つまり外周端および保護膜５０のうちの外縁部を覆うように側面保護テープ７０を貼り付ける。このとき、保護膜５０と側面保護テープ７０とが隙間なく密着した状態になる。
Subsequently, in step S130, a step of attaching a back surface protective tape (not shown) is performed. That is, the back surface protective tape is attached to the back surface of the semiconductor wafer 1 . Further, in step S135, a step of attaching the side surface protection tape is performed to attach the side surface protection tape 70 so as to cover the side surface of the semiconductor wafer 1, that is, the outer peripheral edge and the outer edge portion of the protective film 50. FIG. At this time, the protective film 50 and the side protective tape 70 are in close contact with each other without a gap.
そして、ステップＳ１４０として側面保護テープ７０および裏面保護テープで半導体ウェハ１の側面および裏面を覆った状態で表面めっき処理工程を行う。例えば、表面電極４０のうち保護膜５０から露出させられている部分の表面に、Ｎｉ層のめっき層６０を形成する。このようにしてめっき層６０を形成した状態を示したのが図１である。
Then, in step S140, the surface plating process is performed while the side surface and the back surface of the semiconductor wafer 1 are covered with the side surface protection tape 70 and the back surface protection tape. For example, the plated layer 60 of Ni layer is formed on the surface of the portion of the surface electrode 40 exposed from the protective film 50 . FIG. 1 shows the state in which the plating layer 60 is formed in this manner.
このとき、表面めっき処理の際に薬液に試料を浸すことになるが、保護膜５０と側面保護テープ７０とが隙間なく密着した状態になっているため、薬液が側面保護テープ７０の内部に染み込むことを的確に抑制できる。そして、このような薬液の染み込み抑制を保護膜５０のうちの外縁部を凹凸の無いパターン形成されていない構造とするだけで行っている。このため、側面保護テープ７０の貼り付け後に真空引き処理を行うことで密着性を向上させる手法のように、追加の処理を必要としない。また、テープの糊材質の密着性を増加させる手法のように、めっき処理後の剥離の際に糊が残ることも抑制でき、剥離も容易に行うことができる。
At this time, the sample is immersed in a chemical solution during the surface plating treatment, but since the protective film 50 and the side surface protective tape 70 are in close contact with each other without any gap, the chemical solution penetrates into the side surface protective tape 70. can be suppressed precisely. In addition, such permeation suppression of the chemical solution is performed only by making the outer edge portion of the protective film 50 a structure without unevenness and pattern formation. For this reason, unlike the technique of improving adhesion by vacuuming after the side surface protective tape 70 is attached, no additional processing is required. In addition, it is possible to prevent the adhesive from remaining when peeling off after the plating process, as in the method of increasing the adhesiveness of the adhesive material of the tape, so that the peeling can be easily performed.
この後、ステップＳ１４５、Ｓ１５０として、側面保護テープ７０の剥離工程と裏面保護テープの剥離工程を順に行う。また、ステップＳ１５５として再び裏面保護テープの貼り付け工程を行って、半導体ウェハ１の裏面にダイシングテープを貼り付ける。
After that, as steps S145 and S150, a peeling process of the side surface protective tape 70 and a peeling process of the back surface protective tape are performed in order. In step S155, the process of attaching the back surface protective tape is performed again to attach the dicing tape to the back surface of the semiconductor wafer 1. FIG.
この後、ステップＳ１６０としてダイシング工程を行って、半導体ウェハ１をチップ単位に分割したのち、ステップＳ１６５として裏面保護テープ剥離工程を行って、各チップを裏面保護テープから剥がすことで個片化したチップが形成される。このようにして、チップ化した半導体装置を製造することができる。
Thereafter, a dicing process is performed as step S160 to divide the semiconductor wafer 1 into chips, and then a back surface protective tape peeling process is performed as step S165 to peel off the respective chips from the back surface protective tape to separate the chips. is formed. Thus, a chipped semiconductor device can be manufactured.
以上説明したように、本実施形態では、半導体ウェハ１の表面に形成される保護膜５０について、側面保護テープ７０が貼り付けられる外縁部については、パターンが形成されていない平坦面としている。このため、保護膜５０の外縁部と側面保護テープ７０とを隙間なく密着させられる。
As described above, in the present embodiment, regarding the protective film 50 formed on the surface of the semiconductor wafer 1, the outer edge portion to which the side protective tape 70 is attached is a flat surface on which no pattern is formed. Therefore, the outer edge portion of the protective film 50 and the side surface protective tape 70 can be brought into close contact without any gap.
より詳しくは、従来では、半導体ウェハ１は、図３に示すように、半導体基板１０の上に形成した層間絶縁膜２０および導体プラグ３０の上に、表面電極４０および保護膜５０が半導体ウェハ１の外縁部に至るまで形成された構造になっていた。このため、側面保護テープ７０が保護膜５０に貼り付けられても、保護膜５０の表面に凹凸が形成された状態になっているため、側面保護テープ７０と保護膜５０との間に隙間が生じ、めっき処理時の薬液が染み込んでしまっていた。なお、図３では、表面電極４０が同じ厚みで一面に形成されているように記載してあるが、実際にはパターニングされていて、厚み分の凹凸が形成された状態になっている。
More specifically, conventionally, as shown in FIG. It was a structure formed up to the outer edge of the. Therefore, even if the side surface protective tape 70 is attached to the protective film 50 , the surface of the protective film 50 is in a state in which unevenness is formed. A chemical solution at the time of plating treatment had permeated. Although FIG. 3 shows that the surface electrode 40 is formed all over the surface with the same thickness, it is actually patterned to form unevenness corresponding to the thickness.
これに対して、本実施形態の半導体ウェハ１では、側面保護テープ７０を表面に凹凸が無い保護膜５０に貼り付けているため、保護膜５０の外縁部と側面保護テープ７０とを隙間なく密着させられる。
On the other hand, in the semiconductor wafer 1 of the present embodiment, since the side surface protection tape 70 is attached to the protective film 50 having no irregularities on the surface, the outer edge portion of the protection film 50 and the side surface protection tape 70 are closely attached without any gap. Let me.
したがって、表面電極４０の表面にめっき処理を行うときに、薬液が側面保護テープ７０の内部に染み込むことを的確に抑制できる。そして、上記したように、追加の処理を必要としないし、めっき処理後の剥離の際に糊が残ることも抑制できる。よって、追加の工程を必要としなくてもよく、かつ、めっき処理後の剥離も容易で、めっき処理時の薬液の染み込みを的確に抑制できる構造の半導体ウェハ１とすることができる。そして、そのような半導体ウェハ１を用いて半導体装置を製造することで、めっき処理時の薬液の染み込みによる不具合、例えば薬液残りが発生することを抑制することが可能となる。
Therefore, when the surface of the surface electrode 40 is plated, it is possible to accurately prevent the chemical solution from penetrating into the side surface protection tape 70 . Further, as described above, no additional treatment is required, and it is possible to prevent the adhesive from remaining when peeled off after the plating treatment. Therefore, the semiconductor wafer 1 can have a structure that does not require an additional step, can be easily peeled off after the plating process, and can accurately suppress penetration of the chemical solution during the plating process. By manufacturing a semiconductor device using such a semiconductor wafer 1, it is possible to suppress the occurrence of defects due to permeation of the chemical during plating, such as chemical residue.
（第２実施形態）
第２実施形態について説明する。本実施形態は、第１実施形態に対して半導体ウェハ１のうちの内側の領域についての不具合を抑制するものであり、その他については第１実施形態と同様であるため、第１実施形態と異なる部分についてのみ説明する。 (Second embodiment)
A second embodiment will be described. This embodiment is different from the first embodiment because it suppresses defects in the inner region of thesemiconductor wafer 1 as compared with the first embodiment, and is otherwise the same as the first embodiment. Only part will be explained.
第２実施形態について説明する。本実施形態は、第１実施形態に対して半導体ウェハ１のうちの内側の領域についての不具合を抑制するものであり、その他については第１実施形態と同様であるため、第１実施形態と異なる部分についてのみ説明する。 (Second embodiment)
A second embodiment will be described. This embodiment is different from the first embodiment because it suppresses defects in the inner region of the
第１実施形態では、半導体ウェハ１のうちの外縁部におけるめっき処理時の薬液の染み込み抑制を図っている。これに加えて、本実施形態では、半導体ウェハ１のうちの外縁部よりも内側の領域、具体的には、側面保護テープ７０が貼り付けられた領域よりも内側において、めっき処理時の不具合を抑制する。
In the first embodiment, the permeation of the chemical solution at the outer edge of the semiconductor wafer 1 is suppressed during the plating process. In addition to this, in the present embodiment, in the area inside the outer edge of the semiconductor wafer 1, specifically, inside the area where the side surface protection tape 70 is attached, defects during the plating process are prevented. Suppress.
半導体ウェハ１の内側の領域では、ダイシングが容易に行え、かつ、ダイシングの際に発生した残渣が最終製品に付着して不具合を発生させることを抑制できるように、スクライブライン上に形成されるものをできるだけ少なくするのが好ましい。このため、スクライブライン上では、表面電極４０が形成されないようにしたり、保護膜５０を無くしたりするのが好ましい。この場合、めっき処理時に、スクライブライン上において層間絶縁膜２０および導体プラグ３０が薬液に曝されることになる。
The inner region of the semiconductor wafer 1 is formed on the scribe line so that dicing can be easily performed and residue generated during dicing can be prevented from adhering to the final product and causing defects. should be as low as possible. Therefore, it is preferable not to form the surface electrode 40 or to eliminate the protective film 50 on the scribe line. In this case, the interlayer insulating film 20 and the conductor plugs 30 are exposed to the chemical solution on the scribe line during the plating process.
このように、導体プラグ３０が薬液に曝された場合、導体プラグ３０の露出部にめっきが付着することがあり、後工程で残渣の発生原因となり得ることが確認された。導体プラグ３０の表面には、本来、めっきが付着し難いが、めっきが付着した場合には、密着性が低いために剥がれやすく、後工程において残渣になり易い。スクライブライン上にはできるだけ導体プラグ３０を形成しないようにしているが、アライメントマークをチップ内部に形成できない場合、スクライブライン上に導体プラグ３０の材料を用いたアライメントマークを形成せざるを得ない場合がある。このような場合、スクライブライン上の露出した導体プラグ３０で形成されるアライメントマークがめっき処理時に半導体基板１０と導通する。これにより、露出している導体プラグ３０の表面にめっきが付着してしまうことが判った。
As described above, it was confirmed that when the conductor plug 30 was exposed to the chemical solution, the plating sometimes adhered to the exposed portion of the conductor plug 30, which could cause the generation of residue in the post-process. It is difficult for the plating to adhere to the surface of the conductor plug 30, but when the plating adheres, it is easy to come off due to its low adhesion and tends to become a residue in the post-process. Although the conductor plugs 30 are not formed on the scribe lines as much as possible, if the alignment marks cannot be formed inside the chip, the alignment marks using the material of the conductor plugs 30 must be formed on the scribe lines. There is In such a case, the alignment marks formed by the conductor plugs 30 exposed on the scribe lines are electrically connected to the semiconductor substrate 10 during the plating process. As a result, it has been found that plating adheres to the exposed surface of the conductor plug 30 .
そこで、本実施形態では、図４に示すように、露出した導体プラグ３０と半導体基板１０との間が離れていて、導体プラグ３０が半導体基板１０に接触しない構造にしている。つまり、導体プラグ３０を半導体基板１０から離して電気的にフローティング状態にしている。具体的には、導体プラグ３０が形成される位置に、層間絶縁膜２０に対してコンタクトホール２１を形成する際のエッチングレートを層間絶縁膜２０だけの場合よりも低下させる低エッチングレート部材２２を備えている。このようにすることで、コンタクトホール２１が半導体基板１０まで届かないようにでき、導体プラグ３０と半導体基板１０との間に低エッチングレート部材２２が配置された状態になる。つまり、表面電極４０の材料で構成されるアライメントマーク４１と表面が露出した導体プラグ３０とが半導体基板１０を介して導通しなくなる。このため、露出している導体プラグ３０の表面にめっきが付着することが抑制される。したがって、残渣の発生を抑制でき、残渣が最終製品に付着して不具合を発生させることを抑制することが可能となる。
Therefore, in this embodiment, as shown in FIG. 4, the exposed conductor plug 30 and the semiconductor substrate 10 are separated from each other so that the conductor plug 30 does not come into contact with the semiconductor substrate 10 . In other words, the conductor plug 30 is separated from the semiconductor substrate 10 and is in an electrically floating state. Specifically, a low etching rate member 22 is placed at the position where the conductor plug 30 is to be formed. I have. By doing so, the contact hole 21 can be prevented from reaching the semiconductor substrate 10 , and the low etching rate member 22 is arranged between the conductor plug 30 and the semiconductor substrate 10 . In other words, the alignment mark 41 made of the material of the surface electrode 40 and the conductor plug 30 whose surface is exposed are not electrically connected through the semiconductor substrate 10 . Therefore, the adhesion of plating to the exposed surface of the conductor plug 30 is suppressed. Therefore, it is possible to suppress the generation of residues, and it is possible to suppress the occurrence of defects due to the residues adhering to the final product.
このような低エッチングレート部材２２については、例えば、ポリシリコンやＳｉＮ（シリコン窒化膜）などによって構成することができる。低エッチングレート部材２２の製造方法については任意であり、例えば層間絶縁膜２０の一部を形成した後に、低エッチングレート部材２２のみを成膜すると共に、それをパターニングする工程を行うことなどを適用できる。さらに、半導体素子の形成に用いられる別の部分を形成するための工程と共通化させて低エッチングレート部材２２を形成することもできる。例えば、半導体素子として縦型ＭＯＳＦＥＴを形成する場合、ゲート絶縁膜を半導体基板１０の表面に形成した後、その上にポリシリコンで構成されるゲート電極を形成する際に、そのポリシリコンで低エッチングレート部材２２を形成する。その後に、層間絶縁膜２０を形成するようにすれば、半導体素子の形成に用いられる別の工程と低エッチングレート部材２２の製造工程を共通化でき、製造工程の増加を抑制して製造工程の簡略化を図ることができる。
Such a low etching rate member 22 can be made of, for example, polysilicon or SiN (silicon nitride film). The method for manufacturing the low etching rate member 22 is arbitrary, and for example, after forming a part of the interlayer insulating film 20, only the low etching rate member 22 is formed and patterned. can. Furthermore, the low etching rate member 22 can be formed by sharing the process for forming another portion used for forming the semiconductor element. For example, when forming a vertical MOSFET as a semiconductor element, after forming a gate insulating film on the surface of the semiconductor substrate 10, when forming a gate electrode made of polysilicon thereon, the polysilicon is subjected to low etching. A rate member 22 is formed. If the interlayer insulating film 20 is formed after that, another process used for forming the semiconductor element and the manufacturing process of the low etching rate member 22 can be made common, suppressing an increase in the number of manufacturing processes and shortening the manufacturing process. Simplification can be achieved.
なお、第１実施形態では、層間絶縁膜２０および導体プラグ３０の上に保護膜５０のみを形成し、半導体ウェハ１の外縁部まで保護膜５０を配置して、側面保護テープ７０が保護膜５０の表面に貼り付けられるようにしている。これは、上記した通り、側面保護テープ７０が保護膜５０のうち凹凸の無い表面に隙間無く貼り付けられるようにするためであるが、図５に示すように保護膜５０を半導体ウェハ１の外縁まで備えない構造とすることも考えられる。このようにすれば、凹凸の少ない層間絶縁膜２０および導体プラグ３０に対して側面保護テープ７０を貼り付けられるため、側面保護テープ７０を隙間無く貼り付けることができる。しかしながら、この場合には、保護膜５０と側面保護テープ７０との間において、導体プラグ３０が露出することになるため、めっき処理時にめっき層６０が付着して残渣の発生原因になり得る。したがって、半導体ウェハ１の外縁部については、第１実施形態のように、半導体ウェハ１の外縁部まで保護膜５０を配置して、側面保護テープ７０が保護膜５０の表面に貼り付けられるようにすると好ましい。
In the first embodiment, only the protective film 50 is formed on the interlayer insulating film 20 and the conductor plugs 30, the protective film 50 is arranged up to the outer edge of the semiconductor wafer 1, and the side surface protective tape 70 covers the protective film 50. It is designed to be affixed to any surface. This is because, as described above, the side surface protection tape 70 can be adhered to the smooth surface of the protection film 50 without gaps. It is also conceivable to have a structure that does not include up to. In this way, the side protective tape 70 can be adhered to the interlayer insulating film 20 and the conductor plug 30 with little unevenness, so that the side protective tape 70 can be adhered without gaps. However, in this case, since the conductor plugs 30 are exposed between the protective film 50 and the side surface protective tape 70, the plating layer 60 may adhere during the plating process and cause residue. Therefore, for the outer edge of the semiconductor wafer 1, the protective film 50 is arranged up to the outer edge of the semiconductor wafer 1 as in the first embodiment, and the side surface protective tape 70 is attached to the surface of the protective film 50. It is preferable to do so.
また、導体プラグ３０の表面にめっきが付着することを抑制する技術として、導体プラグ３０の表面を密着性の高いめっき成長が起こる物質で覆う技術、めっき成長が起きない物質で覆う技術などもある。しかしながら、めっき成長が起こる物質で覆うことは、後工程でチップを小片化するダイシング工程において、覆った物質および成長しためっきがダイシングブレードへの負荷となり、チッピングの発生、ブレード寿命の低下という問題が生じてくる。また、めっき成長が起きない物質で覆うことに対しては、追加の膜形成が必要となり、コストの増加が問題となる。このため、本実施形態のように、低エッチングレート部材２２によって導体プラグ３０が半導体基板１０と接しない構造にすることが有用である。
In addition, as a technique for suppressing plating from adhering to the surface of the conductor plug 30, there is a technique of covering the surface of the conductor plug 30 with a material that causes plating growth with high adhesion, and a technique of covering the surface of the conductor plug 30 with a material that does not cause plating growth. . However, covering with a substance that causes plating growth causes problems such as the generation of chipping and a reduction in the life of the blade as the covered substance and the grown plating become a load on the dicing blade in the dicing process in which the chip is cut into small pieces in the subsequent process. arise. In addition, covering with a material that does not cause plating growth requires the formation of an additional film, which poses a problem of increased cost. Therefore, it is useful to provide a structure in which the low etching rate member 22 prevents the conductor plug 30 from coming into contact with the semiconductor substrate 10 as in the present embodiment.
（第２実施形態の変形例）
上記第２実施形態では、半導体基板１０の表面上に層間絶縁膜２０の一部やゲート絶縁膜などの絶縁膜を介して低エッチングレート部材２２を形成する例を示したが、他の構造とすることもできる。 (Modification of Second Embodiment)
In the second embodiment, an example is shown in which the lowetching rate member 22 is formed on the surface of the semiconductor substrate 10 via a part of the interlayer insulating film 20 or an insulating film such as a gate insulating film. You can also
上記第２実施形態では、半導体基板１０の表面上に層間絶縁膜２０の一部やゲート絶縁膜などの絶縁膜を介して低エッチングレート部材２２を形成する例を示したが、他の構造とすることもできる。 (Modification of Second Embodiment)
In the second embodiment, an example is shown in which the low
例えば、半導体素子としてトレンチゲート構造の縦型ＭＯＳＦＥＴを形成する場合に、縦型ＭＯＳＦＥＴと同様のトレンチゲート構造を用いて低エッチングレート部材２２を構成することもできる。具体的には、図６Ａに示すように、導体プラグ３０の形成予定位置において、半導体基板１０の表面からトレンチ１１を形成しておく。そして、トレンチ１１内にゲート電極と同様の構造のポリシリコン層で構成される低エッチングレート部材２２を備える。このようにすれば、トレンチゲート構造と同様の構造によって低エッチングレート部材２２を構成できる。このようにしても、半導体素子の形成に用いられる別の工程と低エッチングレート部材２２の製造工程を共通化でき、製造工程の増加を抑制して製造工程の簡略化を図ることができる。
For example, when forming a vertical MOSFET with a trench gate structure as a semiconductor element, the low etching rate member 22 can also be configured using a trench gate structure similar to the vertical MOSFET. Specifically, as shown in FIG. 6A, trenches 11 are formed from the surface of the semiconductor substrate 10 at positions where the conductor plugs 30 are to be formed. A low etching rate member 22 made of a polysilicon layer having the same structure as the gate electrode is provided in the trench 11 . In this way, the low etching rate member 22 can be configured with a structure similar to the trench gate structure. Also in this way, another process used for forming the semiconductor element and the manufacturing process of the low etching rate member 22 can be shared, and the manufacturing process can be simplified by suppressing an increase in the number of manufacturing processes.
また、図６Ｂに示すように、トレンチゲート構造と同時に導体プラグ３０の形成予定位置にもトレンチ１１を形成しつつ、トレンチ１１内にポリシリコン層が形成されない構造とすることもできる。つまり、トレンチ１１内をゲート絶縁膜や層間絶縁膜２０の一部によって埋め込まれるようにして、実質的に導体プラグ３０の形成予定位置において絶縁膜の厚みがトレンチ１１ではない部分よりも厚くなるようにする。このようにすれば、半導体基板１０に到達する迄の導体プラグ３０のアスペクト比、つまり幅に対する深さの比を増加させられ、導体プラグ３０が半導体基板１０に接触しないようにでき、第２実施形態と同様の効果を得ることができる。
Further, as shown in FIG. 6B, a structure in which the trench 11 is formed at the position where the conductor plug 30 is to be formed at the same time as the trench gate structure and the polysilicon layer is not formed in the trench 11 may be employed. That is, the inside of the trench 11 is partially filled with the gate insulating film and the interlayer insulating film 20 so that the thickness of the insulating film substantially becomes thicker at the position where the conductor plug 30 is to be formed than at the portion other than the trench 11 . to In this way, the aspect ratio of the conductor plug 30 until it reaches the semiconductor substrate 10, that is, the ratio of depth to width, can be increased, and the conductor plug 30 can be prevented from coming into contact with the semiconductor substrate 10. You can get the same effect as the form.
さらに、図６Ｃに示すように、スクライブラインに形成される導体プラグ３０がチップ内に形成される導体プラグ３０よりも幅が小さくなるように、コンタクトホール２１の幅寸法を狭くしてアスペクト比を大きく、つまり高アスペクト比とする。このようにすると、層間絶縁膜２０に対してコンタクトホール２１を形成する際に、マイクロローディング現象により、チップ内に形成されるものよりもスクライブラインに形成されるものの方がコンタクトホール２１の深さが浅くなる。したがって、導体プラグ３０を形成したときに、スクライブラインに形成される導体プラグ３０が半導体基板１０に接触しないようにでき、第２実施形態と同様の効果を得ることができる。
Furthermore, as shown in FIG. 6C, the width dimension of the contact hole 21 is narrowed to reduce the aspect ratio so that the conductor plug 30 formed in the scribe line is narrower than the conductor plug 30 formed in the chip. It should be large, that is, it should have a high aspect ratio. In this way, when the contact hole 21 is formed in the interlayer insulating film 20, the depth of the contact hole 21 formed in the scribe line is greater than that formed in the chip due to the microloading phenomenon. becomes shallower. Therefore, when the conductor plugs 30 are formed, the conductor plugs 30 formed in the scribe line can be prevented from coming into contact with the semiconductor substrate 10, and the same effect as in the second embodiment can be obtained.
（他の実施形態）
本開示は、上記した実施形態に準拠して記述されたが、当該実施形態に限定されるものではなく、様々な変形例や均等範囲内の変形をも包含する。加えて、様々な組み合わせや形態、さらには、それらに一要素のみ、それ以上、あるいはそれ以下、を含む他の組み合わせや形態をも、本開示の範疇や思想範囲に入るものである。 (Other embodiments)
Although the present disclosure has been described based on the above embodiment, it is not limited to the embodiment, and includes various modifications and modifications within the equivalent range. In addition, various combinations and configurations, as well as other combinations and configurations, including single elements, more, or less, are within the scope and spirit of this disclosure.
本開示は、上記した実施形態に準拠して記述されたが、当該実施形態に限定されるものではなく、様々な変形例や均等範囲内の変形をも包含する。加えて、様々な組み合わせや形態、さらには、それらに一要素のみ、それ以上、あるいはそれ以下、を含む他の組み合わせや形態をも、本開示の範疇や思想範囲に入るものである。 (Other embodiments)
Although the present disclosure has been described based on the above embodiment, it is not limited to the embodiment, and includes various modifications and modifications within the equivalent range. In addition, various combinations and configurations, as well as other combinations and configurations, including single elements, more, or less, are within the scope and spirit of this disclosure.
例えば、上記各実施形態では、半導体素子として縦型ＭＯＳＦＥＴを例に挙げたが、これに限るものではなく、他の半導体素子であっても良いし、縦型半導体素子ではない横型半導体素子であっても良い。半導体素子として、トレンチゲート構造の縦型ＩＧＢＴを形成する場合には、トレンチゲート構造の形成の際に、工程を共通化させて図４、図６Ａおよび図６Ｂの構造を形成できるという効果が得られる。
For example, in each of the above-described embodiments, a vertical MOSFET is taken as an example of a semiconductor element, but the semiconductor element is not limited to this, and may be another semiconductor element, or a horizontal semiconductor element that is not a vertical semiconductor element. can be When a vertical IGBT having a trench gate structure is formed as a semiconductor element, an effect can be obtained that the structures shown in FIGS. 4, 6A and 6B can be formed by sharing the steps in forming the trench gate structure. be done.
また、上記第２実施形態では、層間絶縁膜２０および導体プラグ３０が保護膜５０から露出した領域となる露出領域としてスクライブライン上の領域を例に挙げて説明した。しかしながら、スクライブライン上の領域以外に露出領域が存在する場合には、その露出領域についても、第２実施形態やその変型例に示す構造として、導体プラグ３０が半導体基板１０に接しないようにすると好ましい。
In addition, in the above-described second embodiment, the exposed region where the interlayer insulating film 20 and the conductor plug 30 are exposed from the protective film 50 has been described by taking the region on the scribe line as an example. However, if there is an exposed region other than the region on the scribe line, it is possible to prevent the conductor plug 30 from coming into contact with the semiconductor substrate 10 as the structure shown in the second embodiment and its modification for the exposed region. preferable.
また、上記第１実施形態では、図２に示すフローチャートに基づいて半導体装置の製造方法について説明したが、ここに示した各プロセスをすべて行う必要は無い。例えば、半導体基板１０の裏面研削を行わない場合には、裏面研削工程や裏面エッチング工程などを無くしても良い。
Also, in the first embodiment, the method for manufacturing a semiconductor device has been described based on the flowchart shown in FIG. 2, but it is not necessary to perform all the processes shown here. For example, when the back surface of the semiconductor substrate 10 is not ground, the back surface grinding process and the back surface etching process may be omitted.
Claims (6)
- 半導体ウェハであって、
半導体素子が形成された半導体基板（１０）と、
前記半導体基板の上に形成され、少なくとも一部が前記半導体素子の所定位置に繋がる複数のコンタクトホール（２１）が形成された層間絶縁膜（２０）と、
前記複数のコンタクトホール内に埋め込まれた複数の導体プラグ（３０）と、
前記半導体基板における外縁部よりも内側に形成され、前記複数の導体プラグの少なくとも一部と接続された表面電極（４０）と、
前記表面電極の一部を覆いつつ、前記表面電極よりも前記半導体基板の外縁側まで形成されることで、前記表面電極よりも外側において前記層間絶縁膜および前記導体プラグを覆った保護膜（５０）と、
前記半導体基板の外周端および該半導体基板の外縁部において前記保護膜の外縁部と貼り付けられた側面保護テープ（７０）と、
前記表面電極のうち前記保護膜から露出している部分の表面に形成されためっき層（６０）と、を有し、
前記保護膜のうち前記側面保護テープに貼り付けられた領域は、該保護膜のうち前記表面電極を覆っている部分よりも外側の領域とされている、半導体ウェハ。 A semiconductor wafer,
a semiconductor substrate (10) on which a semiconductor element is formed;
an interlayer insulating film (20) formed on the semiconductor substrate and having a plurality of contact holes (21) at least partially connected to predetermined positions of the semiconductor element;
a plurality of conductor plugs (30) embedded in the plurality of contact holes;
a surface electrode (40) formed inside the outer edge of the semiconductor substrate and connected to at least part of the plurality of conductor plugs;
The protective film (50 )When,
a side protection tape (70) attached to the outer edge of the protective film at the outer edge of the semiconductor substrate and the outer edge of the semiconductor substrate;
a plated layer (60) formed on the surface of a portion of the surface electrode exposed from the protective film,
The semiconductor wafer according to claim 1, wherein a region of the protective film attached to the side surface protective tape is a region outside a portion of the protective film covering the surface electrode. - 前記側面保護テープが貼り付けられた領域よりも内側の領域において、前記層間絶縁膜および前記導体プラグが前記保護膜から露出した露出領域があり、
前記露出領域においては、前記導体プラグが前記半導体基板から離れている、請求項１に記載の半導体ウェハ。 an exposed region in which the interlayer insulating film and the conductor plug are exposed from the protective film in a region inside the region to which the side surface protective tape is attached;
2. The semiconductor wafer of claim 1, wherein in said exposed region said conductor plug is spaced from said semiconductor substrate. - 前記導体プラグと前記半導体基板との間に、前記コンタクトホールの形成の際におけるエッチングレートが前記層間絶縁膜よりも低くなる低エッチングレート部材（２２）が配置されている、請求項２に記載の半導体ウェハ。 3. The low etching rate member (22) having an etching rate lower than that of the interlayer insulating film when forming the contact hole is arranged between the conductor plug and the semiconductor substrate. semiconductor wafer.
- 前記半導体素子は、トレンチゲート構造の縦型ＭＯＳＦＥＴもしくは縦型ＩＧＢＴであり、
前記低エッチングレート部材は、前記トレンチゲート構造を構成するゲート電極の材料であるポリシリコンによって構成されている、請求項３に記載の半導体ウェハ。 The semiconductor element is a vertical MOSFET or vertical IGBT with a trench gate structure,
4. The semiconductor wafer according to claim 3, wherein said low etching rate member is made of polysilicon which is a material of a gate electrode forming said trench gate structure. - 前記半導体基板にはトレンチが形成されており、
前記低エッチングレート部材は、前記トレンチ内に配置されている、請求項４に記載の半導体ウェハ。 A trench is formed in the semiconductor substrate,
5. The semiconductor wafer of claim 4, wherein said low etch rate member is located within said trench. - 前記導体プラグの幅に対する深さの比となるアスペクト比について、前記露出領域に形成される前記導体プラグの方が前記表面電極と接続される、もしくは前記保護膜によって覆われる前記導体プラグよりも高アスペクト比になっている、請求項２に記載の半導体ウェハ。 The conductor plug formed in the exposed region has a higher aspect ratio, which is the ratio of the depth to the width of the conductor plug, than the conductor plug connected to the surface electrode or covered with the protective film. 3. The semiconductor wafer of claim 2, having an aspect ratio.
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| JP2004363518A (en) * | 2003-06-09 | 2004-12-24 | Fuji Electric Device Technology Co Ltd | Method for manufacturing semiconductor device |
| JP2010103310A (en) * | 2008-10-23 | 2010-05-06 | Toyota Motor Corp | Method of manufacturing semiconductor device |
| JP2016152317A (en) * | 2015-02-17 | 2016-08-22 | 富士電機株式会社 | Semiconductor device manufacturing method |
| JP2017168659A (en) * | 2016-03-16 | 2017-09-21 | 富士電機株式会社 | Semiconductor device and manufacturing method |
-
2022
- 2022-07-07 JP JP2023534762A patent/JPWO2023286692A1/ja active Pending
- 2022-07-07 WO PCT/JP2022/027018 patent/WO2023286692A1/en unknown
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004363518A (en) * | 2003-06-09 | 2004-12-24 | Fuji Electric Device Technology Co Ltd | Method for manufacturing semiconductor device |
| JP2010103310A (en) * | 2008-10-23 | 2010-05-06 | Toyota Motor Corp | Method of manufacturing semiconductor device |
| JP2016152317A (en) * | 2015-02-17 | 2016-08-22 | 富士電機株式会社 | Semiconductor device manufacturing method |
| JP2017168659A (en) * | 2016-03-16 | 2017-09-21 | 富士電機株式会社 | Semiconductor device and manufacturing method |
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| JPWO2023286692A1 (en) | 2023-01-19 |
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