JPS58200295A - Envelope signal generator - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an envelope signal generator that generates various three-vane envelope signals of musical tone signals used in electronic musical instruments as digital data, and in particular, it is capable of generating signals of a wide range of shapes with a small amount of data. It is made possible to occur.

FIG. 1 is a block diagram of an electronic musical instrument employing the frequency control device of the present invention. 1 is a keyboard section, 2 is an operation section consisting of a tone tablet switch, a vibrato effect on/off switch, a volume for setting the depth of the vibrato effect, etc., and 3 is a central processing unit (CPTR), which is used in computers, etc. 4 is a read/write storage device (random access memory, usually called RAM), and 5 is a read-only storage device (read-only memory, usually called RAM) in which the program that determines the operation of CPU 3 is stored. (referred to as ROM), 7 is a ROM that stores envelope parameters among the parameters for synthesizing timbres;
It is M.

8 is the frequency control device of the present invention, 9 is the patent application No. 1986-165.
A sine wave generator such as No. 189, 1o an envelope signal generator, 11 a multiplier that multiplies envelope data representing the sine wave and the envelope signal, and 12 a multiplication result that is time-division multiplexed. , a time slot control device for changing the order of time division multiplexing,
13 is a time-division multiplexed phase modulator, 14 is a digital-to-analog converter, and 15.16 is an electroacoustic transducer.

Keyboard section 1, operation section 2, cpua, FIAM4, ROM5
, ROMe, ROM 7, frequency control device 8, and envelope signal generator 1o are coupled by a data bus, an address bus, and a control line.

This method of connecting data buses, address buses, and control lines is a well-known method for configuring minicomputers and microcomputers.
, there is nogi. Eight to 16 data buses are used, and data is transmitted and received on these bus lines not in one direction but in multiple directions in a time-division manner.

A plurality of address buses, for example 16, are prepared, and the CPU 3 normally outputs the address code, and other parts receive and receive the address code. The control line is usually
A memory request line (MREQ) II10 request line (IQRQ), read line ('') + write line (WR), etc. are used.

MRIEQ indicates reading and writing memory, IQR
Q indicates that the contents of the input/output device (Ilo) are to be read out, HD indicates the timing of reading data from the memory or Ilo, and WR indicates the timing of writing data to the memorizer 10.

An example of a microprocessor using such a control line is the microprocessor Z8O manufactured by Zilog.

Next, the operation of the electronic musical instrument shown in FIG. 1 will be described.

The keyboard section 1 is configured such that a plurality of key switches are divided into a plurality of groups, and the ON-OFF states of the key switches in the groups can be collectively sent to the data bus.

For example, in the case of a 6-octave keyboard, the 61 keys are divided into 10 groups of 6 keys (half an octave) and 11 groups of 1 group of only 1 key, and each group is assigned an address code of 1-6 pages. When an address code indicating one of the above groups arrives on the address line and l0RQ and RD are applied, the keyboard section 1 decodes the address code and selects the key switch 0N- in the corresponding group. 6 indicating OFF
Outputs a bit or 1 bit of data to the data bus. These can be constructed using decoders, bus drivers and some gate circuits. Of the operation section 2,
The tablet switch can have the same configuration as the keyboard section 1. For the volume setting status,
The voltage output from the volume is converted into a ci-digital code by an analog-to-digital converter and read out by l0RQ and HD.

cptrs reads the instruction code from the ROMes address corresponding to the program counter code inside it, decodes it, and performs arithmetic operations.

Performs tasks such as logical operations, reading and writing data, and jumping instructions by changing the contents of the program counter. The procedures for these operations are written in the 71-inch ROM 5. First, CPU3 is ROM5
Then, a command for importing data from the keyboard section 1 is read, and codes indicating 0ff-OFF of each key of the keyboard section 1 are fetched for each group. Then, the pressed key code is assigned to a finite channel of the musical tone generator.

Next, the CPU 3 sequentially reads a group of instructions from the ROM s for importing data from the operation section 2, decodes them, outputs the address code and control signals l0RQ and HD corresponding to the operation section 2, and outputs the data bus. outputs codes expressing the states of the switches and volume of the operating section 2, and reads them into the CPU 3. Then, the 3PU3 knows which tone of the musical tone signal should be synthesized.

Now that it is clear which tone with which frequency should be generated in which channel of the musical tone generator,
The CPU 3 outputs the address code and control signals MRKQ and R11 containing the frequency parameters of the desired timbre from the ROMe that stores data regarding the frequency of each timbre, and reads out the desired frequency parameters to the data bus. It is taken into 0PUa and written to the frequency control device 8. In order to write, 0PU3 outputs the address code corresponding to the data register provided inside the frequency control device 8, and at the same time outputs l0RQ and Wit, and when the WR double signal rises, it is output on the data bus. Data representing the frequency parameters being determined are written to the data register.

Next, timbre parameters representing the content of the timbre to be output are read from the ROM and written into a register inside the envelope generator 1o. Next, when a sound output command is given to both the frequency control device 8 and the envelope generator 1o, the frequency control device 8 gives the jump number J to the sine wave generator 9, and the envelope signal generator 1o generates envelope data. do.

The sine wave data output from the sine wave generator 9 and having a frequency proportional to the jump number J and the envelope data are multiplied, and an envelope is given to the sine wave. The sine wave data and envelope data are generated by being time-division multiplexed into nine pages. The time division multiplexing is, for example, 160 multiplexed, and 8 channels are provided by allocating a 2° sine wave to each channel. Normally,
By combining 20 sine waves, one musical tone is synthesized. Therefore, 20 sine wave data, known from the Fourier series formula, are added. Data addition between time slots for this purpose is performed by the time slot converter 12. The time slot converter is
Among the sine wave data strings modulated with envelope data that are time-division multiplexed and input in 160 time slots, predetermined data is added to reduce the number of time slots, or Japanese Patent Application No. 57-ZO2';ipc'-a
It exchanges time slots like a time division multiplex converter. The time division multiplexing phase modulator 13 performs multiple types of modulation simultaneously by time division multiplexing, as in Japanese Patent Application No. 66-182083 "Digital Musical Tone Modulation Apparatus". The output of the time-division multiplexing phase modulation device 13 is converted into an analog signal by an analog-to-digital converter 14, and multiple outputs are output from electroacoustic transducers 15 and 16.

Although not shown in FIG. 1, the time slot converter 12
and the time-division multiplexing phase modulation device 13 via the address bus, data path, and control line (coupled with the jPU3, the time slot The conversion and modulation conditions can be changed and set.

In FIG. 1, the envelope signal generator 1o outputs an address and a read command signal to the ROM 7 so that desired data can be directly read.

FIG. 2 is a block diagram of an embodiment of the envelope signal generator of the present invention. In FIG. 2, 7 is the parameter R
The OM stores data obtained by compressing the sample values of the envelope signal. 2o is a sample calculator, 21 is a tablet interface, 22 is a key interface, and 23 is an interpolation calculator.

The 11-page tablet interface 21 and the parameter ROM 7 are supplied with tone color codes from the CPU shown in FIG. The top three bits of the tone code are one of the eight types of instruments.
It is applied to the upper address of the parameter ROM 7 as a code for specifying the one, and selects the area in the parameter ROM 7 in which the parameters of the specified musical instrument sound are stored.

The lower bits of the timbre code include data indicating whether the timbre mode, tone, envelope shape, organ type, etc. Supplied. The tablet interface 21 includes a data latch, and the CPU 3 writes a tone code to the data latch, and then the sample arithmetic unit 2o reads it out at a necessary timing. 0PU3 is for the key interface 22,
Note octave data that represents the pitch of the sound you are trying to generate, and a key O that represents whether the key for that pitch is ON or OFF.
N, OFF signal and write to the internal latch. The sample calculator 2o reads out the data held by the tablet interface 21 and the key interface 22 according to internal predetermined timing, outputs address data to the parameter ROM 7 based on this data, and reads out the contents. , samples are generated by calculation and supplied to the interpolation calculator 23. The interpolation calculator 23 performs interpolation calculations, for example, linear interpolation, on the middle of the envelope samples that are supplied one after another, and outputs smoothly changing envelope samples.

FIG. 3 shows examples of envelope signals and their sample values for explaining the sample calculation applied in the present invention. FIG. 3(b) shows the envelope to be generated in dB scale, with the maximum value being OdB and the minimum value being -80 dB. On this curve, the black point (s
O+ sl 1 s2 + ”' ”・) is the time interval T
i=T and represents the sample value sampled at 2T. If we take the dB scale eave difference value of each sample value based on such data, we get (Le 0.ΔJ +
J”2 +・old・・）

Figure 3 (c+) on page 13 shows how the sample values indicated by the black dots in Figure 3 (b) are converted from the dB scale to the linear scale value (LEO+ ” 1
y L E2 +...), and the respective points are connected with dotted straight lines. In the present invention, the dB difference values ΔEo, Δ”+ shown in FIG.
+ΔE2+... is stored in the parameter ROM 7. By sequentially reading and accumulating these dB difference values, the dB scale eaves envelope sample SOH"
j +S2 +... is obtained.

Next, the dB scale eaves envelope sample is subjected to logarithmic-linear transformation to obtain an envelope sample LEo on the linear scale.

Obtain LXl, LK2,... The sampling period of this envelope sample is the above-mentioned Ti=T or 2T, but this period is larger than the period T of the musical tone sample that is finally output. Therefore, in order to successively generate envelope samples at times corresponding to the sample period of musical tones, samples LKo, IJ, are generated.

LE2. A linear interpolation calculation is performed between two adjacent samples of . . . to obtain an envelope sample having a shape as shown by the dotted line in FIG.

FIG. 4 on page 14 is a block diagram of an embodiment of the present invention, which implements the operational procedure described in FIG. In FIG. 4, the readout calculation control unit 25 controls tone code, note octave data, and key ON.
, OFF data, and according to these data, a timbre code and a dB difference value axi representing an envelope signal corresponding to the note octave data are stored, and an address AD of a certain address is sequentially generated, and a read command signal HD is generated. The fidB difference value ΔEi from the parameter ROM 7 is read out to the output terminal Do and stored in the latch 3o.

It is assumed that the latch 31 always contains zero.

The adder/subtractor 32 adds ΔEi and ze to produce aEi, which is supplied to one input of the adder/subtractor 32. The output of the adder Q·,5 subtracter 33 is stored in the register 34 and is also supplied to the logarithm-linear converter 36.

The output of the register 34 is supplied to the other input of the adder/subtractor 33. Register 34 is a one word latch. The adder/subtractor 33 and the register 34 function as an accumulator that accumulates aJ to generate and output n-+. The logarithmic-linear converter 36 is a read-only memory (ROM) that generates a linearized output code IJn for an input code Sn. If the input is 8 bits and the output is 16 bits, then 256
x16 = 4096 bits of ROM. Envelope sample IJn is applied to register 36 and delayed by one sample time.

Then, the subtracter 37 calculates ΔLXn=LEn-LKn. The output ΔIJn of the subtracter 37 is shifted downward by a predetermined bit in the bit shift register 38 and is supplied to one input of the adder/subtracter 39. The output of the adder/subtractor 39 is delayed by the music sample period TB in the shift register 4o and is supplied to the other input of the adder/subtractor 39. The bit shift register 38 is a kind of divider, and δB=(LEn Ll!:n-+)/(Tn-1/Ts
) (2) (n=2.3, 4. Old...) If it is a power of 2 like Tn-1//'I', = 2P(a), shifting P bits is Corresponds to calculation.

When δY is accumulated 2P times, ΔLE, = IJ:n-LEn,
(4) (n-2H3+' +...). Therefore, between LICn-1 and lICn0,
Linear interpolation can be performed in 'rn-1 time. The interpolated envelope samples are LEn, j = LICn −+ +i (”n ”n−
+ ) / (T!?1 / Tg) (6) (]
1 r .=...+Tn-+/Ts).

The generation of snl "n 14M-2δ is executed in Ti period. Therefore, the latch 30, register 34, 36
, the memory of the bit shift register 38 is updated by outputting the latch pulse from the read operation control section 26. The number of shift bits P of the bit shift register 38 corresponds to Ti/Ts outputted from the read operation control unit 26, and the number of shifted output codes En + ΔIl of multiple series of 17 pages is determined by the code representing P.
l:n/21 leKn/22. ...... is selected and its output is latched. The register 40 has a period Ts
Since the contents are updated every time, a latch pulse is supplied from the read operation control section 25 every cycle T8.

Figure 5 shows simplified envelope data (ΔX1) (i=1
, 2, 3. . . . is an example of N). The dB difference value ΔXi is placed at addresses 1 to N in the parameter ROM. The first address oi is the release address RAD
is stored. Now, for the sake of simplicity, Figure 3 (b
) where Ti (1-1+223+...) are all equal. When the key ON and OFF signals input to the readout calculation control unit 25 are pressed, the address D indicating the address O is first output to the ROM 7, the HD becomes o'', and the address is set to 1. The release address RAD stored in 0 is read out and stored in an internal register. Next, increment D by 1, set RD to o, and write 18 pages to +'r latch 3o at address 1. In the initial state, registers s□, 34.

If zero is stored at 36.38.40, S
, -0, LEl-0, JIIIC, =O, δ, =o. Therefore, the output of the adder/subtractor 33 becomes S2=Δ. After this, calculations are performed according to the procedure described above.

Addressum D increases by 1 each time i advances by 1.

If you keep pressing the key, Ti will advance more and more, but Ti-T1
5, the increment of the address AD is stopped, the contents of the bit shift register 38 are cleared to zero,
If the previous accumulated value is held, the envelope signal will be LF.
, 5 will remain.

After that, when the key ON and OFF signals become "0" and it is known that the key has been unlocked, it corresponds to Ti=T+s.
"ΔE15 is read out and the attenuation process from 815 to S16 begins. T+s is the release start point, and the address where the corresponding Δ"+5 is stored is set as the release address RAD.

Before Ti = T, s, the key ON and OFF signals are 0.
Then, instead of address D increasing by 1, it is rewritten to 19 page RAD and output, and ΔE15 is read out. And after that, RAI) +1.

RAD+2, . . . so that the release process proceeds. In this way, no matter what time the key is turned off, the camera can jump to RAD at that time or at a predetermined time as close as possible, and immediately enter the release after the key is turned off. Moreover, since the dB difference value is used, the connections become smooth. For example, if you jump from s12 to 815, there will be a discontinuity of about 6 dB, but if you jump from Δcap 1 to Δcap 5, after S and 2, there will be a smooth connection with sdB lower than the original data from 815 to 820. It turns out.

Therefore, no matter what the shape of the envelope is, no discontinuity will occur between the connections before and after the flight. Furthermore, since it is on the dB scale, the dB change (slope on the dB scale) per unit time in the release process is maintained. Therefore, the aural sensation of the time rate of the decay of musical tones will be the same no matter at what point the key is turned off.

The read arithmetic control unit 26 that realizes the operations described above includes a register that controls the address range, a register that stores the RAD, an arithmetic unit that increases, decreases, and changes the address, a so-called MLU, and a program that controls these. It can be realized using elemental circuits used in microcomputers, such as a ROM containing ROM and its decoder, in a manner similar to the sequence control of microcomputers.

FIG. 5 shows envelope data consisting of one dB difference value. This group of data can be stored separately for each different octave of the keyboard, and can be stored separately for each different note within one octave. By having separate data like this, you can use the optimal envelope for each key in each range, allowing you to create excellent tones in any range. For this purpose, the note octave data shown in FIG. 4 is received, the address 5D of the parameter ROM is changed according to this data, and the same format stored in addresses 0 to N in FIG. You can also select data.

In the data format shown in Figure 6, Ti is set constant, but since generally the envelope changes rapidly at the rise of a musical note, T
It is better to reduce i and increase the number of sample points. Ti
To be able to change the size of by i, the sixth
Just put it in the data format as shown in the figure. In Figure 6, the release address RAD is at address 0, the slope data 5LOPE is at address 1, the point interval A/PI and point nano (PN) are at address 2, and then Δz1 to Δ are at addresses 3 to 7.
! 5 is stored. Next, PI and PN are stored, followed by PA6 to ΔE14, and as the last group, PI and PN are stored at the RAD address, followed by ΔLs to Δ”19.
is stored. RAD is as described in Figure 6, 5
LOPIC is data indicating the average increment of the rising edge, and ΔE
1 to ΔE5 are commonly added. P.I.
is a code indicating the interval Ti between sample points, and PN is a code indicating how many points the sample point interval Ti lasts.

For the envelope shown in FIG. 3(b), the PI at address 2 specifies T1 and the PN is 5.

At address 8, PI is T6 (=2T,) and PN is 9.

In the release address RAII, PI specifies page 22 of T, and PN is 5.

The procedure for reading out the parameter ROM in the data format shown in FIG. 6 in the embodiment shown in FIG. 4 will be explained. When the key is turned on, first the RAD at address 0 is stored in the RAD register. Next, read the slope data 8LOPE from the register 31.
(Fig. 4).

After that, PI and PN are read out and stored in the PI register and PN register. Next, the value Δx1 at address 3 is read out and stored in the register 30. Then, subtract PN by 1 and PI
A bit shift code corresponding to Ti/TB determined according to is supplied to the bit shift register 38. In this way, the envelope sample LE during the interval T1
, , j are calculated.

Immediately before the end of T1, ΔTL2 is read from address 4 and stored in the register 3o, and PN is decreased by 1. In this way, when the address reaches address 7, PN=O, so it can be seen that PI and PN are stored next. Therefore, address 8 is read and stored in the PI register and PN register. Then, read out ΔT16 from the register 30.
The register 31 is cleared in the 23rd vane. Furthermore, find PN-1,
According to the PI code, T6 (= 2'i'1)
A bit shift code corresponding to the bit shift register 38 is supplied to the bit shift register 38. Since PN becomes zero when it reaches address RAD-1, it can be seen that PI and PN are stored next. Then, by performing the same operation as at address 8, the release process begins.

It can be determined that RAD is in the release process by comparing the data in the RAD register with the current address.1. !
After reading 11C19, the same ΔE19 is read out.
can be read out. If the key remains ON,
What is necessary is to stop before the RAD address. The key is RA
If D is turned OFF in the previous state, it is sufficient to rewrite the contents of the 5D register to RAJC and enter the release process.

If 5LOPIE data is provided as shown in Figure 6, ΔE1
The data length of the rising portion of ~ΔE5 can be reduced, and data can be compressed. 5LOPE data is shown in Figure 3(b)
represents the average slope of the envelope shape, and 5 for ΔE1 to Δ is the deviation from the slope. In the release process, reverse slope data, that is, negative slope data may be provided to RAD.

The read arithmetic control device 26 for reading out the parameter ROM in the 611th data format is internally equipped with a P register, a PM register, a Muku register, a RAD register, etc. as shown in FIG. ,
It can be constructed using well-known circuits for microcomputers, such as a ROM, a program counter, and an instruction decoder for instructing these operating procedures. Furthermore, it is also possible to construct the system using the microcomputer itself.

In the above explanation, the case where one Bc6 package route signal is issued is explained. Since musical tones generally consist of multiple frequency components, multiple envelope signals are required.

Furthermore, when producing not only a single melody but also multiple notes, a separate envelope signal is required for each note. For this purpose, in the embodiment of FIG. 4, registers 3, 4, 36
, 4Q are provided with a plurality of registers, and an adder 33
The .degree.26 vane 39, the subtracter 37, the logarithm-linear converter 35, and the bit shift register 38 may be time-division multiplexed for use. The registers 34, 36, and 40 may be shift registers having the same number of stages as the number of multiplexing units. The operation procedure of the readout calculation control unit 26 may also be configured to perform time-division operation in accordance with the number of multiplexed units.

FIG. 8 shows a configuration in which the sample arithmetic unit of the envelope signal generator of the present invention explained in FIG. This is an embodiment in which the calculation procedure is executed under program control.

In FIG. 8, reference numeral 50 denotes an address controller from 0PU3 to address code DR in FIG.

Data DB, input/output command signal 10RQ, write command signal W
In response to R, the address program D is sent to the parameter ROM 7, and the data specified by the address program D is read from the parameter ROM 7 from the data bus RDB. 61 is a timing pulse generator (TPG) which outputs a pulse signal necessary for the 26th page section based on the master clock frequency. The TPG 151 can be constructed using a clock oscillator, a counter, and a gate. Reference numeral 52 denotes a sequencer, which is a ROM that stores procedures for outputting addresses, write command signals, read command signals, etc., which will be described later, according to calculation procedures. Reference numeral 63 denotes an instruction decoder which inputs the instruction code output from the sequencer 52 and outputs an address code, a write command signal, and a read command signal.

54it,) In the remolo modulation register, the difference value of periodic fluctuation data that causes tremolo modulation is sent to the data bus RDB.
) The receiver is inserted and stored at the rising edge of WRl. OCl is “1”
", the contents are output to the bus. The slope register 66 receives the slope data from the data bus RDB and stores it at the rising edge of WB2. When 002 is "1", it is output to the bus.

Four address codes specifying one of the 120 registers in the slope register 65 are stored in the program D1. 56 is a dB difference register composed of 120 data registers, and one of the 27 registers is designated as D1. Then, at the rising edge of WB3, the data bus RDB receives and stores the pdB difference data, and when OC3 is "1", the contents and the data are output to the B bus. 57 is an envelope register consisting of 120 data registers, one of which is specified by the address codem D2, and the data S supplied from the C bus.
Store n at the rising edge of WB4. d when OC4 is 1”
Output the envelope sample data on the B scale to the A bus. 58 is a logarithmic-linear converter, which latches the data Sn supplied from the C bus at the rising edge of WB2, and outputs the logarithmic-linear converted envelope sample LICn to the bus when OC5 is "1". do. 69 is an envelope sample register consisting of 120 registers, one of which is specified by the address codem D3, and the envelope sample LEn supplied from the C bus is latched at the rising edge of WB2.
When 0061 is "1", it is output to the B bus. 6o is a working register (WRKG), which is composed of two word registers, one of which is selected by the address code D3, and the data supplied from the C bus is stored internally at the startup of WB2. When 0C7B is 1, the contents are output to the bus B, and when 0C7B is 1, the contents are output to the B bus.

61 is an adder/subtractor that calculates each input data of the A bus and B bus and outputs it to the C bus. The addition/subtraction switching selection is specified by the instruction decoder 63.

62 is a differential envelope data register that stores ΔLXn. One of the 20 registers is selected by the address code D4 and internally stores ΔIJn output from the adder/subtractor 61 at the rising edge of WR10.

63 is a differential envelope data register, which consists of 120 data registers, one of which is the address datum D6.
The input data is stored when WB2 rises and is output when OC8 is "1". 64 is a shift gate for shifting input data by a predetermined number of bits. The number of bits to be shifted is specified by the 5HIFT signal. The shifted signal corresponds to data δ. 66 is an adder and a subtracter for accumulation. A register 66 receives and stores the output of the adder/subtractor 65, and is composed of 120 registers. One of them is specified by address datum D6, and WB2
It is stored at the rising edge of , and output when 009 is 1.

In the embodiment shown in FIG. 8, 20 envelope signals corresponding to t)2o-order frequency components per note are generated simultaneously in 8 channels, that is, 8 notes, using 2° x 8 = 160.
It is designed to perform zero-fold time division multiplexing operation. The number of the 8 tones is represented by 1 to 8, and the number of the 20 tones is represented by I = 1 to 2o.

The calculation procedure will be explained next. Instead of the subscript n used earlier, i is used here.

WREG +-8LOF K (K, I) + 7
1E i(K, I) (6) WFtKG
4-WRKG +St (K, I)
(7) Si++(K, I)←WFIEG+ΔmM,
(K, I) (8) LOG /L IN,
WRKG + Δm Mi (K, I) (9) Ru'I
L i-H(Kj) 4+ LOG/LIN-LIC
i (K, I) θ0)L haze, (K, engineering)←LO
G/LIN (11) 3obe, -,ji First, according to equation (6), 8LOPΣ(K, I) is read out from the slope register 66, and the dB difference data Δxi(x
t) is read out from the dB difference register 66, added, and stored in the working register 6o. Next, the contents of the working register 6o and the contents 5i (K, I) of the envelope register 67 are read out and added together as shown in the equation (η), and stored in the working register 6o. The contents of the register 60 and the contents Δm Mi (KtI) of the tremolo modulation register 54 are read out and added, and a new envelope sample Si+1 (
K, engineering) is obtained, and this is stored in the envelope register 67 as (K,
, I > Store at address. Also, the same answer is written to the input latch of the logarithmic-linear converter 68 using equation (9).

Next, according to equation (1o), the logarithm-linear converter 68
The output of the envelope sample register 69 is read out, the difference Ei-+-+ (LI) is taken, and written to address ('I) of the differential envelope data register 62. Next, according to equation (11), the output of the logarithm-linear converter 58, LΣhai, (K, I), is written into the envelope sample register 69 at address 31/, (K, engineering). The above explanation and (6) to (
11) According to the formula, (Kll) points to one of the 8×20=160 word registers. l is a positive integer and is a sample number that increases sequentially starting from 1 after detecting the key ON.

To execute the above calculation procedure, the address codes D1-4, write command signals WR4-7.10, and read command signals oc1-e, 7a, 7b (6)-(11
) should be output in the order of the expressions.

Expressions (6) to (11) are first set to −1, and I=1 to
2o, then =2. . . . By going to 8, going in - order, and returning to the beginning, it is possible to advance i one by one.

The differential envelope data register 62 consists of a 20 word register with I=1-2 degrees. Therefore, after finding 20 new ΔL"i+1 (L-work) with work = 1 to 20, this new Δ"i+1 (Kll) is stored at the corresponding 20 addresses inside the differential envelope data register 63. transferred to the register. The speed of this transfer must match the reading speed of the differential envelope data register 63, that is, the updating speed of the address codem D6. Also, this speed is the final envelope data LI! : Corresponds to the period in which i and j are output. The address codem D6 of the differential envelope data register 63 always changes cyclically with a cycle of 160, and the signal X1 (K, I) is output one after another according to (K, I) determined by the address codem D5.

The shift gate 64 shifts ΔLEi (K, I) by a predetermined number of bits and outputs δi (Ni), which is accumulated by the adder/subtractor 66 and the register 66.

FIG. 9 shows an example of data in the parameter ROM 7 used in the embodiment shown in FIG. Address 0 indicates the basic nature of the sound, such as percussive or normal envelope. It consists of a MODE code and a harmonic restriction code that specifies the maximum number of envelopes from 1 to 20 to be output. Address 1 is the release address mentioned above. Addresses 2-21 are 20 envelopes 3371. , : A table of data specifying the number of envelope data to be used by each time slot corresponding to a signal. Addresses 22 to 41 are 20 pieces of slope data. Address 42 is the point interval PI of the startup multi-part and point number/(-PN.43~62.63~82
．． ......, 20 pages each for addresses 103 to 122
This is NN group dB difference data. These are the PI and PN at address 12323. 124-143, 144-1
63°164-183. - Old... 204 to 223 are 20 dB difference data each. From then on, the arrangement is the same. Multiple sets of parameters with such a configuration are prepared. Each set is provided corresponding to a specific range of a specific tone.

Address controller 50K (3PU3 (first
) from the address code, data, control signal l0RQ,
When WR is supplied, tone code 1 note octave data, key ON, OFF data are supplied, based on these data, 34, -, The start address of the area containing the parameter set corresponding to the note octave can be found (this start address may be given directly from the CPU 3).

This start address is read from the RDB to the parameter 10M and stored in the internal register of the address controller 5o. The addresses are advanced one after another, and data from addresses 0 to 21 is input. Next, the slope data is read from addresses 22 to 41 and stored in the slope data register 66. Next, the PI and PM at address 42 are stored in a predetermined register in the address controller 6o.

Next, for the dB difference data Δ of addresses 43 to 62, (K, I
) is stored in the dB difference register 56. Since the above data has been read, the calculations of equations (6) to (11) can be performed using the procedure described above. mode, harmonic limit code, release address, time slot/envelope number table, PI,
Since PN and the like are required for each channel, registers for storing each are provided inside the address controller.

In FIG. 9 on page 35, the harmonic limit code V is a number from 1 to 20, and specifies that zero is output as an envelope sample that exceeds this number M and is less than or equal to 20.

For this purpose, by applying a large negative number as aJ to (M+1) to 2o, a large negative number is set as ΔLF4, and by keeping the shift amount small, δi is set to a large negative number. shall be.

By doing this, the cumulative value in the adder/subtractor 66 becomes a negative number. On the other hand, in general, envelope samples may typically be zero or positive values. Therefore, adder/subtractor 85
When the calculation result of is negative, a control line 68 is provided to detect this and forcibly output zero. In this way, unnecessary envelope samples can be reduced to zero.

In FIG. 9, the time slot/envelope number table is I; dB difference data Δ”t(KtI) of the envelope i of any time slot from 1 to 20.
) (different data ΔJ (K, I). If we do this, then for Δ, (x, x), I=
It is not necessary to have all 1 to 2o, prepare 1 = 1 to 1o, and for I = 11 to 2o, select an appropriate one from I = 1 to 10, or one with a similar shape. You can do it like this. For this purpose, in the calculation of knees 11 to 2o, an address conversion operation such as outputting the address where ΔEi (KyI) corresponding to engineering=1 to 1o is stored may be performed. Such address conversion can be realized by operations similar to those of relative addresses and indirect addresses in microcomputers and minicomputers.

The data to be supplied to the tremolo modulation register 64 in FIG. 8 may be obtained by reading out differential PGM data of periodically varying waveforms stored in a ROM.

As described above, by using the sample arithmetic unit having the microprocessor structure shown in FIG. 8, a predetermined arithmetic operation can be performed by a program using a group of registers connected to a pass line, an adder/subtractor, and the like.

The procedure of equations (6) to (11) is one example, and by omitting some data or changing the procedure, various embodiments can be constructed in 37 bases.

Address controller 50. Since the timing pulse generator 51, sequencer 52, and instruction decoder 63 are already known in various microprocessors, their details will be omitted.

In the above explanation, if the key remains in the ON state, a certain envelope sample continues to be output before the release address (RAI), but when RAD-1 is reached, the envelope sample is sent to an even earlier address after that. For example, as explained in FIG. 3(B), address operations may be performed by repeating steps 86 to 815. Also,
Instead of repeating 86-S15, repeat S15 to S6-
It may be possible to jump to any address between 815 and 815.

Such address manipulation can be realized by adding or subtracting a random code output from a pseudo-random sequence generator to or from an address.

As a kind of release process, musical instruments require Dantsuku or high-speed muting. In the case of page 38 where such a request occurs, by setting the dB difference data to a large negative value, rapid attenuation can be achieved through accumulation. For this, Δ
It is sufficient to create a procedure for writing a predetermined value as Ei.

FIG. 10 is a diagram showing the timing of the embodiment of FIG. 8. Figure 10 (m) shows the sample arrangement of a sine wave waveform, and the sample period of one sine wave waveform is 20μ.
It is B. Figure 10) is an enlarged view of 20 μs, in which there are 8x20=160 time slots and 160 samples. Each sample has 12
Processed in Sng increments. Channel 1 (CHl) has 20 samples. The same applies to CH2N2. On the other hand, FIG. 10(C) shows the timing at which the difference envelope samples ΔIJi, , are calculated in synchronization with (&). Channel time slots in units of 160 μS CI (S is provided from 1 to 8).

In CH31, calculation of channel 10ΔLEi (+, I) is performed, and calculations of corresponding channels are performed in the following order. 1csoxs=1280 μs (1,28ms
)39, , , , The Xi calculation for each channel is repeated in cycles.

FIG. 10(D) shows the inside of each channel time slot CH8, with CH31 enlarged as an example. In CH31, there are processing time slots PTS 1 to 32 in units of 6 μB. PTS(I),
For I=1 to 20, difference envelope samples Δl4 corresponding to 20 spectra (sine waveforms) in channel 1
Calculate i(K, I). Then, in the first half of the 2.5μ intestine of pT82′l, the calculated 20 ΔLΣi(
K, I") values are transferred to the differential envelope register 63 (Fig. 8) in 125 ns increments as shown in Fig. 10. The timing of this transfer differs for CH31 to CH8. For example, in 0H8B, the It is executed in the latter half of the instruction time slots PT81-20. CE) in FIG. 10 is an enlarged view of the contents of each processing time slot PT81-20. It is divided into parts, each having a length of 830n8.In these instruction time slots ITS, the instructions of formulas (6) to (11) are executed.

Between PT81 and PT20, calculations centering on the adder/subtractor 61 are performed in the embodiment of FIG.

Between PT321 and PT32, Δm Mi (K
, I), 5LOPICi(K,I), Δxt(i
ctx) is newly written via the data bus DB.

In the shape of the envelope shown in Figure 3, in the case of a percussive type, if the attenuation is an exponential function, le can be a constant value in the attenuation process regardless of i, so it is the representative value in the attenuation process. As such, it is sufficient to have a kind of Δ-rich, and a large amount of data compression can be achieved.

As for the conversion characteristics of the logarithmic-linear converter 36 in FIG. 4, when the input Sn is small, for example, the ROM is configured so that zero is output as LE for an input code corresponding to -80 dB or less. It's okay.

As described above, according to the present invention, the following excellent effects can be obtained.

(1) Envelope samples are stored as digital data and interpolation calculations are performed based on this data. Smoothly continuous envelope signal data is generated based on sparse envelope samples. can get.

(2) Since the envelope samples are stored as differential data and accumulated, it is not appropriate to simply read out the envelope samples continuously. key ON→O
Even when changing to FF, a smooth envelope change can be created.

[Brief explanation of the drawing]

Figure 1 is a block diagram of an electronic musical instrument adopting the present invention;
3 is a block diagram showing the basic configuration of the present invention, FIG. 3 is a diagram showing the envelope signal waveform handled by the envelope signal generator of the present invention, FIG. 4 is a block diagram of the main part of the embodiment of the present invention, 5 and 6 are diagrams showing an example of the data format used in the present invention, FIG. 7 is a diagram showing an address calculation register, FIG. 8 is a block diagram of another embodiment of the present invention, and FIG. 9 is a diagram showing an example of the data format used in the present invention. is a diagram showing an example of the format of the data, and FIG. 10 is a diagram showing the timing chart. 42 Page 7... Memory device, 2o... Sample calculator, 23... Interpolation calculator. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 5
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Claims (1)

[Scope of Claims] (1) A digital storage device that stores envelope signals of musical tones, a sample calculator that sequentially reads envelope signals from the storage device and generates envelope samples, and the envelope sample an interpolation calculator that performs an interpolation calculation between adjacent ones, the data stored in the storage unit is a difference value between envelope samples, and the sample calculation unit sequentially accumulates the difference value. An envelope signal generator, especially adapted to generate envelope samples. (2. In the statement of claim 1, the storage device stores slope data corresponding to the slope in at least one of the rising and falling sections of the envelope signal, and the sample arithmetic unit uses the slope data. By adding the specified slope value to the envelope sample in the rising and falling sections, a steep envelope signal is generated.
Envelope signal generator that can be paged. (3) The envelope signal generating device as set forth in claim 1, in which the generation period of the envelope samples is made variable and the interpolation calculation interval is made variable in accordance with the generation period. (4) The envelope signal generating device according to claim 1, wherein the reading of digital data stored in the memory device is made to jump to the address of the release process when the key is OFF. (6) As set forth in claim 1, the digital data stored in the storage device is characterized in that when the key is kept ON for a long time, the address of the data changes randomly. Envelope signal generator. (6) The envelope signal generating device as set forth in claim 1, wherein the sample arithmetic unit and the interpolation arithmetic unit are time-division multiplexed to generate a plurality of envelope signals.