JPS58199538A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To isolate between elements by simultaneously performing the etching of an SiO2 film and the growth of an Si single crystal layer in high vacuum to form an element region, thereby preventing the disconnection of an electrode and the contamination of the surface of a substrate. CONSTITUTION:An SiO2 film 22 is formed on a P<+> type Si substrate 21, and a hole 23 is formed at the part which corresponds to the element forming region. Then, the substrate 21 is held in high vacuum, and Si is deposited while doping boron or the like. At this time, P type Si single crystal layers 24, 25 are formed, and an SiO2 film 22 is etched. Then, a CVD oxidized film 27 is formed to bury a V-shaped groove 26, and a resist film 28 is further coated. Thereafter, the surfaces of the P type Si single crystal layer 25 and the remaining SiO2 film 22' are etched by an RIE method or the like to be exposed. In this manner, an element region in which elements are isolated flatly can be formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of manufacturing a semiconductor device in which elements are isolated using an oxide film.

[Technical background of the invention and its problems]

Conventionally, as a method for separating elements in highly integrated circuits, for example, I, o
A method of manufacturing a semiconductor device using the COG method (selective oxidation method) is known. In this method, a portion of the element isolation oxide film corresponding to the film thickness W is provided below the surface of the silicon substrate by selective oxidation. However, according to this method, during thermal oxidation, oxidation progresses laterally under the silicon nitride film used as an oxidation-resistant mask, resulting in so-called bird's beak. As a result, the device region is short on both sides, resulting in a reduction in the degree of device integration.

For these reasons, recently, methods for manufacturing semiconductor devices using element isolation methods such as selective oxidation technology (5EPOX) using polysilicon and buried oxidation technology (BOX) have been proposed.

First, a case in which 5EPOX is applied to a method of manufacturing a MOS transistor will be described based on FIGS. 1(a) to 1(g). First, a first 5I layer is placed on a p-type silicon substrate 1.
O2 membrane 21. Polycrystalline silicon layer 3. Second SiO□ film 2
2 (as shown in FIG. 1(a)).

Subsequently, an 813N4 film is deposited on the entire surface and patterned to form a 513N4 pattern 4 (as shown in FIG. 1(b)). Subsequently, using this 813N4 pattern 4 as a mask, p-type impurities are ion-implanted and activated to form p+-type channel stopper regions 5 in the substrate 1. Next, the polycrystalline silicon layer 3 is selectively oxidized using the 513N4 mother turn 4 as an oxidation-resistant mask to form a thick oxide film 6 (as shown in FIG. 1C). Next, the above 81. N4/1,000 turns 4. The polycrystalline silicon layer 3 under the second 5IO2 film 22.5t3N4 thousand turns 4 and the first StO□ film 21
All 21 are removed to expose a part of the surface of the substrate 1. At this time,
Polycrystalline silicon layer 3 in the overhang part of thick oxide film 6
As shown in FIG. 1(d), an inter-element isolation film 7 having a convex 9-shaped portion on the element region side in the lateral direction is formed. Thereafter, a dirt oxide film 8 is formed on the exposed substrate 1 by a conventional method, a dirt electrode 9 is formed on this f-) oxide film, and an n-type source and drain (not shown) are formed on the substrate 1. An n-channel MO8) runnostar is manufactured by forming an n-channel MO8) (as shown in FIG. Although integration can be achieved, it is difficult to perform implantation into the substrate at a deep position using 513N4/# turn 4 as a mask, and the steps of the element isolation film 7 are steep, making it difficult to perform f.
f-) There was a risk of breakage during formation of the electrode 9.

Next, a case in which the present invention is applied to a method of manufacturing a 5EPOX MOS transistor will be described based on FIGS. 2(&) to (f). First, a layer of Example 1fA is deposited on a p-type silicon substrate 1 and subjected to i4 turning to form an A/arm turn IO (as shown in FIG. 2(a)). Subsequently, (7) the exposed substrate 1 is appropriately removed by RIE using the A-horn turn 10 as a mask, and an island-shaped portion 11 is formed under the A-horn (turn 10).Next, the substrate I is subjected to thermal oxidation treatment. A third SiO2 film 23 is then deposited on the surface of the substrate 1 and on the side of the island IZO.Subsequently, p-type impurities are ion-implanted into the surface of the substrate 1 using the A-shaped turn 10 as a mask, and activated to form a p-type impurity.
After forming the + type channel stopper region 5..., a plasma S10□ film I2 is formed on the entire surface (as shown in FIG. 2(b)). This plasma 5102 film I2 is then diluted and treated with a HF solution. At this time, the plasma 5IO2
The film 12 remains on the A-tube turn 20 of the island portion II, and the third StO□ film 23 excluding the island portion 11 23
Upper part 1-5 - Remains at the same level as the surface. Note that a V-groove 13 is formed between the residual plasma 8102 film 12' on the third 5I02 film 23 and the island portion 11 (as shown in FIG. 2(c)).

Further, after removing the A horn amount turn ZO by etching and lifting off the plasma 5IO2 film remaining on the island portion 11, a CVD 5iO□ film 14°resist film 15 is sequentially formed on the entire surface (FIG. 2(d)). (Illustrated).

Subsequently, the resist film was heated to 15°CV by RIE method.
D5 Remove the IO2 film I4 until its removed surface is at the same level as the surface of the island-shaped portion 11, and apply CVD only to the V-groove 13.
The oxide film 14' remains, and this remaining CVDSiO2 film 1
4' and the residual plasma 5to2 film 12' perform isolation between elements. After that, a dirt oxide film 8 is formed on the exposed substrate 1 by a conventional method, a gate electrode 1 is formed on this f-) oxide film 8, and an n+ type source region and a drain region are further formed on the substrate 1. (not shown) to form an n-channel M
O8) Manufacture a lansosta (as shown in FIG. 2(f)). However, according to such a manufacturing method, since the substrate 1 is selectively removed by the RIE method using the AtsunoLean 10 as a mask, the ldl□turn 10 and the atmospheric gas react, and the exposed substrate 1 is removed. There was a risk of surface contamination.

[Purpose of the invention]

The present invention was made in view of the above-mentioned circumstances, and eliminates the problem of electrode breakage and A! It is an object of the present invention to provide a method for manufacturing a semiconductor device that can prevent contamination of a substrate surface due to a pattern.

[Summary of the invention]

The present inventor has discovered that when Si evaporation is performed on a St substrate in a high vacuum,
Etching of the 5i02 film occurs above a certain substrate temperature,
The present invention was completed based on the fact that selective growth is possible by etching the 5102 film and growing the 81 single crystal layer on the Sl substrate surface. That is, in the present invention, after forming an oxide film on a semiconductor substrate of a first conductivity type and removing the oxide film corresponding to a portion where an element is to be formed to provide an opening portion,
The oxide film is etched by epitaxial growth on the substrate to reduce the thickness of the oxide film, and a semiconductor single crystal of the first conductivity type having approximately the same thickness as the oxide film remaining on the substrate exposed from the opening is formed. By forming layers,
The main idea is to keep the bare surface of the element formation area and the residual oxide film at the same level, thereby facilitating isolation between elements in subsequent processes, and preventing disconnection of wiring such as dirt electrodes and contamination of the substrate surface.

[Embodiments of the invention]

The case where the present invention is applied to an n-channel MO8) Lanzostar will be explained based on FIGS. A 810□ film 22 of 810□ was formed (third
Figure (a) shown). Subsequently, a portion of the 5io2 film 22 corresponding to the element formation portion was removed by photolithography to form an opening 23 (as shown in FIG. 3(b)). Next, the substrate 21 is set in a predetermined vacuum apparatus, and the substrate temperature is increased to 1 while doping boron in the air at different concentrations.
SS for 10 minutes at 000°C and a deposition rate of 6 μm/hr.
Fumigation was performed. As a result, as shown in FIG. 3(C), a p-type 81 single crystal layer 2 is formed on the substrate 21 exposed through the opening 23.
4. A 1 μm thick single crystal layer consisting of the p-type 81 single crystal layer 25 is formed, and the SlO□ film 22 is formed with a thickness of 1 μm.
The part corresponding to h was etched. and thickness 1
A 8102 μm thick film 22' remained, and a V-groove 26 was formed between this remaining 5IO2 film 22' and the single crystal layer.

[1)] Next, after forming a CVD oxide film 27 on the entire surface so that the V groove 26 is sufficiently filled, the CVD oxide film 27 is
A rainbow resist film 28 is applied thereon (as shown in FIG. 3(d)). Since the resist film 28 has viscosity, its surface becomes flat. Subsequently, the p-type 81 is etched by the RIE method under the condition that the etching rate of the resist film 28 and the CVD oxide film 27 is 1:1.
The surface of the single crystal layer 25 and the remaining 8102 film 22' were removed until they were exposed. As a result, only the V groove 26 has a CV
A D oxide film 27' remained, and isolation between elements was performed by this remaining CVD oxide film 27' and the remaining SIO□ film 22'.
Figure 3 (-) shown). Thereafter, an r-) oxide film 29 is partially formed on the p-type St single crystal layer 25 by a conventional method, and the p-type S1 single crystal layer is formed using this gate oxide film 29 as a mask. An n-type source region 30 and a drain region 31 are formed in 25, and an A7 film is deposited on the entire surface and patterned to form a dirt electrode 32 on the dirt oxide film 29 and a part of the source region so and drain 3Z, respectively. A desired U-channel MOS transistor was manufactured by forming connecting wirings 33 and 33 (as shown in FIG. 3(f)).
.

According to the manufacturing method described above, the 5102 film 22
An element region is formed by simply vapor depositing Si miraboron doping on the substrate 21 exposed through the opening 23,
Then, by forming a CVD oxide film 27 and a resist film 28 and removing these films 27 and 28 by RIE method, V
In order to leave the CVD oxide film 27' only in the groove 26, this remaining CVD oxide film 27' and the remaining 5IO2 film 22'
It is possible to easily perform agglomerate separation.

In addition, the surface of the p-type Si single crystal layer 10-25, the remaining SIO□ film 22', and the remaining CVD oxide film 2, which will become a part of the element region, are also covered.
Since the surfaces of 7' are at the same level, the dirt electrode 32 and wiring can be formed flat without the risk of breakage as in the conventional method.Furthermore, when isolating between elements, the A-flange turn can be used as a mask as in the BOX method described above. Because RIE is not performed,
Contamination of the exposed substrate surface can be prevented.

In the above embodiment, a case has been described in which p-type and p-type silicon single crystal layers are formed on a substrate by vapor deposition of Sl, but the present invention is not limited to this. For example, if the substrate temperature is increased appropriately, 5ta4. It can also be formed by gas plasma decomposition using STC-4 or the like or CVD. Furthermore, by doping the silicon single crystal layer once formed with a U-type impurity such as phosphorus or arsenic, the single crystal layer can be made into an n-type, or by doping with a p-type impurity such as Ron. Accordingly, the impurity concentration of the single crystal layer can be increased.

Furthermore, although silicon was used as the substrate in the above embodiment,
It is not limited to this. For example, the substrate is 81 and the compound is 8I.
2, any substance can be used as long as S +5I2 (solid) → 28I (gas).

Specific examples include Ge (ff rumanium) and the like.

Further, in the above embodiment, the case of manufacturing a MOS (MOS) transistor was described, but the present invention is not limited to this, and can be similarly applied to a semiconductor device having a high-density integrated circuit such as a 2-inch impolar transistor.

〔Effect of the invention〕

As described in detail above, the present invention provides a method for manufacturing highly reliable semiconductor devices such as MOS transistors, etc., in which elements can be separated in a package without causing disconnection of electrodes or contamination of the substrate surface. It is possible.

Yarnell MO8) Cross-sectional diagrams showing the manufacturing method of transistors in order of process, Figures 2 (&) to (f) are B as an element isolation technology.
3 (IL) - (
f) is a cross-sectional view illustrating the manufacturing method of a MOS (MOS) lansoster according to the present invention in the order of steps;

2I... p + type silicon substrate, 22... 5 IO2 film, 22 residual StO□ film, 23... opening, 24...
・p-type St single crystal layer, 25...p-type Si single crystal layer,
26...V groove, 27-CVD5iO□ film, 27'...
・Residual CVDSiO2 film, 28...Resist film, 29
. . . e-t oxide film, 30 . . . meter-shaped source region, 31
...? Type drain region, 32... dart electrode, 33
···wiring.

Applicant's agent: Patent attorney Suzue Takehiko = 13-

Claims (1)

[Claims] 1. Forming an oxide film on a semiconductor substrate of a first conductivity type, and forming an opening by selectively removing a portion of the oxide film corresponding to a portion where an element is to be formed. the oxide film is etched to reduce the thickness of the oxide film by epitaxially growing a semiconductor material while impurities of a first conductivity type are pumped; A method for manufacturing a semiconductor device, comprising: forming a first conductivity type semiconductor single crystal layer having substantially the same thickness as the remaining oxide film. 2. After forming a semiconductor single crystal layer of a first conductivity type on a substrate, an impurity of the first conductivity type or a second conductivity type is introduced into the single crystal layer. A method for manufacturing a semiconductor device according to section 1. 3. After forming a semiconductor single crystal layer of the first conductivity type on the substrate, the entire surface is covered with an insulating film, and then this insulating film is removed down to the semiconductor single crystal layer and the oxide film surface to form a remaining oxide film. Claim 1 is characterized in that the insulating film is left only in the V-groove between the semiconductor single-crystal layer and the semiconductor single-crystal layer, and the semiconductor single-crystal layer is separated by the remaining oxide film and the insulating film in the V-groove. A method for manufacturing a semiconductor device.