JPS58196036A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS58196036A
JPS58196036A JP7933382A JP7933382A JPS58196036A JP S58196036 A JPS58196036 A JP S58196036A JP 7933382 A JP7933382 A JP 7933382A JP 7933382 A JP7933382 A JP 7933382A JP S58196036 A JPS58196036 A JP S58196036A
Authority
JP
Japan
Prior art keywords
film
substrate
groove
semiconductor device
thin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7933382A
Other languages
Japanese (ja)
Inventor
Tadanaka Yoneda
米田 忠央
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP7933382A priority Critical patent/JPS58196036A/en
Publication of JPS58196036A publication Critical patent/JPS58196036A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent the deterioration of LSI characteristics as well as to improve the yield rate for the titled semiconductor device by a method wherein a reflecting film, which reflects energy rays, is formed on the prescribed region located on the surface of a semiconductor substrate. CONSTITUTION:A reflecting film 21 is formed on a silicon substrate 20, and the substrate is placed in the atmosphere containing gas to be used for formation of a thin film. At this time, a beam of light having the wavelength liable to reflect by the film 21 and also absorbed by the substrate 20, is irradiated. No temperature rise is observed on the film 21, but temperature rise is observed on a groove 23. Accordingly, almost no thin film is formed on the film 21, but an SiO2 film for isoration is formed in the groove.

Description

【発明の詳細な説明】 本発明は半導体装置の製造方法に関し、特に半導体基板
表面上の所定の領域のみに薄膜を形成することのできる
半導体装置の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which a thin film can be formed only in a predetermined region on the surface of a semiconductor substrate.

半導体基板上にCVD5法で薄膜を形成すると基板表面
にほぼ同じ厚さの薄膜が形成されるため、薄膜形成後不
要の薄膜を除去しなければならない。
When a thin film is formed on a semiconductor substrate by the CVD5 method, a thin film of approximately the same thickness is formed on the surface of the substrate, so that unnecessary thin films must be removed after the thin film is formed.

例えば従来の絶縁分離方法を第1図A−Cに示す。For example, conventional insulation isolation methods are shown in FIGS. 1A-C.

まずSi基板1の分離形成領域に深さDが約16μmの
溝2を形成する(第1図A)。
First, a groove 2 having a depth D of approximately 16 μm is formed in an isolation formation region of a Si substrate 1 (FIG. 1A).

そしてCVD法により、厚さ約16μmのS x02膜
3を形成して溝2を5102膜3で埋める。そして溝の
上部にホトレジスト膜4を形成する(第1図B)。
Then, by the CVD method, an S x02 film 3 having a thickness of about 16 μm is formed, and the groove 2 is filled with the 5102 film 3. A photoresist film 4 is then formed on the top of the groove (FIG. 1B).

次に、プラズマエツチング法もしくはスパッタエツチン
グ法によりS X 02膜3をエツチングして溝2のみ
に8102膜3を残す。S 102膜をエツチングする
際、不均一にエツチングが進んだり、5102膜3の膜
厚不均一なために8102膜が残っている領域6やエツ
チングが進み過ぎてSi基板がエツチングされている領
域6が生じる(第1図C)。
Next, the S X 02 film 3 is etched by plasma etching or sputter etching, leaving the 8102 film 3 only in the groove 2 . When etching the S102 film, the etching progresses unevenly, or the area 6 where the 8102 film remains because the thickness of the 5102 film 3 is uneven, or the area 6 where the etching progresses too much and the Si substrate is etched. occurs (Fig. 1C).

上記のようにSi基板上に8102膜残り6や凹部6が
生じてしまうためにLSIの歩留が低いという問題があ
る。
As mentioned above, there is a problem that the yield of LSI is low because the 8102 film remains 6 and the recesses 6 are formed on the Si substrate.

また、多層配線の場合の従来の方法を第2図に示す。S
i基板10上にSio2膜11膜形1されていて、厚さ
約04μmの第1層目のAμ配線12が形成し、その上
にプラズマCVD法により厚さ約1μmの8102膜1
3を形成する0そして第1層目のへ!配線12に直行し
て第2層目のAIt配線14を形成する。この場合、第
1層目のAfi配線12のために断差部16が生じて、
第2層目のM配線14が断線し易いし、微細なパターン
を形成することが困難である。
Further, a conventional method in the case of multilayer wiring is shown in FIG. S
A Sio2 film 11 is formed on the i-substrate 10, and a first layer Aμ wiring 12 with a thickness of about 0.4 μm is formed, and an 8102 film 1 with a thickness of about 1 μm is formed on it by plasma CVD.
0 forming 3 and on to the first layer! A second layer of AIt wiring 14 is formed directly to the wiring 12. In this case, a difference 16 is generated due to the first layer Afi wiring 12,
The second layer M wiring 14 is easily disconnected, and it is difficult to form a fine pattern.

本発明は半導体基板上の所定の領域のみ温度を上げて、
この温度の上った領域上にのみ薄膜を形る。基板上の所
定の領域のみ温度を上げる方法として半導体基板上の所
定の領域に光線等のエネルギー+1!を反射する反射膜
を形成し、前記基板上に熱線、赤外線、可視光線、紫外
線等の前記エネルギー光線を照射して反射膜が形成され
ていない領域の温度を上げることにより、反射膜を形成
されていない半導体基板上に反応生成物が形成される半
導体装置の製造方法を提供するものである。また、絶縁
分離領域形成に適用する場合は半導体基板上に光を反射
する反射膜を形成し、分離形成領域の半導体基板上の前
記反射膜を除去し、さらに、前記半導体基板をエツチン
グして溝を設けた後、前記反射膜領域よりも前記溝部の
方が温度が高くなるようにして絶縁膜を生成するガス雰
囲気中に前記基板をおいて溝部に絶縁膜を形成1−1分
離領域の幅が大きくならず、しかも分離領域の凸部(バ
ードビーク)がなく、しかも分離領域の歪が少い半導体
装置の製造方法を提供するものである。
The present invention raises the temperature only in a predetermined area on a semiconductor substrate,
A thin film is formed only on the area where the temperature has risen. As a method of increasing the temperature of only a predetermined region on a semiconductor substrate, the energy of a light beam, etc. is +1! The reflective film is formed by forming a reflective film that reflects energy on the substrate, and irradiating the substrate with the energy rays such as heat rays, infrared rays, visible light, and ultraviolet rays to raise the temperature of the area where the reflective film is not formed. The present invention provides a method for manufacturing a semiconductor device in which a reaction product is formed on a semiconductor substrate that is not stained. When applied to the formation of an insulating isolation region, a reflective film that reflects light is formed on the semiconductor substrate, the reflective film on the semiconductor substrate in the isolation formation region is removed, and the semiconductor substrate is etched to form grooves. After forming an insulating film in the groove, place the substrate in a gas atmosphere that generates an insulating film so that the temperature in the groove is higher than that in the reflective film region.1-1 Width of the isolation region To provide a method for manufacturing a semiconductor device in which the separation region does not become large, there is no protrusion (bird's beak) in the isolation region, and the distortion in the isolation region is small.

多層配線に適用する場合は第1層目の配線形成後、上記
絶縁分離形成の場合と同じように絶縁膜を生成するガス
雰囲気中で基板に光線を照射して配線領域以外に絶縁膜
を形成して表面を平坦にする半導体装置の製造方法を提
供するものである0本発明の第一の実施例として絶縁分
離に適用してMO3LSIを製造する場合を第3図A〜
第3図Eに従って説明する。
When applied to multilayer wiring, after forming the first layer of wiring, the substrate is irradiated with light in a gas atmosphere that generates an insulating film to form an insulating film in areas other than the wiring area, as in the case of forming insulation separation described above. As a first embodiment of the present invention, the case where MO3LSI is manufactured by applying it to insulation isolation is shown in FIGS.
This will be explained according to FIG. 3E.

p形シリコン(St)基板20上に厚さ約o1μmの光
を反射する反射膜(例えばAJL、Cr  のような金
属膜)21を形成する。そしてホトリソ技術を用いて分
離領域形成領域以外にホトレジスト膜22を形成する(
第会図A)。
A reflective film (for example, a metal film such as AJL or Cr) 21 that reflects light is formed on a p-type silicon (St) substrate 20 to a thickness of about 01 μm. Then, using photolithography technology, a photoresist film 22 is formed in areas other than the isolation region forming area (
Diagram A).

次に、ホトレジスト膜22をマスクにして反射膜21を
除去する。さはにシリコン基板2oを約06μmエツチ
ングして溝23を形成する。さらにホトレジスト膜22
をマスクにして溝23の底面にボロンをイオン注入領域
24を形成する(第3図B)。
Next, the reflective film 21 is removed using the photoresist film 22 as a mask. Then, the silicon substrate 2o is etched by about 0.6 μm to form a groove 23. Furthermore, the photoresist film 22
A boron ion implantation region 24 is formed on the bottom surface of the trench 23 using the mask as a mask (FIG. 3B).

次に、ホトレジスト膜22を除去する。そして第4図に
示すように、冷却基板26.枠26.透明ガラス窓27
で囲まれた反応装置の冷却基板26上にシリコン基板2
0’5置く。そして反応装置内をS III(4ガス、
o2ガスの混合ガス雰囲気にするOそして反射膜21に
よって反射し易(Si基板は吸収し易い波長の光2(例
えばArレーザー光、 YAGレーザ−、キセノンラン
プの光等の04μ〜1μの波長の光)?ニガラス窓27
を通して照射する。
Next, the photoresist film 22 is removed. As shown in FIG. 4, the cooling board 26. Frame 26. transparent glass window 27
A silicon substrate 2 is placed on the cooling substrate 26 of the reactor surrounded by
Place 0'5. Then, the inside of the reactor was filled with S III (4 gases,
Create an atmosphere of a mixed gas of O2 gas and reflect it easily by the reflective film 21. light)?Nigarasu window 27
irradiate through.

そうすると、第6図に示すように反射膜21上は光が反
射して温度が上昇しないが、溝23はシリコン基板が露
出しているため、光が吸収され、溝23領域の温度が上
る。冷却基板26はフレオンガスもしくは冷却水を流し
て約30℃に冷却しているので、溝23領域で発生した
熱りはシリコン基板2oの裏側の方へ流れる。そのため
に反射膜21@下のシリコン基板2oはあまり温度が上
がらない。そこで、溝23領域の温度がS IH4ガス
と02ガスが反応してS i02膜が生成する温度(約
sso℃)  になるように、レーザーのノくワーもし
くはランプの電力を設定する。
Then, as shown in FIG. 6, light is reflected on the reflective film 21 and the temperature does not rise, but since the silicon substrate is exposed in the groove 23, light is absorbed and the temperature in the groove 23 area increases. Since the cooling substrate 26 is cooled to about 30° C. by flowing Freon gas or cooling water, the heat generated in the groove 23 region flows toward the back side of the silicon substrate 2o. Therefore, the temperature of the silicon substrate 2o under the reflective film 21 does not rise much. Therefore, the power of the laser blower or the lamp is set so that the temperature in the groove 23 region becomes a temperature (approximately sso° C.) at which the SIH4 gas and the 02 gas react to form a Si02 film.

上記条件で光を照射すると、第3図Cに示すように、溝
23に分離用S z 02膜28が形成し、溝が埋まる
。一方、反射膜21上は温度が上らないためほとんどS
 102膜が形成されず島状のSio2膜29膜形9さ
れるのみである。
When light is irradiated under the above conditions, a separation S z 02 film 28 is formed in the groove 23, filling the groove, as shown in FIG. 3C. On the other hand, the temperature on the reflective film 21 does not rise, so almost no S
102 film is not formed, and only an island-shaped Sio2 film 29 film 9 is formed.

次に、反射膜21がエツチングすると反射膜21と共に
SiO2膜29が除去される(第3図D)。
Next, when the reflective film 21 is etched, the SiO2 film 29 is removed together with the reflective film 21 (FIG. 3D).

その後、ソース領域30.ドレイン領域31゜ゲート酸
化膜32.多結晶Si膜33を形成する。
Thereafter, the source region 30. Drain region 31° gate oxide film 32. A polycrystalline Si film 33 is formed.

また、途中の熱処理によってイオン注入領域24のボロ
ンが拡散してp+形チャネルストッパー領域34が形成
される(第3図E)。
Further, during the heat treatment, boron in the ion implantation region 24 is diffused to form a p+ type channel stopper region 34 (FIG. 3E).

以上第3図の方法によれば、分離すべき領域のみに絶縁
膜(実施例の場合はS 102膜)を形成し、溝を埋め
るので金属膜21を除去をすれば平坦なSi基板が露出
する。そのために歩留の高いLSIを得ることができる
According to the method shown in FIG. 3, an insulating film (S102 film in the example) is formed only in the region to be separated and fills the trench, so when the metal film 21 is removed, a flat Si substrate is exposed. do. Therefore, LSIs with high yield can be obtained.

さらに、高温加熱工程なしで溝23に絶縁物(実施例の
場合は5IO2)を埋めているので、基板に歪が生じず
、結晶欠陥が生じることはない。
Furthermore, since the groove 23 is filled with an insulator (5IO2 in the example) without a high-temperature heating process, no distortion occurs in the substrate and no crystal defects occur.

そのために基板20とソース、ドレイン30.31間の
p−n接合のリーク電流が小さい。捷だ、分離領域の面
積は溝23の幅よりも大きくならないため、受動、能動
素子形成領域の面積が小さくならずLSIの特性悪化を
防ぐことができる。さらに、バードビークが生じず平坦
な分離領域が可能となるので微細パターンを歩留よく形
成できる。
Therefore, the leakage current at the pn junction between the substrate 20 and the source and drain 30, 31 is small. However, since the area of the isolation region does not become larger than the width of the trench 23, the area of the passive and active element formation regions does not become smaller, and deterioration of the characteristics of the LSI can be prevented. Furthermore, since bird's beaks do not occur and a flat separation region is possible, fine patterns can be formed with high yield.

なお、上記工程はMO3LSIについて述べているが、
バイポーラLSIについても同じことがいえる0 以上のように、第3図の方法は結晶欠陥が生じず、分離
領域の幅が大きくならず、凸部のない分離領域を形成で
き、高密度な半導体装置の製造に大きく寄与するもので
ある。
Although the above process describes MO3LSI,
The same can be said for bipolar LSIs. 0 As described above, the method shown in Figure 3 does not cause crystal defects, does not increase the width of the isolation region, can form isolation regions without protrusions, and is suitable for high-density semiconductor devices. This greatly contributes to the production of

本発明の第2の実施例として多層配線に適用した場合を
第6図A〜第6図Cに示す。
A second embodiment of the present invention in which the present invention is applied to multilayer wiring is shown in FIGS. 6A to 6C.

まずSt基板4o上に厚さ約06μmの8102膜41
上に厚さ約04μmの第1層目の導体配線42(例えば
Aj! 、 An−Si合金)を形成する(第6図A)
First, an 8102 film 41 with a thickness of about 06 μm is placed on the St substrate 4o.
A first layer conductor wiring 42 (for example, Aj!, An-Si alloy) having a thickness of about 0.4 μm is formed thereon (FIG. 6A).
.

次に、第4図、第6図に示したように光線を照射しなか
らS iH4と02ガス雰囲気中に基板を置く。
Next, as shown in FIGS. 4 and 6, the substrate is placed in an SiH4 and 02 gas atmosphere without being irradiated with light.

そうすると導体配線42は光線を反射するために、S 
102膜41上にのみ厚さ約04μmのSio2膜43
膜形3されて、表面が平坦になる(第6図B)。
Then, in order to reflect the light beam, the conductor wiring 42
Sio2 film 43 with a thickness of approximately 04 μm is placed only on the 102 film 41.
The surface is flattened (FIG. 6B).

次に、上記基板上にCVD法により、厚さ約05μmの
3102膜44を形成する。そして第1層目の導体配線
42に直行した第2層目の導体配線46を形成する(第
6図C)。
Next, a 3102 film 44 having a thickness of about 05 μm is formed on the substrate by CVD. Then, a second layer of conductor wiring 46 is formed which is perpendicular to the first layer of conductor wiring 42 (FIG. 6C).

第6図に示す工程ではS 102膜44表面上は平坦で
あるため、第2層目の導体配線46は微細パターンを形
成することができるし、断線が生じることはない。
In the step shown in FIG. 6, since the surface of the S102 film 44 is flat, a fine pattern can be formed in the second layer conductor wiring 46 without causing any disconnection.

上記工程は薄膜としてS 102膜形成の場合を述べて
いるが、S IH4ガス雰囲気中にすればSi薄膜が形
成されるし、NH3ガスと5iH2C22ガスの混合ガ
ス雰囲気中にすればSi3N4薄膜が形成されるので所
望の薄膜が得られるようなガス雰囲気中にすれば良い。
The above process describes the case of forming an S 102 film as a thin film, but if it is in an S IH4 gas atmosphere, a Si thin film will be formed, and if it is in a mixed gas atmosphere of NH3 gas and 5iH2C22 gas, a Si3N4 thin film will be formed. Therefore, it is sufficient to use a gas atmosphere in which a desired thin film can be obtained.

本発明によれば所定の領域のみに薄膜を形成することが
できるので、MO8LSI  やバイポーラLSIの絶
縁分離に適用すれば受動、能動素子形成面積が小さくな
らないし、高歩留のLSIを得ることができる。また、
多層配線に適用した場合は微細で、歩留の高い導体配線
を形成することができる。
According to the present invention, it is possible to form a thin film only in a predetermined region, so if it is applied to the isolation of MO8LSI or bipolar LSI, the area for forming passive and active elements will not become small, and it is possible to obtain a high-yield LSI. can. Also,
When applied to multilayer wiring, it is possible to form fine conductor wiring with a high yield.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図A−Cは従来の絶縁分離の製造工程図、第2図は
従来の多層配線の断面図、第3図A−Eは本発明を絶縁
分離に適用した場合のMO8LSIの製造工程図、第4
図、第5図は本発明の絶縁物を形成する場合の装置の概
略構成図、第6図A〜Cは本発明を多層配線に適用した
場合の製造工程図である。 20・・・・0半導体基板、21・・・・・・反射膜、
23…・・・溝、28.43−・・・・・S i02膜
、p、、p、1・・・・拳・光、h・・・・・・熱。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図 2 第2図 /2 − 第3図 2 第3図 8 第4図 第6図 181−
Figures 1A-C are manufacturing process diagrams for conventional insulation isolation, Figure 2 is a cross-sectional view of a conventional multilayer wiring, and Figures 3A-E are manufacturing process diagrams for MO8LSI when the present invention is applied to insulation isolation. , 4th
5 are schematic configuration diagrams of an apparatus for forming an insulator according to the present invention, and FIGS. 6A to 6C are manufacturing process diagrams when the present invention is applied to multilayer wiring. 20...0 semiconductor substrate, 21... reflective film,
23...groove, 28.43-...S i02 film, p,, p, 1...fist/light, h...heat. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 2/2 - Figure 3 2 Figure 3 8 Figure 4 Figure 6 181-

Claims (4)

【特許請求の範囲】[Claims] (1)半導体基板表面上の所定の領域にエネルギー線を
反射する反射膜を形成する工程、前記半導体半導体基板
表面上に薄膜を形成する工程とを備えたことを特徴とす
る半導体装置の製造方法。
(1) A method for manufacturing a semiconductor device, comprising the steps of forming a reflective film that reflects energy rays in a predetermined region on the surface of a semiconductor substrate, and forming a thin film on the surface of the semiconductor substrate. .
(2)半導体基板表面上に光線を反射する反射膜を形成
する工程、所定の領域の前記反射膜を除去し、さらに所
定の深さまで前記半導体基板をエツチングして溝を形成
する工程、前記半導体基板を薄膜形成用ガスを含んだ雰
囲気中におき、前記基板表置の製造方法。
(2) a step of forming a reflective film that reflects light on the surface of the semiconductor substrate; a step of removing the reflective film in a predetermined region; and further etching the semiconductor substrate to a predetermined depth to form a groove; A manufacturing method for placing the substrate on top of the substrate, the substrate being placed in an atmosphere containing a thin film forming gas.
(3)薄膜が絶縁膜であることを特徴とする特許請求の
範囲第1項に記載の半導体装置の製造方法。
(3) The method for manufacturing a semiconductor device according to claim 1, wherein the thin film is an insulating film.
(4)反射膜が導体配線であることを特徴とする特許請
求の範囲第1項に記載の半導体装置の製造方法0
(4) Method 0 of manufacturing a semiconductor device according to claim 1, wherein the reflective film is a conductive wiring.
JP7933382A 1982-05-11 1982-05-11 Manufacture of semiconductor device Pending JPS58196036A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7933382A JPS58196036A (en) 1982-05-11 1982-05-11 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7933382A JPS58196036A (en) 1982-05-11 1982-05-11 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS58196036A true JPS58196036A (en) 1983-11-15

Family

ID=13686962

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7933382A Pending JPS58196036A (en) 1982-05-11 1982-05-11 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS58196036A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59119849A (en) * 1982-12-27 1984-07-11 Fujitsu Ltd Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59119849A (en) * 1982-12-27 1984-07-11 Fujitsu Ltd Manufacture of semiconductor device

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