JPS58195443U - semiconductor equipment - Google Patents

semiconductor equipment

Info

Publication number
JPS58195443U
JPS58195443U JP9502582U JP9502582U JPS58195443U JP S58195443 U JPS58195443 U JP S58195443U JP 9502582 U JP9502582 U JP 9502582U JP 9502582 U JP9502582 U JP 9502582U JP S58195443 U JPS58195443 U JP S58195443U
Authority
JP
Japan
Prior art keywords
semiconductor equipment
semiconductor
package
semiconductor device
recorded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9502582U
Other languages
Japanese (ja)
Inventor
坂根 英生
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP9502582U priority Critical patent/JPS58195443U/en
Publication of JPS58195443U publication Critical patent/JPS58195443U/en
Pending legal-status Critical Current

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  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の半導体装置を示す斜視図、第2図は第1
図の側面図、第3図はこの考案に係る半導体装置の一実
施例を示す側面図である。 図において、各図中同一部分もしくは相当部分には同一
符号もしくは同一符号にダッシュを付しており、図にお
いて、1′はパッケージ、101   ′は側面、2は
リード、3は蓋である。
Figure 1 is a perspective view of a conventional semiconductor device, and Figure 2 is a perspective view of a conventional semiconductor device.
FIG. 3 is a side view showing an embodiment of the semiconductor device according to the invention. In the figures, the same parts or equivalent parts in each figure are denoted by the same reference numerals or dashes. In the figures, 1' is a package, 101' is a side surface, 2 is a lead, and 3 is a lid.

Claims (2)

【実用新案登録請求の範囲】[Scope of utility model registration request] (1)半導体を封入し側面にテーパーが設けられたパッ
ケージ、及び前記半導体に接続され末広がりになるよう
前記パッケージの側面に沿って設けられたリードを備え
た半導体装置。
(1) A semiconductor device comprising a package enclosing a semiconductor and having a tapered side surface, and a lead connected to the semiconductor and provided along the side surface of the package so as to widen toward the end.
(2)パッケージはセラミックからなる実用新案登録請
求の範囲第(1)項記載の半導体装置。
(2) The semiconductor device according to claim (1), wherein the package is made of ceramic.
JP9502582U 1982-06-22 1982-06-22 semiconductor equipment Pending JPS58195443U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9502582U JPS58195443U (en) 1982-06-22 1982-06-22 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9502582U JPS58195443U (en) 1982-06-22 1982-06-22 semiconductor equipment

Publications (1)

Publication Number Publication Date
JPS58195443U true JPS58195443U (en) 1983-12-26

Family

ID=30227139

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9502582U Pending JPS58195443U (en) 1982-06-22 1982-06-22 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS58195443U (en)

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