JPS58195250A - デイジタル加算回路 - Google Patents
デイジタル加算回路Info
- Publication number
- JPS58195250A JPS58195250A JP57077066A JP7706682A JPS58195250A JP S58195250 A JPS58195250 A JP S58195250A JP 57077066 A JP57077066 A JP 57077066A JP 7706682 A JP7706682 A JP 7706682A JP S58195250 A JPS58195250 A JP S58195250A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output
- signal
- input
- adder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/504—Adding; Subtracting in bit-serial fashion, i.e. having a single digit-handling circuit treating all denominations after each other
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/499—Denomination or exception handling, e.g. rounding or overflow
- G06F7/49942—Significance control
- G06F7/49947—Rounding
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Pure & Applied Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- Mathematical Optimization (AREA)
- General Engineering & Computer Science (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57077066A JPS58195250A (ja) | 1982-05-08 | 1982-05-08 | デイジタル加算回路 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57077066A JPS58195250A (ja) | 1982-05-08 | 1982-05-08 | デイジタル加算回路 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58195250A true JPS58195250A (ja) | 1983-11-14 |
| JPH0418334B2 JPH0418334B2 (enExample) | 1992-03-27 |
Family
ID=13623416
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57077066A Granted JPS58195250A (ja) | 1982-05-08 | 1982-05-08 | デイジタル加算回路 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58195250A (enExample) |
-
1982
- 1982-05-08 JP JP57077066A patent/JPS58195250A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0418334B2 (enExample) | 1992-03-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0113391B1 (en) | Digital multiplier and method for adding partial products in a digital multiplier | |
| Patil et al. | Design of speed and power efficient multipliers using vedic mathematics with VLSI implementation | |
| US5070471A (en) | High speed multiplier which divides multiplying factor into parts and adds partial end products | |
| JPH10307706A (ja) | 半及び全加算器を用いたウォレスツリー乗算器 | |
| JP2668180B2 (ja) | 絶対値比較装置 | |
| JPS58195250A (ja) | デイジタル加算回路 | |
| JPH08221256A (ja) | 乗算器及び積和演算装置 | |
| JPH0744530A (ja) | 演算装置 | |
| US4588980A (en) | Residue to analog converter | |
| Shanthi et al. | Memory based hardware efficient implementation of FIR Filters | |
| Chren Jr | Low delay-power product CMOS design using one-hot residue coding | |
| US4584561A (en) | Method of residue to analog conversion | |
| Shanthi et al. | HIGH SPEED AND AREA EFFICIENT FPGA IMPLEMENTATION OF FIR FILTER USING DISTRIBUTED ARITHMETIC. | |
| US4584563A (en) | Method of residue to analog conversion | |
| JP3279462B2 (ja) | ディジタル乗算器、ディジタルトランスバーサル型等化器及びディジタル積和演算回路 | |
| JP2002111447A (ja) | ディジタルフィルタ | |
| US7003538B2 (en) | Process and apparatus for finite field multiplication (FFM) | |
| CN101258464A (zh) | 全加器模块和使用该全加器模块的乘法器装置 | |
| JP3531402B2 (ja) | 2乗回路 | |
| Lo et al. | A reusable distributed arithmetic architecture for FIR filtering | |
| JPH1141107A (ja) | デジタルデータの処理回路及びデジタルデータの処理方法 | |
| JP2838326B2 (ja) | ディジタル乗算器 | |
| US4584562A (en) | Method of residue to analog conversion | |
| JPS6045842A (ja) | 乗算回路 | |
| JPH0544047B2 (enExample) |