JPS58192356A - Manufacture of resin-sealed semiconductor device - Google Patents

Manufacture of resin-sealed semiconductor device

Info

Publication number
JPS58192356A
JPS58192356A JP57075340A JP7534082A JPS58192356A JP S58192356 A JPS58192356 A JP S58192356A JP 57075340 A JP57075340 A JP 57075340A JP 7534082 A JP7534082 A JP 7534082A JP S58192356 A JPS58192356 A JP S58192356A
Authority
JP
Japan
Prior art keywords
resin
lead
lead frame
leads
pellet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57075340A
Other languages
Japanese (ja)
Inventor
Tomio Yamada
富男 山田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57075340A priority Critical patent/JPS58192356A/en
Publication of JPS58192356A publication Critical patent/JPS58192356A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To reduce the cost of products, and to improve reliability by using a lead frame blank coated with Al. CONSTITUTION:A board material coated with Al 2 is prepared as the blank 1 for a lead frame. The lead frame is formed through processing, such as a punching press or photoetching or the like to the blank 1. A semiconductor pellet 9 is bonded on a tab, and wires 10 are thermocompression-bonded among each electrode of the upper surface of the pellet 9 and leads. The pellet and one parts of the leads are sealed with a surrounding resin molding 11. The Al of the surfaces of lead sections 7 exposed outside a resin is removed through etching while using the resin molding as a mask. The surfaces of outer leads from which Al is removed are coated with solder 12. Accordingly, the cost of materials can be economized and processes simplified. Wetproofing is improved because Al has excellent adhesive property with the resin.

Description

【発明の詳細な説明】 本発明は樹月′＃刺止形の半導体装置の製造法、特にリ
ードフレームを利用して半導体ペレットを組立てる方法
に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device of a pin-type type, and more particularly to a method of assembling semiconductor pellets using a lead frame.

バイポーラＩＣ等の半導体装置を側止体に組立てる（あ
たっては、例えばＣｕ（銅）、Ｆｅ（鉄）を主成分とす
る金属板材をプレス又はエツチング加工してタブ、タブ
リードを含む複数のリードを一体の枠体としたリードフ
レームにおいて、一部にＡｕ（金）やＡｇ（銀）をめっ
きし、このＡｇ等でめっきした部分く半導体ペレットを
グイボンディングするとともにベレットの電極とリード
のＡｕ部分との間を金属層ワイヤで接続する、いわゆる
ワイヤボンディングを行ない、その後樹脂モールドを行
なった後、樹脂で覆われないリード表面に錫めっき、半
田コーティング等の処理を行なうプロセスが採用されて
いる。Assemble a semiconductor device such as a bipolar IC to a side stopper (for example, by pressing or etching a metal plate whose main components are Cu (copper) and Fe (iron) to form multiple leads including tabs and tab leads). In a lead frame that is an integral frame, a part is plated with Au (gold) or Ag (silver), and a semiconductor pellet is bonded to the plated part with Ag, etc., and the electrode of the pellet and the Au part of the lead are bonded. A process is used in which so-called wire bonding is performed to connect the leads with a metal layer wire, followed by resin molding, followed by tin plating, solder coating, etc. on the lead surface that is not covered with resin.

しかし上記した在米法ではＡ　ｕ　’Ｐ　Ａ　ｇのごと
き貴金属を少なからず使用し、か、つ部分的にめっきす
る手間もあり、材料的にもコスト的にも価格が高くなる
のをさけられない。However, the above-mentioned US method uses a considerable amount of precious metals such as A u' P A g, and requires the labor of plating some parts, making it difficult to avoid high prices in terms of materials and costs. do not have.

本発明は上記した点を改良し、安いリードフレーム材を
使用し低価格の半導体装置を援供することにある。The object of the present invention is to improve the above-mentioned points, use cheap lead frame materials, and provide a low-cost semiconductor device.

以下本発明を実施例にもとすいて具体的に説明する。The present invention will be explained in detail below using examples.

第１　図（ａｔ〜（ｆｌは本発明によるバイポーラ１　
（？のの組立プロセスを示す工程図であろう （Ｊｉｌ　　リードフレーム用の素材１として片面又は
両面にＡ−Ｃ２を被着した板材を用意する。素材として
は例えばリン宵銅、鉄入り鋼又は４２アロイ４２Ｎｉ−
Ｆｅ合金）等を使用し、慝は１チＳｉ入りの局を素材１
の表面にａｍ、　　スパッタあるいは熱圧着して厚さ２
〜１５μｍの複膜２を形成する。FIG. 1 (at~(fl is bipolar 1 according to the present invention)
(This is a process diagram showing the assembly process of Jil. As the material 1 for the lead frame, a plate material coated with A-C2 on one or both sides is prepared. As the material, for example, phosphorescent copper, iron-filled steel, or 42 alloy 42Ni-
(Fe alloy), etc., and use one silicon-containing base as the material 1.
am, sputtering or thermocompression bonding to the surface of the
A composite film 2 of ~15 μm is formed.

（ｂ＋　）　（＋）ｔ）　　打抜きプレス又はホトエツ
チング等の加工を行なって前記板材か’）（ｂりに示す
ごときパターンのリードフレームを形成するう同図にお
いて、３はぺ・レット付は部となるタブ、４はタブ吊り
リード、５はインナーリード、６はダム、７はアウター
リード、８はフレームである。(b+) (+)t) Processing such as punching press or photo etching is performed to form a lead frame with the pattern shown in b. 4 is a tab suspension lead, 5 is an inner lead, 6 is a dam, 7 is an outer lead, and 8 is a frame.

（Ｃ１通常の組立工程に従つ℃タブ上に半導体ペレット
９をＡｇペースト等の接着剤を用いて接着し、半導体ペ
レット上面の各電極とリードとの間ＫＡＡ又はＡｕワイ
ヤ１０を熱圧着ポンディングする。(C1 Following the normal assembly process, adhere the semiconductor pellet 9 onto the °C tab using an adhesive such as Ag paste, and thermocompress and bond the KAA or Au wire 10 between each electrode and lead on the top surface of the semiconductor pellet. do.

（ｄｌ　　ペレットとリードの一部（インナーリード）
を包囲する樹脂モールド体１１により封止する。(dl Pellet and part of lead (inner lead)
It is sealed with a resin mold body 11 that surrounds it.

ｔｅｌ　　モールド後、樹脂モールド体をマスクとじて
樹脂外部に露出てるリード部（アウターリード）７の表
面のＡＪを薬品でエッチ除去する。このときのＡ２剥離
剤にはアルカリ系のエツチング剤、例えばＮａＱＨ等や
酸性のエツチング剤Ｈ（ニー８’？ＨｔｓＯｔ等を用い
ればよい。tel After molding, the AJ on the surface of the lead portion (outer lead) 7 exposed to the outside of the resin is removed by etching with a chemical by closing the resin mold body as a mask. As the A2 remover at this time, an alkaline etching agent such as NaQH or an acidic etching agent H (Ni8'?HtsOt) may be used.

げ）ＡＪを除去されたアウターリード表面を溶融した半
田又は錫等にディップするか又はめっき方法により半田
又は錫を被着する。この後、不必要なダム部を除去し全
てのリードが一方向にならぶようにアウターリードを折
り曲げてデュアルインライン形の樹脂刺止半導体装置を
完成する。(g) The surface of the outer lead from which AJ has been removed is dipped in molten solder or tin, or solder or tin is applied by plating. Thereafter, unnecessary dam portions are removed and the outer leads are bent so that all the leads are aligned in one direction, completing a dual in-line type resin-stitched semiconductor device.

以上実施例で述べた実発明によれば、Ａ４をリードフレ
ーム素材に被覆することによりＡｕ、　Ａｇめっきを使
用することなくインナーリードへのワイヤボンディング
が可能である。このよ２に高価なＡｕＪＰＡｇを使用し
な（てすむことから材料費の大幅な節減が可能である。According to the actual invention described in the embodiments above, by coating the lead frame material with A4, wire bonding to the inner lead is possible without using Au or Ag plating. Since this method does not require the use of the second most expensive AuJPAg, it is possible to significantly reduce material costs.

しかも、アウターリードに付着したＡＪは樹脂モールド
体をマスクと　　　　　（して選択的にエツチングでき
るから、特にマスク工程も不要で工程も簡素化される。Moreover, since the AJ attached to the outer lead can be selectively etched using the resin molded body as a mask, a masking process is not required and the process is simplified.

又ＩＩＩＩＲ脂モールド体内のリード部材表面にはＡＪ
かのこっており、このＡ４は一般に樹脂との密着性が良
好であるために樹脂とリードとの隙間からの水分の侵入
を防ぎ耐湿性が向上する。これらの点から半導体装置全
体として本発明によれば、製品価格の世減。Also, there is AJ on the surface of the lead member inside the IIIR resin mold body.
Since A4 generally has good adhesion to the resin, it prevents moisture from entering through the gap between the resin and the lead, improving moisture resistance. From these points, according to the present invention, the product price of the semiconductor device as a whole can be reduced.

信頼性の向上等の効果が期待できや。We can expect effects such as improved reliability.

本発明はＩＣＫ限らず、トランジスタのごとき単体にも
同様に応用できる。The present invention is applicable not only to ICKs but also to single devices such as transistors.

本発明は樹脂刺止形の半導体装置全般に通用できる。The present invention can be applied to all resin-filled semiconductor devices.

ドフレームへの組立プロセスを示す工程図であ−て、こ
のうち、（ａｌ　（ｂ、）　ｔｃｌ〜＋ｆｌは断面図、
（ｂりは（１）＋）Ｋ対応する平面図である。It is a process diagram showing the assembly process to the frame, in which (al (b,) tcl~+fl are cross-sectional views,
(b) is a plan view corresponding to (1)+)K.

第２図は組立完成後の半導体装置の斜面図である。FIG. 2 is a perspective view of the semiconductor device after assembly is completed.

１、・・・リードフレーム素材、２・・・Ａ−１３被膜
、３・・・タブ、４・・・タブリード、５・・・インナ
ーリード、６・・・ダム、７・・・アウターリード、８
・・・フレーム、９・・・半導体ペレット、１０・・・
ワイヤ、１１・・・樹脂モールド体、１２・・・半田。1. Lead frame material, 2... A-13 coating, 3... Tab, 4... Tab lead, 5... Inner lead, 6... Dam, 7... Outer lead, 8
...Frame, 9...Semiconductor pellet, 10...
Wire, 11...Resin mold body, 12...Solder.

代理人　弁理士　　薄　１）利　幸 第　　１　　図 第　２　図Agent Patent Attorney Usui 1) Toshiyuki Figure 1 Figure 2

Claims (1)

【特許請求の範囲】[Claims] １、金属板の片面又は全面にアルミニウム被膜を形成し
た板材を加工して複数のリードが一体となったリードフ
レームを形成する工程、複数のリードの関忙半導体ペレ
ットを接続する工程、半導体ペレットとリードの一部を
含み樹脂モールド体で刺止する工程、樹脂モールド体を
マスクとして露ダるリードの表面からアルミニウムをエ
ツチングにより除去した上に半田材をコーディングする
工程とから成ることを％像とする樹脂封止半導体装置の
製造法。1. Processing a metal plate with an aluminum coating formed on one side or the entire surface to form a lead frame in which multiple leads are integrated, a process of connecting semiconductor pellets of multiple leads, a process of connecting semiconductor pellets and The process consists of the process of pricking a part of the lead with a resin mold body, and the process of removing aluminum from the exposed surface of the lead using the resin mold body as a mask by etching, and then coating it with solder material. A method for manufacturing a resin-sealed semiconductor device.
JP57075340A 1982-05-07 1982-05-07 Manufacture of resin-sealed semiconductor device Pending JPS58192356A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57075340A JPS58192356A (en) 1982-05-07 1982-05-07 Manufacture of resin-sealed semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57075340A JPS58192356A (en) 1982-05-07 1982-05-07 Manufacture of resin-sealed semiconductor device

Publications (1)

Publication Number Publication Date
JPS58192356A true JPS58192356A (en) 1983-11-09

Family

ID=13573423

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57075340A Pending JPS58192356A (en) 1982-05-07 1982-05-07 Manufacture of resin-sealed semiconductor device

Country Status (1)

Country Link
JP (1) JPS58192356A (en)

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