JPS58192321A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS58192321A
JPS58192321A JP7590682A JP7590682A JPS58192321A JP S58192321 A JPS58192321 A JP S58192321A JP 7590682 A JP7590682 A JP 7590682A JP 7590682 A JP7590682 A JP 7590682A JP S58192321 A JPS58192321 A JP S58192321A
Authority
JP
Japan
Prior art keywords
layer
phosphorus
glass
heat treatment
diffusion layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7590682A
Other languages
Japanese (ja)
Inventor
Eiji Aramaki
英治 荒牧
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Kyushu Ltd
Original Assignee
NEC Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Kyushu Ltd filed Critical NEC Kyushu Ltd
Priority to JP7590682A priority Critical patent/JPS58192321A/en
Publication of JPS58192321A publication Critical patent/JPS58192321A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

Abstract

PURPOSE:To obtain the ohmic junction of Al wiring by preventing the phosphorus diffusion from the phosphorus glass between layers to a P-layer at the time of heat-treatment, by forming an oxide film on the P-diffused layer. CONSTITUTION:The P-layer 2 is provided on an Si substrate 1, a hole is bored by superposing an SiO2 film 3 and the phosphorus glass 4, then pure O2 is introduced at 900 deg.C, thus the SiO2 film 5 is formed rapidly and heated in N2, and accordingly the step parts of the glass 4 is smoothed. Further, it is covered with the phosphorus glass 6, and a hole is bored. Since the phosphorus density of the glass 6 is low, it is not necessary to form an SiO2 film 7 rapidly on the P-layer 2. Thereafter, heating in N2 slackens the step parts of the glass 6. By this constitution, the formation of an N-layer on the layer 2 due to phosphorus diffusion from the phosphorus glass 4 to the P-layer 2 can be prevented. Therefore, the Al wiring and ohmic junction formed on the P-layer can be realized.

Description

【発明の詳細な説明】 この発ｖ４！ｉ、牛導体装置の製造方法に関するもので
ある。[Detailed description of the invention] This release v4! i. This invention relates to a method for manufacturing a cow conductor device.

従来Ｐチャンネル電界効果半導体装置又は、相補型電界
効果半導体装置製造工程において、眉間リンガラス層成
長後、選択的に開孔を行う。この場合孔の周囲は急な段
になってお９、その１１の状態では、アルきを蒸着する
際、段部にアルミが均一に蒸着されない。これを防ぐた
めに、開孔後に加熱処理を行い、段部をだらしている。In the manufacturing process of a conventional P-channel field effect semiconductor device or a complementary field effect semiconductor device, holes are selectively formed after the glabellar glass layer is grown. In this case, the area around the hole has a steep step 9, and in the state 11, when alkali is deposited, aluminum is not uniformly deposited on the step. In order to prevent this, heat treatment is performed after the hole is opened to make the stepped portion loose.

加熱処理は、高温で行なわれるために、眉間リンガラス
層から、リンが、外拡散される。この時、Ｐ型拡散層は
、開孔されて露出しているので、Ｐ型拡散層に、リンが
拡散され、Ｐ型拡散層上にＮ型拡散層が出来、配線のア
ルミとオーミックコンタクトがとれなくなる欠点がちり
た〇 この発明の目的はｓＰ’ｔｉｌ拡散層と、配線アルミと
をオーン、り接合させる半導体製造工程を提供すること
にある。Since the heat treatment is performed at a high temperature, phosphorus is diffused out from the glabellar phosphorus glass layer. At this time, the P-type diffusion layer is opened and exposed, so phosphorus is diffused into the P-type diffusion layer, an N-type diffusion layer is formed on the P-type diffusion layer, and ohmic contact is made with the aluminum of the wiring. The object of the present invention is to provide a semiconductor manufacturing process in which the sP'til diffusion layer and the wiring aluminum are bonded to each other.

この発明の半導体装置の製造方法は、Ｐ型拡散層と層間
リンガラス層とを有し、Ｐ型拡散層上のリンガラス層に
選択的開孔を行い、不活性ガスによる加熱処理を含む製
造工程において、加熱処理工程前に、あるいは、及び、
加熱処理工程前期に、このＰ型拡散層を酸化膜により被
覆することを特徴とすることにある。The method for manufacturing a semiconductor device of the present invention includes a P-type diffusion layer and an interlayer phosphor glass layer, selectively opening holes in the phosphor glass layer on the P-type diffusion layer, and manufacturing including heat treatment with an inert gas. In the step, before the heat treatment step, or,
The present invention is characterized in that the P-type diffusion layer is covered with an oxide film in the first half of the heat treatment process.

この発明の半導体装置の製造方法は、Ｐ型拡散層上に酸
化膜を形成することにより、加熱処理時に、眉間リンガ
ラス層より外拡散されるり／のＰ型拡散層への拡散を防
ぐので、Ｐ型拡散層と、配線アルｉとのオーミ、り接合
ができる。In the method for manufacturing a semiconductor device of the present invention, by forming an oxide film on the P-type diffusion layer, during heat treatment, diffusion from the glabellar glass layer to/from the glabellar glass layer is prevented from diffusing into the P-type diffusion layer. An ohmic junction can be made between the P-type diffusion layer and the aluminum wiring.

次にこの発明の実施例につき１図を用いて説明する。第
１図（ａ）に示すように、半導体基板１の表面に、選択
的にＰ散拡散層２を形成し、酸化膜３、第１の層間リン
ガラス層４を形成する。酸化膜３と眉間リンガラス層と
には、第１の選択的開孔を行う。次に、加熱処理を行う
が、第１の眉間リンガラス層４のリンの濃度は高く、外
拡散もはげしいので、第１図（ｂ）に示すように酸化膜
５を早く形成する必要がある。酸化膜５を成長するには
、第１の方法として、　　１０００℃で加熱処理を行う
加熱処理装置内にウェハースを導入する前に、酸化膜が
形成される割合よりも、層間り／ガラ１層からリンが外
拡散される割合が小さい９００℃程度の低温に加熱処理
装置内の温度を下げてウエノ・−スを導入する方法。第
２の方法として、不活性ガスと酸素との混合気体、また
は、純粋な酸素を導入しながらウェハースを加熱処理装
置に導入する方法。第３の方法として、第１の方法と、
第２の方法を組み合わせて行う方法がある。Next, an embodiment of the present invention will be explained using one drawing. As shown in FIG. 1(a), a P diffusion layer 2 is selectively formed on the surface of a semiconductor substrate 1, and an oxide film 3 and a first interlayer phosphorus glass layer 4 are formed. A first selective opening is performed in the oxide film 3 and the glabellar glass layer. Next, heat treatment is performed, but since the concentration of phosphorus in the first glabellar phosphorus glass layer 4 is high and the outward diffusion is rapid, it is necessary to quickly form the oxide film 5 as shown in FIG. 1(b). . In order to grow the oxide film 5, as a first method, before introducing the wafer into a heat treatment equipment that performs heat treatment at 1000 ° C., it is necessary to A method in which the temperature inside the heat treatment equipment is lowered to a low temperature of about 900°C, at which the rate of phosphorus being diffused out is small, and then the urethane is introduced. The second method is to introduce the wafer into a heat treatment apparatus while introducing a mixture of an inert gas and oxygen or pure oxygen. As a third method, the first method and
There is a method that combines the second method.

この実権例の場合は第１図（ｂ）の酸化膜５を早く形成
させる必要があるので第３の方法を用いて、加熱処理装
置の温度を９００℃にして、純粋な酸素を加熱処理装置
に導入しながら、ウェハースを加熱処理装置に導入する
。すると第１図（ｂ）に示す如く酸化膜５が形成され、
その後窒素ガス中で、第１の加熱処理を行うと、第１図
（Ｃ）に示す如く第１のリンガラス層４′の段部がだれ
る。さらに、第１図（ｄ）に示す如く第２の層間リンガ
ラス層６を形成し、第２の選択的開孔を行う。第２の層
間リンガラス層６のリンの濃度は低いのでＰ型拡散層２
上に早く酸化膜を形成する必要はない、そこで第２の方
法を用いて、加熱処理装置に、窒素２１　　　　　［２
７分、酸素１．４ｔ／分の混合気体と窒素２１４／分、
酸素１．０５ｔ／分の混合気体との２水準の気体をそれ
ぞれ加熱処理装置に導入しながら、それぞれの加熱処理
装置にウエノ・−スを導入する。In this practical example, it is necessary to quickly form the oxide film 5 shown in FIG. The wafer is introduced into the heat treatment equipment while being introduced into the heat treatment equipment. Then, as shown in FIG. 1(b), an oxide film 5 is formed.
Thereafter, when a first heat treatment is performed in nitrogen gas, the stepped portion of the first phosphor glass layer 4' sag as shown in FIG. 1(C). Furthermore, as shown in FIG. 1(d), a second interlayer phosphor glass layer 6 is formed and a second selective opening is performed. Since the concentration of phosphorus in the second interlayer phosphorus glass layer 6 is low, the P-type diffusion layer 2
There is no need to quickly form an oxide film on the top, so using the second method, nitrogen 21 [2
7 minutes, mixed gas of oxygen 1.4t/min and nitrogen 214/min,
Uenose was introduced into each heat treatment device while introducing two levels of gases including a mixed gas of oxygen at 1.05 t/min into each heat treatment device.

すると、第１図（ｅ）に示す如く、酸化膜７が形成され
、その後窒素ガス中で第２の加熱処理を行うと第１図（
ｔ）に示す如く第２の層間リンガラス層６′の段部がだ
れる。As a result, an oxide film 7 is formed as shown in FIG.
As shown in t), the stepped portion of the second interlayer phosphor glass layer 6' sag.

この実施例によれば第１の加熱処理前に、第１図φ）の
酸化膜５を形成することにより、第１の層間リンガラス
層４より外拡散されるＮＪ不純物であるリンがＰ散拡散
層２に拡散されるのを防ぐことができる。また、第２の
加熱処理前に、第１図（ｅ）の酸化Ｊｌｌ［７を形成す
ることにより、第２の層間リンガラス層６より外拡散さ
れるＮ型不純物でおるリンが、Ｐ散拡散層２に拡散され
るのを防ぐことができる。これによって、Ｐ型拡散層と
、後に形成する配線アルミとをオーミ、り接合すること
ができ、次の表に示すように１枚のつ、）１−スあAccording to this embodiment, by forming the oxide film 5 shown in FIG. Diffusion into the diffusion layer 2 can be prevented. In addition, by forming the oxidized Jll [7] shown in FIG. 1(e) before the second heat treatment, the phosphorus, which is an N-type impurity diffused out from the second interlayer phosphorus glass layer 6, is Diffusion into the diffusion layer 2 can be prevented. As a result, the P-type diffusion layer and the wiring aluminum to be formed later can be ohm-jointed, and as shown in the table below, one

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の実施例を示す断面図である０尚図にお
いて、１は半導体基板、２はＰＭ拡散層、３は酸化膜、
４．４’は第１の層間リンガラス、５は酸化膜、６．６
’は第２の層間リンガラス、７は酸化膜であるＯ 猟　７　回 η　　１　（２） ｉ。 ＝１０３FIG. 1 is a cross-sectional view showing an embodiment of the present invention. In the figure, 1 is a semiconductor substrate, 2 is a PM diffusion layer, 3 is an oxide film,
4.4' is the first interlayer phosphor glass, 5 is the oxide film, 6.6
' is the second interlayer phosphor glass, and 7 is the oxide film. =103

Claims (1)

【特許請求の範囲】[Claims] Ｐ１１拡散層と層間リンガラス層とを有し、該Ｐ漏拡散
層上の該層間リンガラス層に選択的開孔を行い、不活性
ガスによる加熱処理を含む製造工程において、前記加熱
処理工程前に、あるいは、前記加熱処理工程前期に、Ｐ
型拡散層上の開孔部を酸化膜により被覆することを特徴
とする半導体装置、の製造方法。In a manufacturing process that includes a P11 diffusion layer and an interlayer phosphorus glass layer, selectively opening holes in the interlayer phosphorus glass layer on the P leakage diffusion layer, and including heat treatment with an inert gas, before the heat treatment step. Alternatively, in the first half of the heat treatment step, P
A method for manufacturing a semiconductor device, characterized in that an opening on a type diffusion layer is covered with an oxide film.
JP7590682A 1982-05-06 1982-05-06 Manufacture of semiconductor device Pending JPS58192321A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7590682A JPS58192321A (en) 1982-05-06 1982-05-06 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7590682A JPS58192321A (en) 1982-05-06 1982-05-06 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS58192321A true JPS58192321A (en) 1983-11-09

Family

ID=13589839

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7590682A Pending JPS58192321A (en) 1982-05-06 1982-05-06 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS58192321A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53105385A (en) * 1977-02-25 1978-09-13 Fujitsu Ltd Manufacture for semiconductor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53105385A (en) * 1977-02-25 1978-09-13 Fujitsu Ltd Manufacture for semiconductor

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