JPS61174197A - Production of epitaxial wafer - Google Patents

Production of epitaxial wafer

Info

Publication number
JPS61174197A
JPS61174197A JP1197285A JP1197285A JPS61174197A JP S61174197 A JPS61174197 A JP S61174197A JP 1197285 A JP1197285 A JP 1197285A JP 1197285 A JP1197285 A JP 1197285A JP S61174197 A JPS61174197 A JP S61174197A
Authority
JP
Japan
Prior art keywords
substrate
impurities
forming
oxide
diffusion layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1197285A
Other languages
Japanese (ja)
Other versions
JPH0456800B2 (en
Inventor
Norihei Takai
高井 法平
Shoichi Takahashi
高橋 捷一
Kunihiko Fushii
伏井 邦彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Coorstek KK
Original Assignee
Toshiba Ceramics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Ceramics Co Ltd filed Critical Toshiba Ceramics Co Ltd
Priority to JP1197285A priority Critical patent/JPS61174197A/en
Publication of JPS61174197A publication Critical patent/JPS61174197A/en
Publication of JPH0456800B2 publication Critical patent/JPH0456800B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE:To control easily the concn. of impurities and to prevent the contamination of the device forming region by forming the diffusion layer of the same impurities as the impurities contained in an Si substrate, forming an oxide- coated film after specified treatment, polishing the one surface, and then forming an epitaxial layer having the same electric conductivity as the Si substrate. CONSTITUTION:Intrinsic gettering is applied to an Si substrate 1 of usual impurity content produced by the CZ method to form an oxide depositing neucleus 2 at the inside of the substrate 1. After the same impurities as the contained impurities are diffused at the surface and in the vicinity of the surface of the substrate 1 to form a diffusion layer 3, an oxide coated film (SiO2) 4 is formed on the surface of the substrate 1 by oxidation or the rear surface CVD method. The one surface is subsequently mirror-polished to remove the oxide film 4. An epitaxial layer 5 having the same electric conductivity as the substrate 1 having high resistivity is formed on the polished surface by the reduction with hydrogen or thermal decomposition, and the desired epitaxial wafer is produced.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、ダイナミックRANや0MO8等の−高密度
デバイスの製造に用いられるエピタキシヤル・ウェーハ
の製造り法に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing epitaxial wafers used in the manufacture of high-density devices such as dynamic RAN and OMO8.

[従来の技術] 従来、エピタキシャル・ウェーハは、デバイスの直列抵
抗を低下させるため、CZ法(チョクラルスキー法)に
よる高不純物濃度(ホウ素、燐、アンチモン等のドープ
により不純物濃度10〜1019個/cd’)のSin
板を用い、このSi基板の片面を鏡面研磨した後、Si
基板の表面に酸化法またはCVD法によりオートドープ
防止用の酸化被膜を形成するとともに、鏡面側の酸化被
膜を剥離し、しかる後鏡面にSi基板と同−S電形にし
てかつ比抵抗の高いエピタキシャル層を形成する方法に
よって製造されている。
[Prior Art] Conventionally, epitaxial wafers have been manufactured using a CZ method (Czochralski method) to reduce the impurity concentration by doping boron, phosphorus, antimony, etc. in order to reduce the series resistance of devices. cd') Sin
After mirror polishing one side of this Si substrate using a plate,
An oxide film for autodoping prevention is formed on the surface of the substrate by an oxidation method or a CVD method, and the oxide film on the mirror surface side is peeled off. After that, the mirror surface is made into the same -S electric type as the Si substrate and has a high specific resistance. It is manufactured by a method of forming an epitaxial layer.

[発明が解決しようとする問題点] しかし、上記従来の製造方法によれば、結晶引上げの段
階から不純物濃度の制御を行わなければならないととも
に、基板との濃度外大なことによりエピタキシャル層界
面での格子不整の問題が生じ、またかかる方法によって
!lJ造されたエピタキシャル・ウェーハをデバイス製
造プロセスに投入した際、ゲッタ効果を有さないため、
製造プロセス中で重金属等によって汚染される等の問題
がある。
[Problems to be Solved by the Invention] However, according to the above-mentioned conventional manufacturing method, the impurity concentration must be controlled from the stage of crystal pulling, and the concentration of impurities with the substrate is too large to cause problems at the interface of the epitaxial layer. The problem of lattice misalignment arises, and also by such a method! When the LJ fabricated epitaxial wafer is introduced into the device manufacturing process, it does not have a getter effect, so
There are problems such as contamination with heavy metals during the manufacturing process.

[問題点を解決するための手段] 本発明は、上記問題点を解決するため、CZ法による通
常の不純物濃度(1014〜1016個/i)のSi基
板にその含有不純物と同一の不純物を拡散して拡散層を
形成する前あるいは後にイントリンシック・ゲッタリン
グ処理を施し、前記Si基板の表面に酸化被膜を形成す
るとともに、その片面の酸化被膜を鏡面研磨して除去し
た後、前記研旧面に81基板と同一導電形のエピタキシ
ャル層を形成するものである。
[Means for Solving the Problems] In order to solve the above problems, the present invention diffuses the same impurities as the impurities contained in the Si substrate with the usual impurity concentration (1014 to 1016 pieces/i) by the CZ method. Before or after forming the diffusion layer, an intrinsic gettering process is performed to form an oxide film on the surface of the Si substrate, and after removing the oxide film on one side by mirror polishing, the polished surface is Then, an epitaxial layer of the same conductivity type as the 81 substrate is formed.

[作 用] 通常の不純物濃度のSi基板にその含有不純物と同一の
不純物の拡散層が形成されるとことにより、Si基板の
表面近傍に比抵抗の十分低い層が形成される。また、イ
ントリンシック・ゲッタリング処理により、Si基板中
の表面と裏面の拡散層間に酸素析出核が形成されるとと
もに、このエピタキシャル・ウェーハをデバイス製造プ
ロセスに投入することにより、内部の酸素析出核が汚染
不純物をゲッタする微小欠陥へ成長する。
[Function] By forming a diffusion layer of the same impurity as the impurity contained in the Si substrate with a normal impurity concentration, a layer with sufficiently low resistivity is formed near the surface of the Si substrate. In addition, due to the intrinsic gettering process, oxygen precipitate nuclei are formed between the diffusion layers on the front and back surfaces of the Si substrate, and by introducing this epitaxial wafer into the device manufacturing process, the internal oxygen precipitate nuclei are removed. It grows into microscopic defects that getter contaminant impurities.

[実施例] 以下、本発明の実施例を図面を参照して説明する。[Example] Embodiments of the present invention will be described below with reference to the drawings.

第1図a、b、c、d、e、fは本発明の第1実施例を
示す工程図で、この実施例によりエピタキシャル・ウェ
ーハを製造するには、CZ法によって製造された通常の
不純物濃度(10”〜1016個/CI!>(F)Si
基板1を用い(第1図C参照)、このSi基板1にイン
トリンシック・ゲッタリング処理を施し、Si基板1の
内部に酸素析出核2を形成する(第1図す参照)。この
とき、適度なイントリンシック・ゲッタリング効果を得
るためのSi基板1は、含有酸素濃度が1.0×101
8個/i(赤外分光計吸収係数をαとした場合、αx 
3.Ox 1017の換口濃度)以上であることが必要
である。
Figures 1a, b, c, d, e, and f are process diagrams showing the first embodiment of the present invention. Concentration (10”~1016 pieces/CI!>(F)Si
Using the substrate 1 (see FIG. 1C), the Si substrate 1 is subjected to an intrinsic gettering process to form oxygen precipitation nuclei 2 inside the Si substrate 1 (see FIG. 1C). At this time, in order to obtain a suitable intrinsic gettering effect, the Si substrate 1 has an oxygen concentration of 1.0×101
8 pieces/i (If the infrared spectrometer absorption coefficient is α, αx
3. Ox 1017 exchange concentration) or higher.

ついで、Si基板1の表面および表面近傍に、このSi
基板1に含有される不純物と同一の不純物を拡散して拡
散層3を形成する(第1図C参照)。この拡散層3の形
成により、Si基板1の表面およびその近傍は、高不純
物濃度(1018〜1019個/ ci )のSi基板
と同程度の導電率となる。
Next, this Si is deposited on and near the surface of the Si substrate 1.
A diffusion layer 3 is formed by diffusing the same impurity as that contained in the substrate 1 (see FIG. 1C). Due to the formation of this diffusion layer 3, the surface of the Si substrate 1 and its vicinity have a conductivity comparable to that of a Si substrate with a high impurity concentration (1018 to 1019 impurities/ci).

拡散層3の形成後、後述するエピタキシャル層形成時、
背面(図において下面)からのオートドーピング現象を
抑制するため、Si基板1の表面に酸化液1!(Si0
2)4を酸化法または裏面CVD法により形成する(第
1図C参照)。その後その片面(図において上面)の酸
化皮膜あるいは裏面CVD時の表面まわり込み突起物や
残滓4を鏡面研磨して除去する(第1図C参照)。
After forming the diffusion layer 3, when forming an epitaxial layer, which will be described later,
In order to suppress the autodoping phenomenon from the back side (lower side in the figure), an oxidizing solution 1! is applied to the surface of the Si substrate 1! (Si0
2) 4 is formed by an oxidation method or a backside CVD method (see FIG. 1C). Thereafter, the oxide film on one side (the upper side in the figure) or the protrusions and residues 4 surrounding the surface during CVD on the back side are removed by mirror polishing (see FIG. 1C).

そして、Si基板1の研磨面に、この81基板1と同一
導電形にしてかつ高い比抵抗をもつエピタキシャル層5
を、水素還元法や熱分解法等により形成する(第1図C
参照)と、所望のエピタキシャル・ウェーハが完成する
Then, on the polished surface of the Si substrate 1, an epitaxial layer 5 having the same conductivity type as the 81 substrate 1 and having a high resistivity is formed.
is formed by a hydrogen reduction method, a thermal decomposition method, etc. (Fig. 1C)
), the desired epitaxial wafer is completed.

第2図a、b、c、d、eは本発明の第2実施例を示す
工程図で、この実施例によりエピタキシ?/L/・ウェ
ーハを製造するには、前述した第1実施例の場合と同様
に、CZ法によって製造された通常の不純物濃度のSi
基板1を用い(第2図C参照)、このSi基板1の表面
および表面近傍に、Si基板1に含有される不純物と同
一の不純物を拡散して拡散層3を形成する(第2図す参
照)。
Figures 2a, b, c, d, and e are process diagrams showing a second embodiment of the present invention. /L/. In order to manufacture a wafer, as in the case of the first embodiment described above, Si with a normal impurity concentration manufactured by the CZ method is used.
Using a substrate 1 (see FIG. 2C), a diffusion layer 3 is formed by diffusing the same impurity as that contained in the Si substrate 1 on and near the surface of the Si substrate 1 (see FIG. 2C). reference).

この拡散WJ3の形成により、81基板1の表面および
その近傍は、従来の高不純物5ttxtのSi基板と同
程度の導電率となる。
Due to the formation of this diffusion WJ3, the surface of the 81 substrate 1 and its vicinity have a conductivity comparable to that of a conventional Si substrate with high impurity levels of 5ttxt.

ついで、Si基板1にイントリンシック・ゲッタリング
処理を施してSi基板1の内部に酸素析出核2を形成す
るとともに、Si基板1の表面にオートドーピング現象
抑制用の酸素被膜(Si 02)4を形成する(第2図
C参照)。
Next, the Si substrate 1 is subjected to an intrinsic gettering process to form oxygen precipitation nuclei 2 inside the Si substrate 1, and an oxygen film (Si02) 4 is formed on the surface of the Si substrate 1 to suppress the autodoping phenomenon. form (see Figure 2C).

そして、Si基板1の片面の酸化被膜あるいは裏面CV
D時の表面まわり込み突起物や残滓4を鏡面研磨して除
去した(第2図C参照)後、この研磨面に、Si基板1
と同一導電形にしてかつ高い比抵抗をもつエピタキシャ
ルH5を水素還元法等により形成する(第2図C参照)
と、所望のエピタキシャル・ウェーハが完成する。
Then, the oxide film on one side of the Si substrate 1 or the CV on the back side
After mirror-polishing and removing the protrusions and residue 4 that went around the surface in D (see Figure 2C), the Si substrate 1 was placed on this polished surface.
Epitaxial H5 having the same conductivity type and high resistivity is formed by hydrogen reduction method etc. (see Figure 2C).
The desired epitaxial wafer is then completed.

なお、各実施例におけるイントリンシック・ゲッタリン
グ処理は、エピタキシャル・ウェーハを用いて製造され
るデバイスの種類に応じて、低温熱処理(窒素ガス中に
おいて500〜900℃の温度で4・〜32時間加熱)
により酸素析出核2を形成する場合、または低温熱処理
(500〜900℃)による酸素析出核2の形成後、高
温熱処理(窒素ガス中において1000〜1100℃の
温度で数時間加熱)により酸素析出核2をある程度微小
欠陥に成長させる場合かのいづれかの方法がとられる。
Note that the intrinsic gettering treatment in each example includes low-temperature heat treatment (heating in nitrogen gas at a temperature of 500 to 900°C for 4 to 32 hours) depending on the type of device manufactured using the epitaxial wafer. )
or after forming oxygen precipitate nuclei 2 by low-temperature heat treatment (500 to 900°C), high-temperature heat treatment (heating at a temperature of 1000 to 1100°C in nitrogen gas for several hours) Either of the following methods can be used to grow 2 to some extent into minute defects.

本発明における重要なポイントであるイントリンシック
・ゲッタリング処理での高温での酸素の外方拡散処理は
、通常濃度基板に拡散層3を形成する工程をもって代替
可能であることが判っている。すなわち、本発明におけ
る拡散層形成工程(ホウ素、燐、アンチモン等を110
0〜1250℃の温度で拡散し、10〜20μmの拡散
層を形成する工程)は、基板表面近傍の酸素を外方拡散
するに十分な条件であり、また、実験でも拡散層中には
微小欠陥は全く発生しないことを確かめている。
It has been found that the out-diffusion treatment of oxygen at a high temperature in the intrinsic gettering treatment, which is an important point in the present invention, can be replaced by a process of forming the diffusion layer 3 on a normal concentration substrate. That is, in the diffusion layer forming step of the present invention (boron, phosphorus, antimony, etc.
The process of diffusing at a temperature of 0 to 1250°C to form a diffusion layer of 10 to 20 μm is a sufficient condition to outwardly diffuse oxygen near the substrate surface. We have confirmed that no defects occur.

また、イントリンシック・ゲッタリング処理によって形
成された酸素析出核2は、デバイス製造プロセス中にお
いて微小欠陥に成長するとともに製造プロセス中に混入
する重金属等の汚染物をゲッタするものであり、かつ微
小欠陥の外周辺には無欠陥層が形成されるものである。
In addition, the oxygen precipitation nuclei 2 formed by the intrinsic gettering process grow into micro defects during the device manufacturing process, and also getter contaminants such as heavy metals mixed in during the manufacturing process. A defect-free layer is formed around the outer periphery of the layer.

[発明の効果] 以上のように本発明によれば、従来技術に比し以下に述
べる種々の効果が得られる。
[Effects of the Invention] As described above, according to the present invention, various effects described below can be obtained compared to the conventional technology.

(1)通常の不純物濃度のSi基板を用いることができ
、単結晶育成時の不純物の濃度制御を容易に行うことが
できる。
(1) A Si substrate with a normal impurity concentration can be used, and the impurity concentration can be easily controlled during single crystal growth.

(2)デバイス製造プロセス中における重金属等による
汚染をエピタキシャル・ウェーハ自身でゲッタすること
ができ、デバイス形成領域の汚染を防止することができ
る。
(2) Contamination caused by heavy metals and the like during the device manufacturing process can be gettered on the epitaxial wafer itself, and contamination of the device formation region can be prevented.

(3)デバイスのラッチアップを防止できるとともに、
キャリアの不要な拡散によるデバイスの誤動作等を改善
することができる。
(3) Device latch-up can be prevented, and
Device malfunctions caused by unnecessary diffusion of carriers can be improved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図a、b、c、d、e、fおよび第2図a、b、c
、d、eはそれぞれ本発明の第1実施例および第2実施
例を示づ工程図である。 1・・・Si基板     2・・・酸素析出核3・・
・拡散層      4・・・酸イじ被膜5・・・エピ
タキシャル層 発  明  者      高  井   法  平発
  明  者       高  m    捷  −
−発  明  者      伏  井   邦  産
出 願 人  東芝セラミックス株式会社第1図   
  第2図
Figure 1 a, b, c, d, e, f and Figure 2 a, b, c
, d and e are process diagrams showing a first embodiment and a second embodiment of the present invention, respectively. 1...Si substrate 2...Oxygen precipitation nucleus 3...
・Diffusion layer 4...Acidic coating 5...Epitaxial layer Inventor: Norihiro Takai Inventor: Takashi M. -
-Inventor: Kuni Fushii Producer: Toshiba Ceramics Corporation Figure 1
Figure 2

Claims (1)

【特許請求の範囲】[Claims] CZ法による通常の不純物濃度のSi基板にその含有不
純物と同一の不純物を拡散して拡散層を形成する前ある
いは後にイントリンシック・ゲッタリング処理を施し、
前記Si基板の表面に酸化被膜を形成するとともに、そ
の片面の酸化被膜を鏡面研磨して除去した後、前記研磨
面にSi基板と同一導電形のエピタキシャル層を形成す
ることを特徴とするエピタキシャル・ウェーハの製造方
法。
Intrinsic gettering treatment is performed before or after forming a diffusion layer by diffusing the same impurity as the impurity contained in the Si substrate with a normal impurity concentration by the CZ method,
An epitaxial method characterized by forming an oxide film on the surface of the Si substrate, removing the oxide film on one side by mirror polishing, and then forming an epitaxial layer having the same conductivity type as the Si substrate on the polished surface. Wafer manufacturing method.
JP1197285A 1985-01-25 1985-01-25 Production of epitaxial wafer Granted JPS61174197A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1197285A JPS61174197A (en) 1985-01-25 1985-01-25 Production of epitaxial wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1197285A JPS61174197A (en) 1985-01-25 1985-01-25 Production of epitaxial wafer

Publications (2)

Publication Number Publication Date
JPS61174197A true JPS61174197A (en) 1986-08-05
JPH0456800B2 JPH0456800B2 (en) 1992-09-09

Family

ID=11792520

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1197285A Granted JPS61174197A (en) 1985-01-25 1985-01-25 Production of epitaxial wafer

Country Status (1)

Country Link
JP (1) JPS61174197A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005175251A (en) * 2003-12-12 2005-06-30 Matsushita Electric Ind Co Ltd Semiconductor wafer and manufacturing method thereof
KR100790725B1 (en) 2006-12-20 2008-01-02 동부일렉트로닉스 주식회사 A method for fabricating a semiconductor

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5162974A (en) * 1974-11-29 1976-05-31 Matsushita Electronics Corp Handotaisochino seizohoho
JPS51145268A (en) * 1975-06-10 1976-12-14 Nec Home Electronics Ltd Epitaxial semiconductor device
JPS56167335A (en) * 1980-05-29 1981-12-23 Nec Corp Manufacture of semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5162974A (en) * 1974-11-29 1976-05-31 Matsushita Electronics Corp Handotaisochino seizohoho
JPS51145268A (en) * 1975-06-10 1976-12-14 Nec Home Electronics Ltd Epitaxial semiconductor device
JPS56167335A (en) * 1980-05-29 1981-12-23 Nec Corp Manufacture of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005175251A (en) * 2003-12-12 2005-06-30 Matsushita Electric Ind Co Ltd Semiconductor wafer and manufacturing method thereof
KR100790725B1 (en) 2006-12-20 2008-01-02 동부일렉트로닉스 주식회사 A method for fabricating a semiconductor

Also Published As

Publication number Publication date
JPH0456800B2 (en) 1992-09-09

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