JPS58190059A - Manufacture of mos type semiconductor device - Google Patents

Abstract

PURPOSE:To enable to previously prevent the phenomenon of abnormal decrease in threshold voltage and thus enable to attain the threshold voltage as the designed value with good controllability, by forming a source-drain region consisting of a two stage impurity region. CONSTITUTION:A B contained P type Si substrate 1 is prepared, then the element forming region of the substrate is covered with a mask 2, and the field region of the Si substrate 1 is etched. An inversion prevention layer 3 is formed by ion implantation of B, and a Si oxide film 4 is buried in the field region. A fluid film 8 which is fluid and becomes equal to a CVDSiO2 film 6 in etching speed is formed, then a recess 7 is bruied, and its surface is flatted. At the time of forming the source-drain by ion implantation, first and acceleration voltage is set at 50kV at a low dosage 3X10<14>/cm<3>, and then As is ion-implanted into the source-drain formng region. Ion implantation is performed by using a mask and a high accuracy aligner which go inside from the W direction respectively by 0.6mum from both sides.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides f
J! ! Regarding improvement of delivery method.

[Technical background of the invention and its problems]

Various device isolation technologies using oxide films have been devised, but
Among them, the BOX method (B
uryingOxide 1nto 5ilicon
GrOOVe, Kurosawa 1% Gansho No. 56-88257). This BOX method will be briefly explained. First, Si is etched in other regions (field regions) of the silicon substrate, leaving only the element formation region. An insulating oxide film (Si02) is placed in this etched and lowered recess.
to the same height as the silicon surface of the buried element forming area. Elements can thus be formed in the insulated and isolated silicon element region through normal steps. As mentioned in section -F, the advantages of this BOX method are flattening of the device plane and drastic reduction of bird's beak, and it is a revolutionary new technology that is extremely useful for increasing the integration of devices.

However, the device created by the above BOX method has
Several additional problems have since arisen. for example,
Channel @W of MOS transistor is 3.0 (μm)
When it comes to a shorter region around 20 [μm],
A phenomenon has been discovered in which the threshold voltage (VT) is lower than the designed value. This phenomenon has a major impact on the reliability of devices in the fields of process and design, and must be avoided. As a countermeasure against this problem, a method is currently used in which N-channel MO8 devices include a large amount of impurity poron only in the vicinity of the side surfaces in the direction of the channel width W. Specifically, the current practice is to use ion implantation technology and take advantage of the spread of impurity ions into the device region during lateral force during implantation.

However, with this method of ion implantation,
Because ion implantation does not utilize impurity implantation in the original depth direction, but instead utilizes the resulting lateral spread, the effect is small and its control is extremely difficult.

For this reason, when manufacturing an MO8 type semiconductor device with a short channel width (3) 1 m or less), it has been difficult to adjust the threshold voltage to a designed value with good controllability.

[Purpose of the invention]

An object of the present invention is to prevent the phenomenon of an abnormal drop in threshold voltage when manufacturing an MO8 type semiconductor device using the BOX method, and to maintain the threshold voltage as designed with good controllability. M that can achieve high voltage and has a simple process
An object of the present invention is to provide a method for manufacturing an O8 type semiconductor device.

[Summary of the invention]

When manufacturing an MO8 type semiconductor device, the present invention involves forming a film on an element formation region of a semiconductor substrate, selectively etching the film using the film as a mask, forming a recess in a field region of the substrate, and then at least the bottom of the recess. An impurity having the same conductivity type as the substrate is ion-implanted into the substrate, a first insulating film is buried in the recess with a groove formed around the periphery, and a second insulating film is deposited to fill the groove. Then, the entire surface is etched to form the first and second parts on the four parts.
The element formation region of the substrate is exposed with the insulating film buried therein, and then impurities that form a conductivity type opposite to that of the substrate are ion-implanted into the source/drain formation regions of the exposed element formation region.・Ion implantation of an impurity that creates a conductivity type opposite to that of the substrate into the source/drain formation region except for both sides in the width direction at a dose that is at least one order of magnitude higher than the dose of the impurity ion-implanted into the drain formation region. This is how I did it.

In other words, the gist of the present invention is to achieve device isolation using the BoX method, and then continue the device fabrication process by performing the source/source process.
In the ion implantation process for forming the drain region, a predetermined source and drain region is first formed at a low dose, and then a dose at least one order of magnitude higher than this dose is implanted in the width direction of the source and drain regions. The purpose is to implant ions again into regions separated by about 0.25 to 0.3 [μm] from both sides.

〔Effect of the invention〕

According to the present invention, by forming the source/drain regions consisting of two stages of impurity regions, in particular, the channel width W
When is short, the abnormal drop in threshold voltage that occurs in the BOX method can be easily avoided. For this reason, M.O.
The threshold voltage of an 8-type semiconductor device can be adjusted to a designed value with good controllability. In addition, the process is simple since ion implantation is performed only twice.

[Embodiments of the invention]

Figures 1 (a), (b) to Figure 8 (a), (b)
) shows the manufacturing process of a MOS transistor according to an embodiment of the present invention, (a) is a sectional view, and (0)) is a plan view. First, Figure 1 (a) T (b)
A Pffi silicon substrate 1 containing boron with a plane orientation (100) and a resistivity of about 5 to 50 [f-no-] as shown in the figure is prepared, and the element formation area of the substrate is etched with a mask 2 by a normal photolithography process. Then, the field region of the silicon substrate 1 is etched by an amount corresponding to the desired field film thickness.

Next, as shown in FIGS. 2(a) and 2(b), an impurity, such as boron B, which forms the same electric type as the silicon substrate 1, is ion-implanted into the field region using the same mask 2 to prevent field reversal. , forming the anti-inversion layer 3. Thereafter, as shown in FIGS. 3(a) and 3(b), a silicon oxide film 4 is buried in the field region using a lift-off process. This lift-off processing is performed, for example, as follows.

That is, plasma CVD5 is applied to the entire surface of the silicon substrate I.
Deposit the j02 film. Next, when the entire surface is etched with ammonium fluoride, the plasma CVN deposited on the side surface of the step formed at the boundary between the field region and the element formation region is removed.
sio, the etching rate of the film is 3 to 3 compared to the flat part.
Because it is 20 times faster, plasma CVD5 on the side surface of the step part
The io2 film is selectively removed. Thereafter, when the mask 2 on the element forming region is removed, the plasma CVD5iO□ film deposited on the mask 2 is also removed, and the plasma CVD5iO□ film 4 is buried in the field region. At this time, a narrow groove 5 with a constant cross-sectional shape is left at the boundary between the field region and the element forming region, as shown in FIG. 3(a).

Next, as shown in FIGS. 4(a) and 4(b), when a CVD sio2 film 6 is deposited on the entire surface so as to bury the narrow groove 5, a constant layer is formed on the surface of the CVD5 to □ film 6 at the top of the narrow groove 5. A recess 7 is formed. Subsequently, a fluid film 8 is formed which is fluid and has an etching rate equal to that of the CVD 5iO film 6, and the mortar s7 is embedded and its surface is flattened.

Next, as shown in FIGS. 5(a) and 5(b), when the fluid film 8 and the cvDsjot film 6 are etched away from the entire surface to expose the element formation region, the field region becomes C.
It is buried substantially flat with the vDS1026 film and the plasma CvDS1024 film.

Next, a predetermined element is formed in the exposed element formation region. That is, in a dry oxidation furnace, for example, 90
0(C) and FIG. 6(a).

A gate oxide film 9 (310 [:A) as shown in FIG. This is etched by photolithography, leaving a predetermined portion.

Next, when forming sources and drains by ion implantation, which is a feature of the present invention, first a low dose of 3 x 10
” (/cd) and set the acceleration voltage to 50KV, Figure 7(a)
), as shown in (b), arsenic A8. ) Ion implantation (shaded area in FIG. 7 (1)) was performed. In this example, the width W of the source and drain was 2.0 [μm]. Subsequently, 4-on implantation was performed using a mask and a high-precision aligner that entered inward from the W direction by 0.6 [μm] on each side. By the way, the alignment accuracy of the high-precision aligner used is 0.3 at 3V.
[μm]. That is, Fig. 8(a), (b
), arsenic AB was ion-implanted again into a slightly narrow region in the width direction (Fig. 8 (hatched area in BL)) at a daytime dose of, for example, 5xlO (/-) and an accelerating voltage of 50 [proof].

In this example, one mask was prepared for the second high-dose ion implantation. In this mask, ions are also implanted into the polycrystalline silicon gate part, so that the gate electrode becomes N+. In addition, in consideration of mask misalignment in the channel direction during ion implantation of polycrystalline silicon, care was taken to avoid ion implantation into the first low dose area. Thus the sauce
formed a drain.

Next, a CVD oxide film is deposited on the element formation region and field region, and a so-called PSGCVD film containing phosphorus impurities is deposited.
The film was deposited and the prescribed thermal steps were completed. Thereafter, using photolithography and etching techniques, contact holes for wiring were made, and predetermined wiring was placed in the source/drain/gate electrode portions. At this point, in terms of channel width, the high-dose region had expanded a little in the lateral direction, and was 027 [μm] deeper into the channel than the low-dose region in the spinning period. Thereafter, sintering was performed, and the electrical characteristics of the formed MOS transistor were measured. The measurement results are shown in FIG. 9 by O.

The figure also shows cases in which the channel width W on the mask is varied in various ways. In any case,
For example, a substantially expected value is achieved for a predetermined threshold voltage tO (V). Incidentally, FIG. 9 also shows the variation. At this time, the first. When the sheet resistance (fs) and junction depth (Xj) were inspected on a test silicon substrate that had undergone the same thermal process after the second ion implantation, the first
In the region where only the second ion implantation is performed, fs is 70 [Ω
/mouth] and Xj was 0.29 (, μm).

Further, in the area that underwent both the first and second steps, fs was 28 (#/c+) and xj was 0.31 (μm).

In order to examine the effects of the present invention in more detail, we will compare the conventional method, that is, the case of only the element isolation process using the BOX method. The results obtained when using the lateral spread due to injection are shown by the mark in the middle of Figure 2.

As can be seen from FIG. 9, the fluctuation of the threshold voltage is large with respect to the channel width W, and the variation thereof is also large compared to the example. Element isolation process by BOX method and 1. BOX
As a method for completely eliminating the drop in threshold voltage peculiar to the method, a method in which a conventional process utilizing lateral spreading by ion implantation is combined has the following drawbacks. That is, in order to obtain lateral spread of impurities, in the first ion implantation step, it is necessary to perform ion implantation of holons at an accelerating voltage with a projection range Rf that is approximately half the depth of the recess that will be formed thereafter. be. In this case, the standard deviation value ΔRf in the depth direction is 1. /2 to 1//3 in size ζ. Although ions such as boron are relatively light and the lateral spread △X of the ions under the mask is relatively large, it is still only △X + △Rf at most, so the size itself is actually very large. small. Talented, △
In order to increase X, it is necessary to increase ΔRf, and in that case, the acceleration voltage must be increased. In this case, the projected range Rf becomes large and it becomes difficult to control the descent of the VT. Furthermore, if too much poron is implanted on the side surfaces of the recess, the diffusion coefficient of poron itself is large, so that boron will inevitably diffuse in the center of the element formation region during subsequent heat treatment. If this happens, the original threshold voltage itself will be distorted, and furthermore, there will be negative effects on the device characteristics, such as a decrease in the withstand voltage of the diffusion layer formed in the device formation region and an increase in parasitic capacitance.

The present inventors further investigated the following three points in order to verify the effects of the present invention. That is, (1) a comparison of the implantation doses of the first and second ion implantations for source/drain formation, (2) the range of the implanted region in the second high-dose ion implantation, and ( 3) This is the physical property basis for obtaining the effects of the present invention. Regarding the first consideration, first, in the high dose region, in order to achieve the xj and fs required for the device characteristics, the approximately normal 3 to 5
A dose of about 10 (cd) is good, and as a result of various careful investigations into the low dose range, it has been found that for any value, one order of magnitude or less than the above value is better. Further, as a result of investigation regarding the second point, it was found that it is optimal to narrow the end dimensions by 0.25 to 0.3 C, μm from both sides in the W direction.

Incidentally, when the high dose region was narrowed in the L direction ζ, the voltage-current characteristics deteriorated. Regarding the third point, this will lead to investigating the phenomenon of threshold voltage drop especially when W is small, which would be possible if only the BOX method was used. It turns out that this is due to the fact that it flows easily. In order to reduce the contribution of this path, it is better to make it difficult for current to pass through the region at the edge of the source/drain in the width direction in advance, as in the present invention, thereby reducing the contribution of this portion to VT and reducing the overall effect. This leads to suppressing fluctuations in the threshold value VT. Further, according to the studies of the present inventors, it has been confirmed that the effect of the present invention is even more effective when the channel length is short.

Note that the present invention is not limited to the embodiments described above, and can be implemented with various modifications without departing from the gist thereof. For example, the impurity to be ion-implanted into the source/drain region and a part of the region is not limited to arsenic, but may be any impurity that forms a reverse conductor and a mold with the substrate. Furthermore, the dose of ion implantation may be appropriately determined within a range where the second ion implantation is one order of magnitude larger than the first ion implantation. Also M
Of course, the present invention can be applied not only to OS h transistors but also to various other MO8 type semiconductor devices.

[Brief explanation of the drawing]

Figures 1 (a), (b) to Figure 8 (a), (b)
) shows the manufacturing process of a MOS transistor according to an embodiment of the present invention, (a) shows a cross-sectional view, (b) shows a plan view, and FIG. 9 explains the operation of the method of the above embodiment. 0 1... P-type silicon substrate (semiconductor substrate), 2... Mask film, 4, 6... Silicon oxide film, 8... Fluid film, 9... Gate oxide film, 10... Polycrystalline silicon film. Applicant's agent: Patent attorney Takehiko Suzue Figure 5 Figure 6

Claims (2)

[Claims] (1) A step of forming a film on the element formation region of a semiconductor substrate, selectively etching the substrate using the film as a mask, and forming a recess in the field region of the substrate, and forming a recess at least at the bottom of the recess in the same manner as the substrate. A process of ion-implanting impurities that create a conductivity type, and then burying a first insulating film in the recess with a groove formed around it, and then depositing a second insulating film to fill the groove. a step of etching the entire surface to expose the element formation region of the substrate with the first and second insulating films buried in the recesses; A step of ion-implanting an impurity that has a conductivity type opposite to that of the substrate, and then implanting ions into both sides of the source/drain formation region in the width direction at a dose that is at least one order of magnitude higher than the dose of the impurity ion-implanted into the source/drain formation region. A MOS characterized by comprising a step of ion-implanting an impurity that has a conductivity opposite to that of the substrate and forms a mold into a portion other than the substrate.
A method for manufacturing a type semiconductor device. (2) The step of ion-implanting impurities into the portions of the source/drain formation region other than both sides in the width direction is such that the ion-implanted layer formed by the ion implantation is formed in the source/drain formation region at the time when each step described below is completed. A method for manufacturing a MOS type semiconductor device according to claim 1, wherein ions are implanted so as to be 0.25 to 03 μm inside from both ends in the width direction.