JPS58190044A - Ceramic package type semiconductor device - Google Patents

Ceramic package type semiconductor device

Info

Publication number
JPS58190044A
JPS58190044A JP58068633A JP6863383A JPS58190044A JP S58190044 A JPS58190044 A JP S58190044A JP 58068633 A JP58068633 A JP 58068633A JP 6863383 A JP6863383 A JP 6863383A JP S58190044 A JPS58190044 A JP S58190044A
Authority
JP
Japan
Prior art keywords
semiconductor device
package
packages
performance
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58068633A
Other languages
Japanese (ja)
Inventor
Eiji Hagimoto
萩本　英二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58068633A priority Critical patent/JPS58190044A/en
Publication of JPS58190044A publication Critical patent/JPS58190044A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To easily classify the packages to be used and discriminate the terminal No.1 without confusion with the marking for indicating performance after assembling by providing a metallized layer to the direction indicator (notch) of package. CONSTITUTION:In case an alphabet C is indicated on the ceramic surface 2 of the notch 1 having a recess, performance of semiconductor device can be acknowledged correctly by giving an indication for performance at the surface 2, in place of giving such indication to the No.1 terminal location indicating portion 4. (For example, the sign 0 or 1 is given to this indicating portion 4.) Moreover, there is an advantage that misunderstanding is not given in regard to the packages used for assembling in case if there are several kinds of packages having the same appearance and different only in the location of ground terminal at the time of assembling semiconductor device. This advantage can also be applied to the manufacturing of the package, and working can be performed for the packages which are different in the location of ground terminal, with the metallized pattern of notch portion being considered as the marking.

Description

【発明の詳細な説明】 本発明はセラミックパッケージ型の半導体装置に係り、
特にセラミックの半導体装置用パッケージにおけるパッ
ケージ名称、グランド端子番号等の表示構造に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a ceramic package type semiconductor device,
In particular, it relates to the display structure of the package name, ground terminal number, etc. in a ceramic semiconductor device package.

従来、セラミックの半導体装置用パッケージ（以下パッ
ケージと称する）における多数端子の内筒１＃端子位置
の表示は次のように行なわれている。Conventionally, the position of the inner tube 1# terminal of multiple terminals in a ceramic semiconductor device package (hereinafter referred to as package) has been indicated as follows.

パッケージのセラミックの第１番端子位置近傍の土間に
メタライズ１＠又は樹脂インキを用いて表示していた。It was indicated using metallized 1@ or resin ink on the dirt floor near the first ceramic terminal position of the package.

しかし、これらの表示において特にセセラミックを基体
とする気密封止型パッケージにおいては、該パッケージ
の第１番端子位置を表示する場所とほぼ同一位置に、半
導体素子（ｉｌ−組立てて半導体装置としたときの性能
別表示を付する場合があり、かかる場合にはあらかじめ
基体に表示された記号と性能別表示との誤認を生ずる町
貧し性がある。例えば性能別表示として画点が用いられ
た場合に、この画点による性能表示に対して、前記メタ
ライズ層に金（Ａｕ）メッキ時に無電解的にＡｕが付着
した第１番端子表示は極めて晃まちがえ易い。However, in these displays, especially for hermetically sealed packages based on ceramics, the semiconductor element (IL- assembled into a semiconductor device) is displayed at almost the same position as the position of the first terminal of the package. In some cases, performance-based markings may be attached to the product, and in such cases, there is a risk of confusion between the symbol displayed on the base and the performance-based marking.For example, if a dot is used as the performance-based marking. Furthermore, in contrast to the performance display using the dots, the display of the first terminal in which Au is electrolessly attached to the metallized layer during gold plating is extremely easy to confuse.

本発明は、かかる問題点を改善する改良されたセラミッ
クパッケージを有する半導体装１ｆ’に提供するもので
ある。The present invention provides a semiconductor device 1f' having an improved ceramic package that overcomes these problems.

本発明の特徴は、パッケージの方向指示部（以下ノツチ
部と称する。）にメタライズ層を設けてかかる表示記号
を付したセラミックパッケージ型の半導体装置にある。A feature of the present invention is a ceramic package type semiconductor device in which a metallized layer is provided on a direction indicating portion (hereinafter referred to as a notch portion) of the package and such a display symbol is attached.

以下に実施例を用いて、本発明を具体的に説明する。The present invention will be specifically described below using Examples.

第１図（ａ）は、本発明ヶ気密封止型の積層セラミック
パッケージに適用した場合の実施例を示す。FIG. 1(a) shows an embodiment in which the present invention is applied to a hermetically sealed multilayer ceramic package.

本実施例においては凹みのあるノツチ部１のセラミック
表面２の上にアルファベットのＣを表示した場合を示し
ている。そして、従来のパッケージに付すべき第１番端
子位置表示部４にはかかる表示をつけず、表面２のとこ
ろに性能別表示を付することにすれば半導体装置の性能
誤認は生じない。In this embodiment, a case is shown in which the alphabet C is displayed on the ceramic surface 2 of the notch portion 1 having a recess. If such a display is not attached to the first terminal position display section 4, which should be attached to a conventional package, but a performance-based display is attached to the surface 2, misunderstanding of the performance of the semiconductor device will not occur.

（この表示部４には、例えばＯや１の記号を入れる。）
また、半導体装置の組立時において特にパッケージ外観
が同一でグランド端子の位置のみが異なる数種類のパッ
ケージが存在する場合には組立に使用するパッケージに
錯誤を生じないという利点がある。このことはパッケー
ジの製造時にも直えることで、グランド端子の位置が異
なるもの３− は、そのノツチ部のメタライズパターンを目印として作
業を定めることができる。(For example, a symbol such as O or 1 is entered in this display section 4.)
Furthermore, when assembling a semiconductor device, there is an advantage that there is no confusion regarding the package to be used for assembly, especially when there are several types of packages that have the same package appearance but differ only in the position of the ground terminal. This can be corrected during package manufacturing, and for packages with different ground terminal positions, the work can be determined using the metallized pattern of the notch as a guide.

第１図（ｂ）は第１図（ａｌの績ｊ−セラミックパッケ
ージの断面図である。かかる断面図においては、半導体
装ＩＪｊｔｋ載置すべきマウント面５とノツチ部セラミ
ック底面２とを同一平面にとっである場合を示す。FIG. 1(b) is a sectional view of the ceramic package shown in FIG. Indicates when it is.

本発明によれば、使用するパッケージの区分。According to the invention, the classification of the packages used.

第１番端子などが容易に判別可能であり、さらに組立て
後の性能表示のマーキングとの誤認がない。The No. 1 terminal etc. can be easily identified, and furthermore, there is no misidentification with the performance marking after assembly.

さらに、このパッケージの表示がメタライズ層によって
形成されているので５組立て中の熱処理。Furthermore, since the display of this package is formed by a metallized layer, 5 heat treatment during assembly is required.

機械的な力等によって変質、剥離の心配もない。There is no need to worry about deterioration or peeling due to mechanical force.

【図面の簡単な説明】[Brief explanation of drawings]

第１図（ａ）は本発明の実施例を示すパッケージの平面
図、第１図（ｂ）はその断面図を示す。FIG. 1(a) is a plan view of a package showing an embodiment of the present invention, and FIG. 1(b) is a sectional view thereof.

Claims (1)

【特許請求の範囲】[Claims] セラミックケースの一生表面に四部が設けられて半導体
素子が収納され、該セラミックケースの外周辺の一部に
切欠部が設けられたセラミックパッケージ型半導体装置
において、該切欠部にメタライズ層によって形成された
記号が設けられていることを特徴とするセラミックパッ
ケージ型半導体装置。In a ceramic package type semiconductor device in which a semiconductor element is housed in four parts provided on the surface of a ceramic case, and a cutout part is provided in a part of the outer periphery of the ceramic case, the cutout part is formed of a metallized layer. A ceramic package type semiconductor device characterized by being provided with a symbol.
JP58068633A 1983-04-19 1983-04-19 Ceramic package type semiconductor device Pending JPS58190044A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58068633A JPS58190044A (en) 1983-04-19 1983-04-19 Ceramic package type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58068633A JPS58190044A (en) 1983-04-19 1983-04-19 Ceramic package type semiconductor device

Publications (1)

Publication Number Publication Date
JPS58190044A true JPS58190044A (en) 1983-11-05

Family

ID=13379334

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58068633A Pending JPS58190044A (en) 1983-04-19 1983-04-19 Ceramic package type semiconductor device

Country Status (1)

Country Link
JP (1) JPS58190044A (en)

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