JPH01310548A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPH01310548A
JPH01310548A JP63142285A JP14228588A JPH01310548A JP H01310548 A JPH01310548 A JP H01310548A JP 63142285 A JP63142285 A JP 63142285A JP 14228588 A JP14228588 A JP 14228588A JP H01310548 A JPH01310548 A JP H01310548A
Authority
JP
Japan
Prior art keywords
pad
pads
semiconductor integrated
integrated circuit
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63142285A
Other languages
Japanese (ja)
Inventor
Noriaki Takagi
範明 高木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63142285A priority Critical patent/JPH01310548A/en
Publication of JPH01310548A publication Critical patent/JPH01310548A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512—Aligning
    • H01L2224/85121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/8513—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To facilitate the confirmation of pads to be bonded during the assembling process by a method wherein electrode pads with pad identification codes are provided. CONSTITUTION:Multiple pads 2 taking rectangular or square shape are juxtaposed along a semiconductor integrated circuit 1 to be led out by gold wire or aluminum wire bonding process. The bonding wires are bonded onto the ranges displayed by the circles while pad identification codes 4 are written on every four corners of the pads 2 not to be hidden by any slipped bonding positions. Furthermore, respective pads 2 are provided with different pad identification codes e.g. Arabic numerals etc., in series from '1' to facilitate the identification. Through these procedures, any pad to be bonded during the assembling process can be easily confirmed so that the objective pad may be immediately found out of numerous pads in order to evaluate the electrical properties in a state of wafer.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体集積回路装置に関し特に組立工程及び
、ウェハー状での電気的特性測定等に便利な電極パッド
の形状に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a shape of an electrode pad convenient for assembly process and measurement of electrical characteristics in a wafer shape.

〔従来の技術〕[Conventional technology]

従来から半導体集積回路装置には、その内周に沿って、
パッドと呼ばれるものが並べられている。このパッドは
導伝性材料で作られ、ボンディング等により半導体集積
回路装置の信号を、外部へ引き出す為の端子の役目をし
ており、ボンディングパッドとも呼ばれている。又、そ
の大きさ及び形状は、１辺が、１００〜２００μｍの長
方形あるいは、正方形である場合が多い。Traditionally, semiconductor integrated circuit devices have a
There are things called pads lined up. This pad is made of a conductive material and serves as a terminal for extracting signals from a semiconductor integrated circuit device to the outside through bonding or the like, and is also called a bonding pad. Moreover, its size and shape are often rectangular or square with one side of 100 to 200 μm.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来のパッドは、半導体集積回路装置において
、その形状が同一である場合がほとんどである。この事
は多数のパッドを有する半導体集積回路において、次の
ような欠点がある。まず第１にゲートアレイなどの半導
体集積回路装置は搭載するパッケージ毎にボンディング
するパッドが異なっており、その為組立工程時に、ボン
ディングするパッドをまちがえる危険がある。この事は
、半導体集積回路装置の品質の低下にもつながる。又第
２に、ウェハー状で電気的特性を評価する場合に、パッ
ドの数が多いと目的のパッドをさがすのが大変である。In most cases, the conventional pads described above have the same shape in a semiconductor integrated circuit device. This has the following disadvantages in semiconductor integrated circuits having a large number of pads. First of all, semiconductor integrated circuit devices such as gate arrays have different bonding pads depending on the package in which they are mounted, so there is a risk of making a mistake in the bonding pads during the assembly process. This also leads to deterioration in the quality of the semiconductor integrated circuit device. Secondly, when evaluating the electrical characteristics of a wafer, it is difficult to find a target pad if there are a large number of pads.

とくに、顕微鏡等で、はしからパッドを数えて目的のパ
ッドをみつけるのは、非効率である。第３に上記欠点を
補う為に、従来はパッドの近傍に、アラビア数字等のパ
ッド識別記号を付けていたが、最近の半導体集積回路装
置では、集積度が大幅に上っている為、パッド識別記号
を付けるスペースが、はとんどない。その為現在ではパ
ッド近傍にパッド識別記号を付けられないのが現状であ
る。In particular, it is inefficient to find the desired pad by counting the pads from the edge using a microscope or the like. Thirdly, in order to compensate for the above drawback, pad identification symbols such as Arabic numerals were traditionally attached near the pads, but in recent semiconductor integrated circuit devices, the degree of integration has increased significantly, so pad There is not enough space to put an identification symbol. Therefore, at present, it is not possible to attach a pad identification symbol near the pad.

〔課題を解決するための手段〕[Means to solve the problem]

本発明によれば、パッド内に、パッド識別用の記号例え
ば、アラビア数字等を有した電極パッドを備えた半導体
集積回路装置を得る。According to the present invention, a semiconductor integrated circuit device is provided which includes electrode pads having pad identification symbols, such as Arabic numerals, in the pads.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図は、本発明の一実施例の平面図であり第２図はそ
の全景図である。図中で１は半導体集積回路装置、２は
パッド２３はボンディングワイヤーがボンディングされ
る範囲、４はパッド識別記号である。一般に半導体集積
回路１は、その円周に沿って、パッド２が、多数並べら
れている。FIG. 1 is a plan view of one embodiment of the present invention, and FIG. 2 is a panoramic view thereof. In the figure, 1 is a semiconductor integrated circuit device, 2 is a pad 23 is a range to which a bonding wire is bonded, and 4 is a pad identification symbol. Generally, a semiconductor integrated circuit 1 has a large number of pads 2 arranged along its circumference.

そのパッド２は形状が１００〜２００μｍの長方形ある
いは正方形であり、直径３０μｍ程度の金線やアルミニ
ウム線でボンディングにより外部へ信号が引き出される
。ボンディングは、ボンディングワイヤー３が、ボンデ
ィングされる範囲で示された範囲にボンディングされる
。パッド識別記号４は、たとえボンディング位置がずれ
てもかくれてしまわないように、パッド２の四隅すべて
に付ける。付ける方法としてはパッド２をエツチング等
により形成する時に同時に、パッド識別記号４をエツチ
ングすれば良い。又、パッド識別記号４は各々のパッド
２の各々に異った記号例えば例えば、アラビア数字等を
１″から順番に付けるのが、わかりやすい。The pad 2 has a rectangular or square shape with a diameter of 100 to 200 μm, and a signal is extracted to the outside by bonding with a gold wire or aluminum wire with a diameter of about 30 μm. In the bonding, the bonding wire 3 is bonded in the range indicated in the bonding range. The pad identification symbols 4 are attached to all four corners of the pad 2 so that they will not be hidden even if the bonding position is shifted. The pad identification symbol 4 may be etched at the same time as the pad 2 is formed by etching or the like. Further, it is easier to understand that the pad identification symbol 4 is given to each pad 2 with a different symbol, for example, an Arabic numeral, etc., in order starting from 1''.

第３図は本発明の他の実施例の平面図である。FIG. 3 is a plan view of another embodiment of the invention.

本図はとくにパッド部分を拡大して示したものである。This figure shows a particularly enlarged view of the pad portion.

さて最近の半導体集積回路は配線層が２層で、その配線
材料としてアルミニウム等が用いられる場合が多くパッ
ドも配線層と同様に２層になる場合がほとんどである。Now, recent semiconductor integrated circuits have two wiring layers, and aluminum or the like is often used as the wiring material, and in most cases, the pads also have two layers like the wiring layers.

そして１層と２層の電気的接続にはスルーホールと呼ば
れる穴を１・２層の絶縁膜にあけて行う。このスルーホ
ーを用いてパッド内に識別記号を付けたものが第３図で
ある。図中、５はアルミニウムでできた１層目のパッド
であり、６はアルミニウムでできた２層目のパッド、７
はスルーホール、８はボンディングワイヤーがボンディ
ングされる範囲、９はパッド識別記号の形をしたスルー
ホールを示す。この場合、２層目のパッド６のアルミニ
ウムはスルーホールの部分がくぼんで見えるが、これは
スルーホールの深さ分だけ２層目のパッド６のアルミニ
ウムがスルーホールに落ち込む為である。ところで、パ
ッド識別記号の形をしたスルーホール９を有している為
、２層目のパッド６の上から見るとそのスルーホールに
沿ってパッド識別記号が見える事になる。Electrical connections between the first and second layers are made by making holes called through holes in the first and second layers of the insulating film. FIG. 3 shows an identification mark inside the pad using this through-hole. In the figure, 5 is the first layer pad made of aluminum, 6 is the second layer pad made of aluminum, and 7 is the first layer pad made of aluminum.
8 indicates a through hole, 8 indicates a range where a bonding wire is bonded, and 9 indicates a through hole in the shape of a pad identification symbol. In this case, the aluminum of the second layer pad 6 appears depressed at the through hole, but this is because the aluminum of the second layer pad 6 falls into the through hole by the depth of the through hole. By the way, since it has a through hole 9 in the shape of a pad identification symbol, when the second layer pad 6 is viewed from above, the pad identification symbol can be seen along the through hole.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明は、パッドにパッド識別記
号を付ける事により、組立工程時にパッドの位置を確認
しながらボンディングする事が容易にでき、又、ボンデ
ィング時に確認する場合も効率よく確実にできるという
効果がある。又、ウェハー状で電気的特性を評価する場
合多数並んでいる。パッドの中から目的のパッドがすぐ
に見つかるという効果がある。さらにパッド内にパッド
識別記号を付ける為、高集積化の進んだ現在の半導体集
積回路装置おいてパッド識別記号のスペース上の制約を
受けないという効果がある。As explained above, the present invention makes it possible to easily bond while confirming the position of the pad during the assembly process by attaching a pad identification symbol to the pad, and also enables efficient and reliable confirmation during bonding. There is an effect that it can be done. In addition, when evaluating electrical characteristics in the form of a wafer, a large number of them are lined up. This has the effect of quickly finding the desired pad among the pads. Furthermore, since the pad identification symbol is attached within the pad, there is an effect that there is no space restriction of the pad identification symbol in the current highly integrated semiconductor integrated circuit devices.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例の半導体集積回路チップの部
分平面図、第２図は第１図のチップの全体を示す平面図
、第３図は本発明の他の実施例による半導体集積回路チ
ップの部平面図である。 １・・・・・・半導体集積回路装置、２・・・・・・パ
ッド、３・・・・・・ボンディングワイヤーがボンディ
ングされる範囲、４・・・・・・パッド識別記号、５・
・・・・・１層目のパッド、６・・・・・・２１目のパ
ッド、７・・・・・・スル−ホール、８・・・・・・ボ
ンディングワイヤーがボンディングされる範囲、９・・
・・・・パッド識別記号の形をしたスルーホール。 代理人　弁理士　　内　原　　　音 閉１図 第２図 第３図FIG. 1 is a partial plan view of a semiconductor integrated circuit chip according to an embodiment of the present invention, FIG. 2 is a plan view showing the entire chip of FIG. 1, and FIG. 3 is a semiconductor integrated circuit chip according to another embodiment of the present invention. FIG. 2 is a partial plan view of a circuit chip. 1...Semiconductor integrated circuit device, 2...Pad, 3...Range to which the bonding wire is bonded, 4...Pad identification symbol, 5...
...First layer pad, 6...21st pad, 7...Through hole, 8... Range where bonding wire is bonded, 9・・・
...Through hole in the shape of a pad identification symbol. Agent Patent Attorney Uchihara Otohiro Figure 1 Figure 2 Figure 3

Claims (1)

【特許請求の範囲】[Claims] 　ボンディングする為のパッドを有する半導体集積回路
装置において、前記パッドがパッド内にパッド識別用の
記号を有する事を特徴とする半導体集積回路装置。1. A semiconductor integrated circuit device having a pad for bonding, wherein the pad has a pad identification symbol within the pad.
JP63142285A 1988-06-08 1988-06-08 Semiconductor integrated circuit device Pending JPH01310548A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63142285A JPH01310548A (en) 1988-06-08 1988-06-08 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63142285A JPH01310548A (en) 1988-06-08 1988-06-08 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPH01310548A true JPH01310548A (en) 1989-12-14

Family

ID=15311815

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63142285A Pending JPH01310548A (en) 1988-06-08 1988-06-08 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPH01310548A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5760421A (en) * 1993-06-10 1998-06-02 Canon Kabushiki Kaisha Semiconductor device including indices for identifying positions of elements in the device.

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5378768A (en) * 1976-12-23 1978-07-12 Toshiba Corp Wire bonding method of semiconductor element
JPS53132122A (en) * 1977-04-25 1978-11-17 Furukawa Electric Co Ltd Machine for burying linear material under sea bottom
JPS5547795B2 (en) * 1975-08-06 1980-12-02
JPS63108393A (en) * 1986-10-27 1988-05-13 京セラミタ株式会社 Character generator

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5547795B2 (en) * 1975-08-06 1980-12-02
JPS5378768A (en) * 1976-12-23 1978-07-12 Toshiba Corp Wire bonding method of semiconductor element
JPS53132122A (en) * 1977-04-25 1978-11-17 Furukawa Electric Co Ltd Machine for burying linear material under sea bottom
JPS63108393A (en) * 1986-10-27 1988-05-13 京セラミタ株式会社 Character generator

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5760421A (en) * 1993-06-10 1998-06-02 Canon Kabushiki Kaisha Semiconductor device including indices for identifying positions of elements in the device.

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