JPS58197752A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS58197752A
JPS58197752A JP58068634A JP6863483A JPS58197752A JP S58197752 A JPS58197752 A JP S58197752A JP 58068634 A JP58068634 A JP 58068634A JP 6863483 A JP6863483 A JP 6863483A JP S58197752 A JPS58197752 A JP S58197752A
Authority
JP
Japan
Prior art keywords
package
mark
notch part
notch
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58068634A
Other languages
Japanese (ja)
Inventor
Eiji Hagimoto
萩本　英二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58068634A priority Critical patent/JPS58197752A/en
Publication of JPS58197752A publication Critical patent/JPS58197752A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54406—Marks applied to semiconductor devices or parts comprising alphanumeric information
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

PURPOSE:To obtain an indication mark having no fear of misconception at the semiconductor device provided with a notch part at a part of the outside circumference of a package by a method wherein the notch part is utilized to print the article name, the mark by performance thereon. CONSTITUTION:The alphabet C, etc., to indicate the article name, performance, etc., are formed by printing on the surface 2 of a ceramics at the notch part 1 having a cavity provided in the airtightly sealing package. Namely, at the position indicating part 4 of the first terminal 3 to be applied to a normal package, the mark like this is not provided, and is provided at the notch part 1 to make to be easy to see. Otherwise, when the notch part 1 is penetrating the substrate vertically, the mark of the numeral 1, etc., is adhered on the side of the notch 1. The mark like this can be provided easily by offset printing using metallized ink or resin ink.

Description

【発明の詳細な説明】 本発明は半導体装置に係り、特に半導体装置用パッケー
ジにおけるパッケージ名称グランド端子番号の表示構造
に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to a display structure for a package name and ground terminal number in a package for a semiconductor device.

従来、半導体装置用パッケージ（以下パッケージと称す
る）における多数熾子の内温１番端子位置の表示は次の
ように行なわれている。パッケージの基本例えば気密封
止型であればセラミック７、樹脂封止型であれば樹脂材
料の第１番肩子位置近傍の上面にメタライズ・イ、ンキ
又は樹脂インキを用いて表示してい丸。しかし、これら
の表示において特にセラミックを基体とする気密封止型
パッケージにおいては、該パッケージの第１番肩子位置
を表示する場所とほぼ同一位置に、半導体素子を組立て
半導体装置としたときに性能別表示を付する場合があり
、かかる場合にはあらかじめ基体に表示された記号は性
能別表示のｌｉ！４認を生ずる可能性がある。例えば黄
煮による性能表示に対して、Ａｕメッキ時に、無電解的
にＡｕが付着し九第１番趨子表示があげられる。樹脂封
止型であっても、性能別表示の要請は前記気密封止型パ
ッケージの場合と同様であり１品名１産地表示等の記号
とのかね合いもあって性能別表示に使用できるスペース
は限られてきているのが現状である。Conventionally, the position of the internal temperature No. 1 terminal of a semiconductor device package (hereinafter referred to as a package) is indicated as follows. Basics of the package For example, if it is an airtight seal type, it is marked with ceramic 7, or if it is a resin seal type, it is marked with metallized ink or resin ink on the top surface of the resin material near the first shoulder position. However, in these displays, especially in the case of a hermetically sealed package with a ceramic base, when the semiconductor element is assembled into a semiconductor device at almost the same position as the first shoulder position of the package, the performance In some cases, a separate indication may be attached, and in such cases, the symbol pre-displayed on the base is the li! There is a possibility of giving rise to a For example, in contrast to the performance indication by boiling in yellow, Au is electrolessly attached during Au plating, resulting in No. 9 No. 1 trend indication. Even for resin-sealed types, the requirements for performance-based labeling are the same as for hermetically sealed packages, and there is a conflict with symbols such as 1 product name and 1 production area, so the space that can be used for performance-based labeling is limited. The current situation is that it is limited.

本発明はかかる現状を改善する改良されたパッケージを
有する半導体装置を提供するものである。The present invention provides a semiconductor device having an improved package that improves the current situation.

本発明の特徴はパッケージの方向指示部（以下ノツチ部
と称する。）にかかる表示記号を付することにある。A feature of the present invention is that a display symbol is attached to the direction indicating part (hereinafter referred to as a notch part) of the package.

以下に実施例を用いて１本発明の詳細な説明する。The present invention will be described in detail below using examples.

第１図（ａ）は、本発明を気密封止型パッケージに適用
した場合の実施例を示す。本実施例においては凹みのあ
るノツチ部１のセラミック表面２の上にアルファベット
のＣを表示し九場合を示している。そして、従来のパッ
ケージに付すべき第ＩＷ湖子位置表示部４にはかかる表
示をつけず、表面２のところに性能別表示を付すること
にすれば半導体装置の性能誤認は生じない。（この表示
部４には、例えばＯや１の記号を入れる。）また、半導
体装置の組立時において特にパッケージ外観が同一でグ
ランド端子の位置のみが異なる数種類のパッケージが存
在する場合には組立に使用するパッケージに錯誤を生じ
ないという利点がある。このことはパッケージの製造時
にもきえることで、グランド端子の位置が異なる。もの
は、そのノツチ部の印刷パターンを目印として作条を定
めることができる。第１図（ｂ）は本発明を説明するだ
めの積層型セラミックパッケージでの部分を説明する断
面図である。かかる断面図においては、半導体装置を載
置すべきマウント面５とノツチ部セラミック底面２とを
同一平面にとっである場合を示す。FIG. 1(a) shows an embodiment in which the present invention is applied to a hermetically sealed package. In this embodiment, the alphabet C is displayed on the ceramic surface 2 of the notch portion 1 having a concave portion to indicate the case of 9. If such a display is not attached to the IW position display section 4, which should be attached to a conventional package, but a performance-based display is attached to the surface 2, misunderstanding of the performance of the semiconductor device will not occur. (For example, a symbol such as O or 1 is entered in this display section 4.) Also, when assembling a semiconductor device, especially when there are several types of packages that have the same package appearance but differ only in the position of the ground terminal, it is difficult to assemble. This has the advantage that there is no confusion regarding the package used. This also applies when manufacturing packages, and the position of the ground terminal differs. The printing pattern of the notch part of the material can be used as a guide to determine the rows. FIG. 1(b) is a sectional view illustrating a portion of a laminated ceramic package for explaining the present invention. This sectional view shows the case where the mounting surface 5 on which the semiconductor device is mounted and the notch ceramic bottom surface 2 are on the same plane.

第２図は本発明の他の実施例を示すものである。FIG. 2 shows another embodiment of the invention.

本実施例においてはノツチ部１は基体の上下を貫いてお
り、付すべき性能別記号はその側面に表示することにな
る。このような記号を付する方法についてはオフセット
印刷等の従来の技術を使用できるＯ 以上、第１図（ａ）、第１図（ｂ）、第２図においては
気密封止型セラミックケースの場合を取り上げたが、本
発明はセラミックパッケージに限定されることはなく、
−脂封止型パッケージの場合にも適用できるのは当然で
ある。In this embodiment, the notch portion 1 passes through the top and bottom of the base body, and the performance symbol to be attached is displayed on the side surface thereof. Conventional techniques such as offset printing can be used to attach such symbols. In the above, Figures 1(a), 1(b), and 2 are for hermetically sealed ceramic cases. However, the present invention is not limited to ceramic packages;
-Of course, it can also be applied to oil-sealed packages.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ａ）は本発明の第１の実施例を示すパッケージ
の平面図、第１図（ｂ）はその断面図を示す。 第２図は本発明の第２の実施例を示すパッケージの斜視
図である。 尚、図において、１・・・・・ノツチ部、２・・川・ノ
ツチ部底面、３・・・・・・第１番端子、４・・・・・
・第１番端子部　ｌ　閏　（ａ） め　ｌ　ぶつ（ｂ）FIG. 1(a) is a plan view of a package showing a first embodiment of the present invention, and FIG. 1(b) is a sectional view thereof. FIG. 2 is a perspective view of a package showing a second embodiment of the invention. In addition, in the figure, 1...notch part, 2...bottom of river/notch part, 3...1st terminal, 4...
・No. 1 terminal part (a) (b)

Claims (1)

【特許請求の範囲】[Claims] パッケージ外周辺の一部に切欠部が設けられた半導体装
置において、該切欠部に印刷による記号が設けられてい
ることを特徴とする半導体装置。1. A semiconductor device including a notch in a part of the outer periphery of a package, wherein the notch is provided with a printed symbol.
JP58068634A 1983-04-19 1983-04-19 Semiconductor device Pending JPS58197752A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58068634A JPS58197752A (en) 1983-04-19 1983-04-19 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58068634A JPS58197752A (en) 1983-04-19 1983-04-19 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS58197752A true JPS58197752A (en) 1983-11-17

Family

ID=13379362

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58068634A Pending JPS58197752A (en) 1983-04-19 1983-04-19 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS58197752A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5749393U (en) * 1981-01-23 1982-03-19

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5749393U (en) * 1981-01-23 1982-03-19

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