JPS5818929A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

Info

Publication number
JPS5818929A
JPS5818929A JP11694881A JP11694881A JPS5818929A JP S5818929 A JPS5818929 A JP S5818929A JP 11694881 A JP11694881 A JP 11694881A JP 11694881 A JP11694881 A JP 11694881A JP S5818929 A JPS5818929 A JP S5818929A
Authority
JP
Japan
Prior art keywords
heat treatment
hours
semiconductor device
denuded zone
temperature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11694881A
Other languages
English (en)
Japanese (ja)
Other versions
JPS639745B2 (enrdf_load_stackoverflow
Inventor
Koichiro Honda
耕一郎 本田
Akira Osawa
大沢　昭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP11694881A priority Critical patent/JPS5818929A/ja
Publication of JPS5818929A publication Critical patent/JPS5818929A/ja
Publication of JPS639745B2 publication Critical patent/JPS639745B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
JP11694881A 1981-07-24 1981-07-24 半導体装置の製造方法 Granted JPS5818929A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11694881A JPS5818929A (ja) 1981-07-24 1981-07-24 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11694881A JPS5818929A (ja) 1981-07-24 1981-07-24 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPS5818929A true JPS5818929A (ja) 1983-02-03
JPS639745B2 JPS639745B2 (enrdf_load_stackoverflow) 1988-03-01

Family

ID=14699689

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11694881A Granted JPS5818929A (ja) 1981-07-24 1981-07-24 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPS5818929A (enrdf_load_stackoverflow)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4505759A (en) * 1983-12-19 1985-03-19 Mara William C O Method for making a conductive silicon substrate by heat treatment of oxygenated and lightly doped silicon single crystals
US5506178A (en) * 1992-12-25 1996-04-09 Sony Corporation Process for forming gate silicon oxide film for MOS transistors
WO2002049091A1 (fr) 2000-12-13 2002-06-20 Shin-Etsu Handotai Co., Ltd. Procede de fabrication d'une tranche de recuit et tranche obtenue
JP2003068743A (ja) * 2001-08-23 2003-03-07 Shin Etsu Handotai Co Ltd エピタキシャルウエーハおよびその製造方法
US7081422B2 (en) 2000-12-13 2006-07-25 Shin-Etsu Handotai Co., Ltd. Manufacturing process for annealed wafer and annealed wafer
JP2015164179A (ja) * 2014-01-29 2015-09-10 三菱マテリアル株式会社 プラズマ処理装置用電極板及びその製造方法

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4505759A (en) * 1983-12-19 1985-03-19 Mara William C O Method for making a conductive silicon substrate by heat treatment of oxygenated and lightly doped silicon single crystals
US5506178A (en) * 1992-12-25 1996-04-09 Sony Corporation Process for forming gate silicon oxide film for MOS transistors
WO2002049091A1 (fr) 2000-12-13 2002-06-20 Shin-Etsu Handotai Co., Ltd. Procede de fabrication d'une tranche de recuit et tranche obtenue
JP2002184779A (ja) * 2000-12-13 2002-06-28 Shin Etsu Handotai Co Ltd アニールウェーハの製造方法及びアニールウェーハ
US7081422B2 (en) 2000-12-13 2006-07-25 Shin-Etsu Handotai Co., Ltd. Manufacturing process for annealed wafer and annealed wafer
EP1343200A4 (en) * 2000-12-13 2007-09-12 Shinetsu Handotai Kk METHOD FOR MANUFACTURING A RECTANGULAR WAFER AND WAFER OBTAINED
KR100847925B1 (ko) 2000-12-13 2008-07-22 신에츠 한도타이 가부시키가이샤 어닐웨이퍼의 제조방법 및 어닐웨이퍼
JP2003068743A (ja) * 2001-08-23 2003-03-07 Shin Etsu Handotai Co Ltd エピタキシャルウエーハおよびその製造方法
JP2015164179A (ja) * 2014-01-29 2015-09-10 三菱マテリアル株式会社 プラズマ処理装置用電極板及びその製造方法

Also Published As

Publication number Publication date
JPS639745B2 (enrdf_load_stackoverflow) 1988-03-01

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