JPS58188952A - パラレル・シリアル・デ−タ伝送回路 - Google Patents

パラレル・シリアル・デ−タ伝送回路

Info

Publication number
JPS58188952A
JPS58188952A JP57072345A JP7234582A JPS58188952A JP S58188952 A JPS58188952 A JP S58188952A JP 57072345 A JP57072345 A JP 57072345A JP 7234582 A JP7234582 A JP 7234582A JP S58188952 A JPS58188952 A JP S58188952A
Authority
JP
Japan
Prior art keywords
clock
shift
signal
circuit
serial data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57072345A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0153821B2 (enrdf_load_stackoverflow
Inventor
Kenzo Ishiguro
石黒 健三
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hewlett Packard Japan Inc
Original Assignee
Yokogawa Hewlett Packard Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yokogawa Hewlett Packard Ltd filed Critical Yokogawa Hewlett Packard Ltd
Priority to JP57072345A priority Critical patent/JPS58188952A/ja
Publication of JPS58188952A publication Critical patent/JPS58188952A/ja
Publication of JPH0153821B2 publication Critical patent/JPH0153821B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/38Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40Transmitting circuits; Receiving circuits
    • H04L25/45Transmitting circuits; Receiving circuits using electronic distributors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Communication Control (AREA)
JP57072345A 1982-04-28 1982-04-28 パラレル・シリアル・デ−タ伝送回路 Granted JPS58188952A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57072345A JPS58188952A (ja) 1982-04-28 1982-04-28 パラレル・シリアル・デ−タ伝送回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57072345A JPS58188952A (ja) 1982-04-28 1982-04-28 パラレル・シリアル・デ−タ伝送回路

Publications (2)

Publication Number Publication Date
JPS58188952A true JPS58188952A (ja) 1983-11-04
JPH0153821B2 JPH0153821B2 (enrdf_load_stackoverflow) 1989-11-15

Family

ID=13486619

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57072345A Granted JPS58188952A (ja) 1982-04-28 1982-04-28 パラレル・シリアル・デ−タ伝送回路

Country Status (1)

Country Link
JP (1) JPS58188952A (enrdf_load_stackoverflow)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61105936A (ja) * 1984-10-30 1986-05-24 Sony Corp 調歩同期式デ−タ伝送システム
JPS6388601A (ja) * 1986-10-01 1988-04-19 Mitsubishi Electric Corp シ−ケンスコントロ−ラの位置決めユニツト

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61105936A (ja) * 1984-10-30 1986-05-24 Sony Corp 調歩同期式デ−タ伝送システム
JPS6388601A (ja) * 1986-10-01 1988-04-19 Mitsubishi Electric Corp シ−ケンスコントロ−ラの位置決めユニツト

Also Published As

Publication number Publication date
JPH0153821B2 (enrdf_load_stackoverflow) 1989-11-15

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