JPS58188135A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS58188135A
JPS58188135A JP57073160A JP7316082A JPS58188135A JP S58188135 A JPS58188135 A JP S58188135A JP 57073160 A JP57073160 A JP 57073160A JP 7316082 A JP7316082 A JP 7316082A JP S58188135 A JPS58188135 A JP S58188135A
Authority
JP
Japan
Prior art keywords
substrate
electrode
film
mask
bar
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57073160A
Other languages
Japanese (ja)
Inventor
Haruo Shimamoto
晴夫 島本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP57073160A priority Critical patent/JPS58188135A/en
Publication of JPS58188135A publication Critical patent/JPS58188135A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To make the gaps between connected semiconductor elements and substrate even by a method wherein the bar-like electrode are formed on the substrate. CONSTITUTION:Cu 6 is evaporated on a ceramic substrate 1 to perform patterning by means of placing Cr, Ti evaporated film 7 thereupon coating the film 7 with a resist thick film 8 to form the holes 9. Then the bar-like electrodes 9 are formed by means of etching the metallic film using the mask 8 as well as Cu plating. Next the mask 8 is removed etching the Cu layer 6 utilizing the metallic layer 7 as a mask to complete said Cu layer 6. When a semiconductor element with solder projected electrode is connected to the substrate in this constitution, the mutual gaps may be decided evenly by the height of said bar- like electrode 9 making dispersion of the gaps due to the difference in the wetness of solder and in the height of said projected electrode even to prevent the defective junction or the stress concentration improving the reliability.

Description

【発明の詳細な説明】 この発明は、＋導体装置、特に７リツプチツプ半導体素
子のボンディング用絶縁基板の構造に関するものである
。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a positive conductor device, particularly to the structure of an insulating substrate for bonding a 7-lip chip semiconductor device.

従来この種の半導体装置として第１図に示すものがあつ
友。図において（１）は絶縁基板（セラミック基板）で
、（２）は上記セラミック基板上に形成された配線で、
（３）は半田の流れ止め用ダムである。The conventional semiconductor device of this type is the one shown in FIG. In the figure, (1) is an insulating substrate (ceramic substrate), (2) is the wiring formed on the ceramic substrate,
(3) is a dam for stopping the flow of solder.

（４）は上記基板上に搭載する半導体チップ、（５）は
上記半導体チップ上に形成された半田の突起［ＦＭであ
る。上記配線（２）及び半田ダム（３）は、スクリーン
印刷によってセラミック基板上に形成する。(4) is a semiconductor chip mounted on the substrate, and (5) is a solder protrusion [FM] formed on the semiconductor chip. The wiring (2) and solder dam (3) are formed on the ceramic substrate by screen printing.

突起＊　ｔｍ　（ｂｌを形成し九半導体素子（４）を、
突起電極をセラきツク基板上の配線上に接合するため位
置合せな行い仮付けしＩＪ　７　ｃＩ−によって半導体
素子のセラミック基板へのボンディングを行う、この際
に、突起ｌｔ極の構成物である半田の配線上への流れ止
めとして、ガラスコート（３）を配線上に施す。Protrusion * tm (forming bl and nine semiconductor elements (4),
In order to bond the protruding electrode to the wiring on the ceramic substrate, align it and temporarily attach it, and then bond the semiconductor element to the ceramic substrate using IJ 7 cI-. A glass coat (3) is applied to the wiring to prevent solder from flowing onto the wiring.

従来の半導体装置は、以上のように構成されているので
、上記半導体素子と基板とのボンディングの際に、半導
体素子上の突起ＷｌＦＭの高さにバラツキがあると半導
体チップと基板間の間隔が不均一となり、接合部のある
部分に応力が集中し、その結果としてその部分の突起電
極の破断をもたらし、電気的にオープンとなってしまう
。また、突起電極の高さが低くすぎて、セラミック基板
上の配線と接合されてない場合も発生する丸め、信頼性
を大きく低下させるなどの欠点があつ九・この発明は、
上記のような欠点な除去するもので、基板上に棒状電極
を形成することによって。Since the conventional semiconductor device is configured as described above, when the semiconductor element and the substrate are bonded, if there is a variation in the height of the protrusion WlFM on the semiconductor element, the gap between the semiconductor chip and the substrate may be increased. This results in non-uniformity, and stress concentrates on a certain part of the joint, resulting in breakage of the protruding electrode in that part, resulting in an electrical open. In addition, there are drawbacks such as rounding that occurs when the height of the protruding electrode is too low and is not bonded to the wiring on the ceramic substrate, which greatly reduces reliability.
By forming rod-shaped electrodes on the substrate, the above drawbacks are eliminated.

半導体素子とセラミック基板とのボンディング後の間隔
な均一にすることを目的としている。The purpose is to make the distance between the semiconductor element and the ceramic substrate uniform after bonding.

以下、この発明の一実施例を図について説明する。第２
図において（６）は、セラミック基板（１）上に形成さ
れる配線となる金属層で、ここではＣｕｆ用いてお９基
板全面に蒸着した。上記金属層上に半田の流れ止めとな
る金属（７）、九とえばＣｒ、Ｔｉな蒸着し、必要な配
線部分のみを写真制版で残し、エツチングによシバター
ニングを行った上記上うＺツク基板上にドライフィルム
のような厚膜レジスト（８）を塗布し、棒状電極（９）
を形成する部分のみを写真制版で穴あけな行う。このレ
ジスト（８）をマスクに上層の金属層（７）をエツチン
グし、下層金属層（６）を露出させる。次にこの下層金
属層（６）な電極にして、レジスト（８）で囲まれた空
所にＣｕメッキで棒状電極（９）を形成する。この後、
レジスト（８）を除去し、下Ｊ−金属層（６）を金属層
（７）？マスクにエツチングで除去した基板が第３図で
ある。下層金属層でめるＣｕをエツチングする際に、棒
状１を極もエツチングされるが、膜厚が全く違うため問
題はない。An embodiment of the present invention will be described below with reference to the drawings. Second
In the figure, (6) is a metal layer that will become wiring formed on the ceramic substrate (1), and here it was deposited on the entire surface of the nine substrates using CUF. A metal (7), such as Cr or Ti, which serves as a stopper for solder flow, is vapor-deposited on the metal layer, and only the necessary wiring portions are left by photolithography, and patterned by etching. A thick film resist (8) like a dry film is applied on the substrate, and a rod-shaped electrode (9) is applied.
Drill only the part that will form the hole using a photo printing plate. Using this resist (8) as a mask, the upper metal layer (7) is etched to expose the lower metal layer (6). Next, using this lower metal layer (6) as an electrode, a rod-shaped electrode (9) is formed by Cu plating in the void surrounded by the resist (8). After this,
Remove the resist (8) and replace the lower J-metal layer (6) with the metal layer (7)? FIG. 3 shows the substrate removed by etching into the mask. When etching the Cu in the lower metal layer, the poles of the rods 1 are also etched, but there is no problem because the film thicknesses are completely different.

以上のように構成されたセラミック基板上に。on a ceramic substrate configured as described above.

半田からなる突起電極をもった半導体素子をボンディン
グすると、半導体素子と基板間の間隔は、棒状電極の高
さで均一に決まってしまい、半田のぬれ性の違い及び突
起電極の高さの違いから生ずるチップ−基板間の間隔の
バラツキを抑えることが出来る。When bonding a semiconductor element with protruding electrodes made of solder, the distance between the semiconductor element and the substrate is determined uniformly by the height of the rod-shaped electrode, and due to differences in solder wettability and differences in the height of the protruding electrodes. Variations in the chip-to-substrate spacing that occur can be suppressed.

上記実施例では、半導体素子を搭載したが、チップ部品
を搭載することにより基板上への高密度寮装が可能とな
る。In the above embodiments, semiconductor elements are mounted, but high-density dormitory equipment can be mounted on the board by mounting chip parts.

以上のように、この発明によればセラミック基板上に棒
状電極を形成したため、半導体素子ボンディング後の基
板とチップの間隔が一定となり、ボンディング不良及び
応力集中がなくなり、信頼性が改善される。又、棒状電
極にＣｕ　ｆ用いることによって半導体素子からの放熱
が良くなり％熱抵抗が減少する。As described above, according to the present invention, since the rod-shaped electrode is formed on the ceramic substrate, the distance between the substrate and the chip after semiconductor element bonding becomes constant, bonding defects and stress concentration are eliminated, and reliability is improved. Furthermore, by using Cu f for the rod-shaped electrode, heat radiation from the semiconductor element is improved and the percent thermal resistance is reduced.

【図面の簡単な説明】[Brief explanation of drawings]

Ｍｇ１図は、従来の半導体装置の一例な示すＩＩＴ面゛
図、第２図及び第３図は、この発明の一実施例によるフ
リップチップ用基板を示す断面図でるる。 （旧・・セラミック基板、（２）・・・配Ｍｉ３）・・
・ガラスコ）　ｓ　（’）・・・半導体チップ、（５）
・・・突起１１Ｃｆｆｌ　、　（ａ）　、　（７）・・
・金属ｊ＠、Ｃ８）・・・レジス）　、（９）・・・棒
状電極。 なお図中、同一符号は、同−又は相幽部分な示す。 代理人　葛野信− 第１図 第２図 第３図 ７・９ 手続補正書（自発） 持＋ｉ’ｌ’　Ｉ’ｄ’長官殿 １、　　’ＩＣＩ’ｌのノ（＋ｊ’＋　　　　　　特願
昭　６７−丁８１６０　号２　づ６明の名ｆろ、 半導体装置 、（補１１．を・遣ると ４ｃｆ’ｌ・との関係　　　特許出願人住　所　　　　
　東京都ｆ−代ｒ＋を区丸の内二丁目２番３号名　称ｆ
６０１１　　　三菱電機株式会社代表者片山仁八部 １、代理人 ｆ１′、所　　　　　東京都千代１１１区丸の内二Ｊ’
１−１２番３シ）５、補正の対象 明細書の発明の詳細な説明の欄 ６、　　＠正の内容 明細書をつぎのとおり訂正する。FIG. 1 is an IIT plane view showing an example of a conventional semiconductor device, and FIGS. 2 and 3 are cross-sectional views showing a flip-chip substrate according to an embodiment of the present invention. (Old...Ceramic board, (2)...Mi3)...
・Glasco) s (')...Semiconductor chip, (5)
...Protrusion 11Cffl, (a), (7)...
・Metal j@, C8)... Regis), (9)... Rod-shaped electrode. In the drawings, the same reference numerals indicate the same or different parts. Agent Makoto Kuzuno - Figure 1 Figure 2 Figure 3 Figures 7 and 9 Procedural amendment (spontaneous) Mochi + i'l'I'd' Director-General 1, 'ICI'l no (+j' + Patent application 1986) - No. 8160 No. 2 6 Akira's name fro, Semiconductor device, (Relationship with 4cf'l when Supplement 11. is used. Address of patent applicant.
2-2-3 Marunouchi, Tokyo
6011 Mitsubishi Electric Co., Ltd. Representative: Hitoshi Katayama 8be 1, Agent f1', Address: Marunouchi 2J', 111-ku, Chiyo, Tokyo
1-12 No. 3 C) 5. Column 6 of the detailed description of the invention in the specification to be amended, @correct description of contents is corrected as follows.

Claims (3)

【特許請求の範囲】[Claims] （１）半導体素子を搭載する絶縁基板上に、上記亭導体
素子上に形成された突起電極部と同位置に棒状電極を形
成し、上記半導体素子をフェースダウンでボンディング
した際に上記突起電極と棒状電極との接合によシミ気的
接続な得ることを特徴とする半導体装置。(1) A rod-shaped electrode is formed on the insulating substrate on which the semiconductor element is mounted at the same position as the protruding electrode part formed on the bow conductor element, and when the semiconductor element is bonded face-down, the protruding electrode and A semiconductor device characterized in that an air-tight connection is obtained by joining with a rod-shaped electrode. （２）上記棒状電極によって半導体素子と上記絶縁基板
との間隔を一定に保持したことを特徴とする特許請求の
範囲第１項記載の半導体装置。(2) The semiconductor device according to claim 1, wherein the distance between the semiconductor element and the insulating substrate is maintained constant by the rod-shaped electrode. （３）上記棒状電極なＣｕによって構成したことな特徴
とする特許請求の範囲第１項記載の半導体装置。(3) The semiconductor device according to claim 1, wherein the rod-shaped electrode is made of Cu.
JP57073160A 1982-04-27 1982-04-27 Semiconductor device Pending JPS58188135A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57073160A JPS58188135A (en) 1982-04-27 1982-04-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57073160A JPS58188135A (en) 1982-04-27 1982-04-27 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS58188135A true JPS58188135A (en) 1983-11-02

Family

ID=13510136

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57073160A Pending JPS58188135A (en) 1982-04-27 1982-04-27 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS58188135A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03133138A (en) * 1989-10-19 1991-06-06 Ngk Spark Plug Co Ltd Manufacture of bump of package for integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03133138A (en) * 1989-10-19 1991-06-06 Ngk Spark Plug Co Ltd Manufacture of bump of package for integrated circuit

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