JPS58186863A - Data system selecting circuit - Google Patents

Abstract

PURPOSE:To decrease the number of input/output terminals of integrated circuits greatly, by transferring outputs from circuit group input/output data buses to a memory bank through a data driver and also supplying it to a CPU through an output switching and selecting circuit. CONSTITUTION:Input switching and selecting circuits 4-1 and 4-2 have one-side inputs connected to memory banks 2-1, 2-2-2-4 and the other-side inputs connected to a data bus 100 from the CPU1 which use plural memory banks. The circuits 4-1 and 4-2 send selected memory banks to integrated circuits 3-1, 3-2- 3-4 through circuit group input/output data buses 30-1 and 30-2. The outputs of the integrated circuits, on the other hand, are sent to the banks 2-1-2-4 through the circuit group bus and data drivers 6-1 and 6-2 and also transferred to the CPU1 through the output switching and selecting circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data system selection circuit, and particularly to a selection circuit in a data transfer thread between a central processing unit of an information processing device and a memory section in a memory device.

In general VC1 information processing equipment, the central processing unit (C
Transfer of takes between the PU) and a memory device having an error correction function is performed via one data control path. That is, for example, when a CPU stores data into a memory section consisting of a plurality of memory elements and their peripheral circuits, the data is generally first transferred to a data control circuit, and then converted into data in that circuit. After all error correction check pits are added, this data is stored in the specified memory address.

1. Even when reading data from the added memory address, this data is first read to the data control circuit, the necessary error correction is performed there, and then the CP '
Transfer to U.

Furthermore, in a storage device that performs error correction, when the CPU rewrites all bytes of a word at a certain memory address (performs partial convolution), the entire word is once rewritten from this memory address. The data is read into the data control integrated circuit, where the added byte portion is replaced and the necessary error correction check pits are updated, and then stored at the old memory address.

As mentioned above, data is generally exchanged between the C'PU and the memory section via a data control circuit, and
Recently, this data control circuit has been widely used in large-scale integrated circuits (L
SI).

Now, in the FIT memory and 匝 which performs interleaving with the CPU, the data transfer of the song between the data control integrated circuit and the memory section is carried out by a two-pronged connection similar to that of a Geropi.

That is, the memory section in which the interleaving operation 1-r is performed is as follows.
In general, the memory is divided into a plurality of memory banks, each of which is assigned a part of an address, and a collection circuit for data control 11 is provided corresponding to each memory bank.

In this data control integrated circuit, each integrated circuit has a data input/output interface (input/output pin) for the corresponding memory bank side, and a data input/output interface for the CPU side, each with its own dedicated input/output interface. has been established. This results in
While one data control integrated circuit is transferring data to and from the CPU, another data control integrated circuit is communicating with the corresponding memory bank using a dedicated interface. In parallel with this, data can be exchanged. In this way, a decrease in efficiency due to input/output data contention in the data control integrated circuit is prevented.

However, on the other hand, this configuration
11 (1) This has the drawback of increasing the number of pins in the data interface of the III circuit, making it difficult to integrate it into an LSI.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data system selection circuit which eliminates the above-mentioned conventional drawbacks.

Each uninvented circuit shares a data input line and a data output line? Jlj memory bank, a plurality of data control integrated circuits provided corresponding to each of the plurality of memory banks, each of which shares a data input line and a data output line, and each of the plurality of integrated circuits. (b) Integration that belongs to the same group in multiple integrated circuit groups consisting of
a plurality of circuit group input/output data buses configured by sharing the data input line and the data output image of the circuit;
10,000 inputs are connected to the data outputs from said memory banks, and the other input is connected to a data bus connected to a central processing unit using the previously distributed number of memory banks, and any part of these inputs a plurality of input switching selection means provided corresponding to these circuit groups so as to connect the selected output to the input/output data bus of the circuit group including the integrated circuit corresponding to the memory bank;
Output switching selection means for switching and selecting one of the outputs of the plurality of circuit group input/output data buses and connecting it to the data bus connected to the processing device; and outputs from the circuit group input/output data bus. to the memory banks corresponding to the integrated circuits associated with this group.

The present invention will now be described in detail with reference to all the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

This embodiment includes a central processing unit (CPU) 1, and four memory banks 2-1 to 2-1 that share data input lines and output lines.
2-4. Four data control integrated circuits 3-1 to 3-4, 6 are provided for each memory bank and share data input lines and data output lines. -2 is the first integrated circuit group and is configured by connecting it to the shared ^↑1 TED output line Kinsobe/First circuit group input/output data bus 30-1. Further, the axle collector circuits 3-3 and 3-4 are set as a 20th axle collector circuit group.

A second circuit group input/output data bus 30-2 configured by interconnecting the shared data input/output lines of integrated circuits 3-3 and 3-4 belonging to this group. Each circuit group input/output data bus 30-1 and 30-
2, the output from the aforementioned memory bank 1 is supplied as an input, and the output of the CPU data bus 100 from the CPU that uses this memory bank is supplied as the other input. Input switching selection circuits 4-1 and 4-2 which switch and select one of the two supplied inputs and output it to the corresponding circuit group input/output data bus 3O-It or 30-2. an output switching selection circuit that selects one of the circuit group input/output data buses 30-1 and 30-2 and outputs the selected signal to the CPU data bus 100;5. and a data driver provided in contrast to each of the circuit group input/output data buses 30-1 and 30-2 for transferring output from each input/output data bus 30-1 or 30-2 to all memory banks. 6-1 and 6-2 (r'N).

As mentioned above, the data control integrated circuits 3-1 to 3-4 and the memory banks 2-1 to 2-4 all input and output data through a common input/output data interface,
This allows for a significant reduction in the number of bins in the main tough ace.

Now, the data write operation from the CPUI to the memory bank is as follows.

The CPU designates the memory address to be filled in and the fact that the current operation is a filling operation for a memory bank to a control unit (not shown), and outputs the color data to be filled in to the data bus 100. .

As a result, the front i-pi control unit generates volume control information based on the specified 1゛H information, and selects the memory banks 2-1 to 2-4 and selects the necessary control information tones, respectively. 1st road 4-1
~4-2, the data control integrated circuits 3-1 to 3-4 are supplied to the drivers 6-1, 6-2, and the selection circuit 5, and are controlled to perform the write operation as described below.

First, if the specified memory address is included in the memory bank 2-1, the control tV4 information indicates the circuit group to which the corresponding integrated circuit 3-1 is connected. A selection circuit 4-1 corresponding to the input/output data bus 30-1 selects the inputs on the CPU data bus 100 side and performs control to output all of them. Along with that,
The control information controls 1 so that the integrated circuit 3-1 performs an operation regarding data 1 included. That is, first, #1iiielOl viewed from the output side of the data selection circuit 4-1.
The integrated circuit 3-
1 and 3-2 k tlfll (wholesale, and also rapeseed circuit 3-1 selects circuit 4- from @ki CPU bus 100)
1. Take in the data transferred via the input/output data bus 30-1', and process this data 9 in the internal circuit.
- A check pit for correcting error 9 is added to the data, and this data is output to the same input/output data path 30-1 after a predetermined time has elapsed. At this point, according to the control information, the output of the selection circuit 4-1 is 1ft! + is controlled to have high impedance.

In this way, the section p is transferred to the input/output data bus 30-1.
The drafting data with correction check pits added is data driver 6-1'! Memory bank 2-I through
Transferred to II+.

The memory bank 2-1 side is controlled to the data convolution state by the control tTf information. That is, memory bank 2-
The input impedances of 1 and 2-2 are controlled to be high impedance, and the memory bank 2-1 stores the transferred write data at a memory address added by +'ti. In this way, the data from the CPUI is added with the necessary error correction check pits in the integrated circuit 3-1, and is inserted into the memory address created in the memory bank 2-10. Is the CPU data from a specific memory address in bank 2-1? The operation for drinking is as follows.

The CPUI is l! 4Vs is determined to be the memory address of the data to be downloaded and the current operation is a read operation from the memory bank 2-1.

Accordingly, in the same manner as described above, the control section 1 also performs the control section 11 for data starvation based on the specified information.
! It generates information, supplies the necessary control information to each circuit, and controls it to carry out the trajectory operation that can be transmitted to the following.

First, these control IH information are supplied to the memory bank,
The memory bank 2-1 included in the designated memory address is controlled to perform the data exposure operation. Thus,
The data at the specified memory address is 1. However, at this point, the driver 6-1 and memory bank 2-2 are controlled to have an output impedance of 1.

-10,000 sfJ'jlii self-control t*especially good trace selection circuit 4-
1 selects all inputs of memory bank 1 and outputs them to all input/output data buses 30-1. In this way, the data read from the specified memory address appears on the data input/output interface of the integrated circuit 3-1 (at this point, the data read out from the specified memory address appears on the data input/output interface of the integrated circuit 3-1 and 3-2).
is controlled to become a high human-powered impedance).

Now, the control information is given to the integrated circuit 3-1, whereby the circuit 3-1 performs a data read operation.

In other words, when the data appearing on the input/output data interface is internally imported, and the data is not completely error-proof, and the data is not fully corrected in advance.
1, this data is output to the input/output data bus 30-1. At this point, the output impedance of the selection circuit 4-1 is controlled to be high impedance according to the previous line control information.

In this way, the output from integrated circuit 3-1 is
The control information appearing at the input terminal of the selection circuit 5 through the input data path 3O-1i and being supplied to the circuit 5 causes the circuit 5 to correspond 2-1 to the memory bank containing the specified memory address. The output of the human output data path 30-1 connected to the integrated circuit 3-1 is
Output to U data bus 100. Of course, at this point, the CPUI side of the data bus 100 is in high impedance and is controlled to be in a data input state.

Thus, C) 'Ul reads out the data at the specified memory address from the memory bank 2-1, collects it, and performs the process 3-
After performing the necessary deviation correction in step 1, this can be imported.

The above is an explanation of a normal one-write operation and a normal emptying operation for a specific memory address, but when performing the above-mentioned partial write, the process is as follows.

The CPU informs the previous DPI control unit of the memory address at which the partial write should be performed, the byte position within this memory address where the partial write should be performed, and that the operation at the boundary is a partial convolution operation. Partial write data for performing partial writing is sent onto the IrCPU data bus 13-100.

As a result, the control h+ from the control part 1! According to the information, the selection circuit 4-1 corresponding to the memory bank 2-1 (which is tentatively added to the memory bank 2-1) containing the specified memory address is configured to select the CP[J Catabus 100'jk]. The partially convolved data on the Fm gtj bus 100 is sent to the input/output data bus 30-1 including the fully integrated circuit 3-1.

The integrated circuit 3-1 takes in this data and holds it therein.

Part of the data at the memory address specified by the control information is extracted from the memory bank 2-1, but the corresponding selection circuit 4-1 previously selected the partial write data to the integrated circuit 3-1. When the transfer is done, the CPU data bus 10
0 and controlled 1 to select this output of memory bank 2-19111. Thus, the data read from the memory bank 2-1 appears on the input/output data bus 30-1 and is internally taken in by the integrated circuit 3-1.

14- Inside the integrated circuit 3-1, the memory backup 2-
The error 9 correction of the 9 data read from 1 is performed, and then the byte portion specified by the control information in this error-corrected data is transferred from the CPUI and is stored in the corresponding part of the partial write data. It is possible to increase m by part-time job. Necessary error correction check bits are added to the newly generated partial replacement data, and the data is output to the input/output data bus 30-1 after a predetermined period of time has elapsed. After this, this partial replacement data is stored in the specified memory address of memory bank 2-1 in exactly the same manner as already explained in the normal convolution operation, and the partial write operation is completed. As mentioned above, if there are 4 unimplemented circuits, C will be used as the input/output data interface of the data control collector circuit.
The input/output data interface to the PU side and the input/output data interface to the memory bank side can all be processed using a common data interface. For this reason, the data interface multiplication circuit, which is an integrated circuit for data control, uses a circuit group input/output data basket, which is configured by grouping two circuits and connecting the human output data interfaces of the same group in common. Since it is connected to a selection circuit, it is possible to reduce the number of selection circuits and save other hardware.

゛In the above embodiment, the input/output data bus was constructed by grouping one data control 1'4'' l-th root circuit 21, but if the number of data control integrated circuits is large, two Input switching selection by grouping the above
The number of PL paths and other hardware can be further reduced.

In this way, increasing the number of data management circuits in the same group will result in a corresponding reduction in hardware, but will also increase the probability that data conflicts will occur on some circuit group input/output data buses. It gets expensive.

Therefore, by appropriately selecting this number, it is possible to find an appropriate compromise between data contention and hardware savings depending on the scale of the device.

Now, finally, the details of the data control integrated circuits 3-1 to 3-4 (hereinafter referred to as rapeseed circuit 3) used in the above d-pi embodiment will be explained.

FIG. 2 is a diagram 9 showing a circuit example of this integrated circuit 3.

This output circuit 3 has an input/output data interface for the CPU side, an input/output data interface for the memory bank 1, and an input/output data interface 30 that is common to all. This interface 30 includes
A data receiver 301 is connected for data input, and a data driver 302 is connected for data output.
It is enabled/disabled by the sub-side 1 signal from the control unit via 020'i, and is set to fell ml so that the interface 30 can be commonly used for either data input or data output. Inside, there are a starting data register 303, a check bit register 17-304, and an output register 309f, as well as a selector 305, check bit/syndrome generation (ro)
Th306, Tecode circuit 307 and error correction circuit 3
Contains 08.

Now, the operation of the integrated circuit 3 in the case of data loading from the CPU to the memory bank as described in @ is as described below.

Once the write data from the CPUI is transferred and appears on the interface 30, the control f! With the control information supplied from A, the data driver 3
02 is disabled and has a high output impedance, the data receiver 301 is enabled and the transferred data is stored in the committed data register 304. Then, the selector 305 receives the control signal 30 from the front 81 control section.
50 causes i to select the output of register 304.
Under the control σ, the convolution data selected by this selector 305 is -V qubits/syndrome occurrence p1
The circuit 306 is supplied to the circuit 306, and the circuit 308 is connected to the circuit 308.
is supplied to

18- When the circuit 306 is supplied with a control signal specifying the sinking state from the control unit via the control line 3060,
A check bit for error correction is generated for the supplied convolution data. This check pit is stored in a field for storing an error correction check pit (k) of the output register 309. - 10,000, the code circuit 307 does not produce any output even if this check pin is supplied, and therefore the convolution data supplied to the error correction circuit 308 is not corrected in the circuit 308 and is stored in the output register 309. Stored in Cheetah Field.

Next, the driver 302 is enabled by the control information supplied from the ffl control unit, and the 1-input data stored in the output register 309 and the corresponding error correction check and qubit are connected to the data interface in parallel. 3
0, and this is the aforementioned 1 for the memory bank.
The data will be included.

Also, the data from the aforementioned memory bank to the CPU
The operation of the integrated circuit 3 in the case of output is as follows.

At the time when the error correction check pit output data from the memory bank is transferred and appears on the interface 30, the input signal supplied from the control unit via the line 3020 is input to the driver 30.
2 is disabled to high output impedance.
The pre-accented data, which is $1 and extracted from the memory bank, is stored in the pre-accented data register 303 via the receiver 301.

Then, the selector 305 is controlled by the control information from the line 3050 to select the output of the register 303, and the escaped data selected by the selector 305 is generated in a check bit/syndrome and is passed through one path. 30
6 and surcharge discount-! It is dedicated to the road 308.

The circuit 306 is specified to be in the ω start state by the sub-side j information sent from the control unit via line 3 (16 (l).

The circuit 306 designated to be in the active state generates the syndrome based on the supplied read data including check pits for error correction, and supplies it to the code circuit 307 . Circuit 307 decodes this syndrome and generates an error correction bit. If there is no error in the escaped data, all 10#s are output as a syndrome, and as a result, no error correction bit appears in the output of the code circuit 307.

Now, from the cultivator 305, the f4i1 aem output data from which the error 91" pressure check pit has been removed is supplied to the pinning circuit 308, and here the error correction bit from the tecoding circuit 307 is applied to this data. Exclusive OR is performed and error 9 correction is performed. The bladder ejection data subjected to error correction in this way is stored in the output register 309, and then the driver 302 is enabled by the control 1ffl information supplied from the control section 1, and the ejected data is outputted to the outside via the interface 30. and is transferred to the CPUI as described above.

Finally, the operation of the integrated circuit 3 when performing the above-mentioned partial write is as follows: First, when the partial convolution data from the CPUI is transferred 21- and appears on the interface 30, the data supplied from the control section is Due to the control information, this partial write data is held in the convolution data register 304 by a margin A1, which is different from the case of the data write described above.

Next, when data to be partially written from the memory bank (partially written data) is bounded by the interface 30, it is first stored in the indulgence data register 303, as in the case of data reading described above, and then the data is read out. This partially written data is corrected by exactly the same operation that was cleared by the operation of , and is output to the output register 309.
is stored in

Now, partial convolution is specified for the arrow selector 305 via the control line 3050, which causes the register 30
The byte data at the byte position designated for partial writing of the partial write data held in register 4 and register 3.
It is controlled to selectively combine all the byte data in the other byte positions of the partially written data which has undergone all the error correction stored in 09 and output it.

As a result, the output side of the selector 305 receives data that has been correctly partially replaced, but this data is
From this point on, the write data is handled in the same way as when writing data to the memory node mentioned above. In other words, when -000 is selected, check 5.
Tabi 1. is supplied to the t/syndrome generation circuit 306,
Here, an error check bit for correction is generated for this partially replaced data, and this is sent to the output register 3.
09 error correction check bit It & stored) (stored in /redo.) - 10,000, the partially replaced data is passed through the error correction circuit 308 (here, (i'1 etc. is not corrected) ) is stored in the data field of output register 309.

Then, the driver 30 is enabled by the control information supplied from the control section b, and the output register 30
The partially replaced data stored in 9 and the corresponding error correction check and y bits are output from the interface 30 in parallel, and these are stored in the specified memory address as described in 111, and the partial write operation is performed. Complete.

By using the above-mentioned data processing circuit,
Is the implementation not shown in Figure 1 above? 11 can be easily seen in the center.

As described above, by using the present invention, the number of pins in the input/output data interface of the data control integrated circuit can be significantly reduced, and the data A suitable compromise between data contention on the input/output data bus of the constraint 1 integrated circuit and hardware savings can be found.

This makes it possible to provide a flexible data system selection circuit having a data control circuit that can be implemented in large scale integration (LSI).

[Brief explanation of the drawing]

FIG. 1 is a block diagram illustrating the present invention, and FIG. 2 is a block diagram illustrating an example of a collecting circuit for data open side I used in a detailed example. In the figure, %1... River/Central processing unit (CPU), 2
-1~2-4...Memory bank, 3.3-1~
3-4... Data control integrated circuit, 4-1.4
-2・°°...Input switch @ selection circuit, 5...Output switching selection -1 path, 6-1.6-2...River/data driver, 3o...Group/input/output data interface, 30
-1...'1Jj1 circuit group people output data bus, 30-2...River, 2nd circuit group people output data bus, 301...Data receiver, 3o2...River...
Data driver, 3o3... Group/blasder output data register, 3o4... Song writing 7-ta L/Jister, 305...
...Selector, 3o6, old...Che, Tavi 1. 3o7...te code circuit, 308...error correction circuit, 3o9...group/output register. 25-

Claims (1)

[Scope of Claims] A plurality of memory banks, each of which shares a data input line and a data output line, and a plurality of memory banks provided corresponding to each of the mantissa memory banks, each of which shares a data input line and a data output line. A plurality of data control integrated circuits to be shared, and a plurality of integrated circuit groups each consisting of a plurality of the integrated circuits, in which the data input line and the data output line of the integrated circuits belonging to the same group are shared. f and a mantissa circuit group input/output data bus and a data bus having ten thousand inputs connected to data outputs from said memory banks and the other inputs connected to a central processing unit utilizing said plurality of memory banks. A mantissa input switch is provided corresponding to each of these circuit groups so as to connect any of these inputs to the selected output to the input/output data bus of the circuit group containing the integrated circuit corresponding to this memory bank. an output switching selection means for switching and selecting one of the outputs of the circuit group input/output data bus of the mantissa and connecting it to the data bus connected to the processing device; and the circuit group and means for transferring an output from an input/output data bus to the memory bank corresponding to the integrated circuit belonging to this group.