JP2000222294A - Computer system and bus fault recovering method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a computer system capable of maintaining stable operation against a bus fault without multiplexing a bus. SOLUTION: In the computer system mutually connecting plural modules 1, 2,..., (n) through a bus 12, a spare bus line 13 is prepared for substituting the fault line of the bus 12 and when the fault line of the bus 12 is detected, that fault line is switched to the spare bus line 13 for use. Since the fault line can be substituted for the unit of line just after the detection of fault while using the spare line 13, the computer system can be stably operated until recovery processing such as exchange of a fault spot is executed, and the high- reliability computer system can be provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a computer system configured by interconnecting a plurality of integrated circuits (modules) via a bus, and a bus failure recovery method.

[0002]

2. Description of the Related Art Conventionally, computer systems such as servers requiring reliability require an error correcting code (ECC) such as garbled bits of a signal flowing through a bus.
: Error correction code). Bit corruption detected on the bus is considered to be due to a failure in one of the lines that make up the bus, and it is common practice to stop the computer system early after the error is detected and start work on failure recovery such as replacing the failed part. Have been done.

However, the computer system is still operated in an unstable state until this bus failure recovery operation is performed. This can be said to be a problem that must be solved particularly in computer systems such as servers that require high reliability.

As a method for ensuring stable operation of a computer system in response to a bus failure, there is a bus multiplexing method using a plurality of buses having the same bit width. According to this, when a failure occurs in the main bus, the computer system can be maintained in a stable state even during a period in which the failure recovery work is performed by switching to the sub bus. However, when the bus is multiplexed, the scale of the computer system itself is greatly increased, and the cost is also greatly increased.

[0005]

As described above, conventionally, errors in data flowing through the bus can be corrected by ECC, but the system is operated in an unstable state with a bus failure. Continuing is dangerous. There is a bus multiplexing system as a method for solving this problem. However, in this method, the hardware scale is increased, and the cost is increased.

SUMMARY OF THE INVENTION The present invention has been made to solve such problems, and a computer system and a bus failure recovery method capable of maintaining stable operation against a bus failure without multiplexing the bus. It is intended to provide.

[0007]

According to one aspect of the present invention, there is provided a computer system comprising: a plurality of modules; a bus connecting the modules; and a fault line in the bus. A spare line that replaces the module, the module includes: a failure detection unit that detects a failure line in the bus; and when the failure detection unit detects a failure line, information of the failure line is transmitted to all of the modules. And a switching means for switching the detected faulty line to the spare line based on the faulty line information notified by the fault notifying means.

According to the present invention, a faulty bus can be replaced line by line using a spare line. Therefore,
To provide a computer system that can operate a computer system stably even before a failure recovery procedure such as replacement of a failure point is performed, and has the same reliability and an inexpensive computer system as a bus multiplex system. Can be.

A computer system according to a second aspect of the present invention has a plurality of modules, a bus connecting the modules, and a plurality of spare lines replacing a faulty line in the bus. A module configured to detect a failure line in the bus, a failure notification unit configured to notify information of the failure line to all the modules when the failure detection unit detects the failure line; Storage means capable of accumulating a plurality of pieces of information on the fault line notified by the means, and switching means for switching the fault line to the spare line based on the fault line information stored by the storage means. .

According to the present invention, when a plurality of faulty lines occur over different bus cycles, each faulty line can be replaced with a separate spare line. Therefore, the computer system can be operated stably even before a fault recovery procedure such as replacement of a fault location is performed, and a computer system that is superior in reliability and cheaper than a bus multiplex system is provided. can do.

The computer system according to the third aspect of the present invention has a plurality of modules, a bus connecting the modules, and a plurality of spare lines replacing a fault line in the bus. The module includes: an error detection and correction unit that performs error detection and error correction of data flowing through the bus alternately for each of a plurality of line groups configuring the bus; and an error is detected in a certain line group by the error detection and correction unit. A failure notifying unit for notifying information of the line in which the error has occurred to all of the modules; and a switching unit for switching the error line to the spare line based on the error line information notified by the failure notifying unit. It is characterized by the following.

According to the present invention, even when a plurality of faulty lines occur simultaneously on the bus, those faulty lines can be replaced with a plurality of spare lines. Therefore, the computer system can be operated stably even before a failure recovery procedure such as replacement of a failure point is performed, and a computer system having the same reliability and an inexpensive computer system as a bus multiplexing system is provided. can do.

[0013]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a diagram showing a configuration of a computer system according to the first embodiment of the present invention.

As shown in FIG. 1, each module 1, 2,..., N in the computer system has a bus 12 composed of at least m (where m is a multiple of 8) lines 12 and (m / m). 8) The spare bus lines 13 are connected to each other.

The module 1 includes a processor 14, a memory 15, a bus I / F 16, and a bus transceiver (Tr.) 1.
7, fault line information register (EL Reg.) 18,
A spare bus transceiver (S-Tr.) 19 is provided. Further, the bus I / F 16 has an ECC circuit (error detection / correction circuit) 20.

The bus transceiver 17 has a function of connecting the module 1 and the bus 12. The spare bus transceiver 19 has a function of connecting the module 1 and the spare bus line 13. The ECC circuit 20 performs error detection and error correction on m-bit data input from the bus 12 through the bus transceiver 17.

When the processor 14 detects a failure in the bus 12 based on the error detection result from the ECC circuit 20, the processor 14 sends information (failure line information) indicating which line of the bus 12 has caused the failure. .., N via the bus I / F 16 together with a command instructing to write information.

The configuration of the module 1 described above is the same for the other modules 2,..., N.

FIG. 2 shows the bus transceiver 17 and the spare bus transceiver 1 inside the module 1 shown in FIG.
9 is a diagram illustrating a specific bit configuration of No. 9; FIG.

As shown in FIG. 1, the spare bus transceiver (S-Tr.) 19 includes a fault line information register (E
L Reg. 3) an output selector 91 for selecting a signal to be output to the spare bus line 13 based on the fault line information held in 18, an amplifier 92 for amplifying the signal selected by the output selector 91, and the spare bus line 13.
The amplifier 93 amplifies the input signal. Data of bits other than the specific bit is input to the output selector 91 from the transceiver.

A bus transceiver (Tr.) 17 has an input selector 71 for selecting an input signal from the bus 12 and an input signal from the spare bus line 13 based on the fault line information held in the fault line information register 18.
An amplifier 72 amplifies an output signal to the bus line 12 and an amplifier 73 amplifies an input signal from the bus 12. The bus transceiver 17 is specifically provided for each individual bit line in the bus 12 as shown in FIG. 3 (71-1, 71-2,..., 71-n).

Next, the operation of the first embodiment will be described.

ECC in bus I / F 16 of module 1
The operation of the present embodiment will be described by taking as an example a case where a failure of the bus 12 is detected by the circuit 20.

The processor 14 in the module 1 has an ECC
Upon receiving an error detection signal from the circuit 20 and knowing that a failure has occurred in a line of a specific bit of the bus 12, information indicating the line in which the failure has occurred (line information of a specific bit indicating the occurrence of a failure) Is issued to all the modules 1, 2,..., N including itself, together with a command for writing this information to the fault line information register 18.

When all of the modules 1, 2,..., N connected to the bus 12 receive the fault line information and the command from the bus 12, they execute the command immediately. As a result, all modules 1, 2,
,..., The common fault line information is simultaneously written (in the same bus cycle) to the fault line information registers 18 in n.

In the following, in all the modules 1, 2,..., N, a switching process for replacing the faulty line with the spare bus line 13 based on the faulty line information held in the faulty line information register 18 is as follows. It is performed as follows.

In all the modules 1, 2,..., N, the information held in the fault line information register 18 is input to the output selector 91 in the spare bus transceiver 19. The output selector 91 switches the fault line of the bus 12 to the spare bus line 13 based on the input fault line information. Thereby, for example, module 1
Is output to the spare bus line 13 via the output selector 91 and the amplifier 92.

In all the modules 1, 2,..., N, the information held in the fault line information register 18 is also input to the input selector 71 in the bus transceiver 17. The input selector 71 performs switching so as to select an input from a line other than the fault line of the bus 12 and an input from the spare bus line 13 based on the input fault line information. Thus, for example, in the module 2, data of a specific bit input from the spare bus line 13 is input via the amplifier 93 and the input selector 71.

In this way, after the failed line information is written into the failed line information register 18, data transfer between modules using the spare bus line 13 is started from the next bus cycle.

In the above embodiment, even when data is transferred between modules using the spare bus line 13,
Error detection and error correction are normally performed by the ECC circuit 20 in the bus I / F 16. That is, the bus 12 including the spare bus line 13 is protected by the ECC circuit 20 as before.

Incidentally, it is needless to say that the bus for transferring the fault line information and the command for writing the fault line information to the fault line information register 18 is preferably a bus protected by the ECC circuit.

In the computer system according to the present embodiment,
In the case where the same bus fault is detected in a plurality of modules, only one module can issue fault line information and a command by bus arbitration. Other failure detection modules not given the right to use the bus cancel the command according to the bus specification.

As described above, according to the present embodiment, the line of the bus 12 in which a failure has occurred can be replaced line by line using the spare bus line 13 and immediately after the failure is detected. Therefore, the computer system can be operated stably even before recovery processing such as replacement of a faulty part is performed, and a highly reliable computer system can be provided. Further, according to the present embodiment, it is only necessary to prepare m / 8 spare bus lines 13 for the bus 12 composed of m lines, so that the circuit size and cost are lower than those of the bus multiplexing system. Has the advantage of being small.

Next, a computer system according to a second embodiment of the present invention will be described.

In the computer system of the present embodiment, two spare bus lines are prepared so as to cope with a case where a bus failure occurs in a different bus cycle.

FIG. 4 shows a specific bit configuration of the bus transceiver, the fault line information register, and the spare bus transceiver in the module of the computer system according to the present embodiment. As shown in the figure, each module is
A first spare bus transceiver 19a corresponding to the first spare bus line 13a, and a second spare bus line 1
3b corresponding to the second spare bus transceiver 19b
And a first fault line information register (EL) corresponding to each of the spare bus transceivers 19a and 19b.
Reg. 1) 18a and a second fault line information register (EL Reg. 2) 18b.

Each spare bus transceiver 19a, 19b
Are the corresponding fault line information registers 18a, 1
8b, output selectors 91a and 91b for selecting signals to be output to the corresponding spare bus lines 13a and 13b, based on the fault line information held in the output selector 91b.
a, an amplifier 9 for amplifying the signal selected by 91b
2a, 92b and the corresponding spare bus lines 13a, 1
Amplifiers 93a and 93 for amplifying the signal input from 3b
b. Data of bits other than the specific bit is input from the transceiver to the output selectors 91a and 91b. Each fault line information register 18a, 18
The output of b is introduced to the output selectors 91a and 91b in the corresponding spare bus transceivers 19a and 19b, and also to the input selector 71 in the bus transceiver 17.

Next, the operation of this embodiment will be described. The fault line information regarding the first bus fault is written to the first fault line information register 18a. The information held in the fault line information register 18a is input to an output selector 91a in the first spare bus transceiver 19a. The output selector 91a switches a faulty line of a specific bit of the bus 12 to the first spare bus line 13a and outputs data based on the input faulty line information. The information held in the first fault line information register 18a is also input to the input selector 71 in the bus transceiver 17. The input selector 71 performs switching so as to select data transmitted from another module via the first spare bus line 13 based on the input failure line information of the specific bit. The above operation is executed in all the modules 1, 2,..., N in the computer system as described in the previous embodiment.

If a fault occurs again in another specific bit line of the bus 12 before a fault elimination process such as replacement of a faulty portion of the bus 12 is performed, the information of the new faulty line is the second faulty line. Is written to the fault line information register 18b. The line information of another specific bit held in the failure line information register 18b is input to the output selector 91b in the second spare bus transceiver 19b. The output selector 91b switches the failure line of another specific bit of the bus 12 to the second spare bus line 13b based on the inputted failure line information and outputs data.
The information held in the second fault line information register 18b is also input to the input selector 71 in the bus transceiver 17. If the bit of the input selector 71 is another specific bit, switching is performed so that a signal is input from the second spare bus line 13b based on the fault line information input from the second fault line information register 18b. .

Therefore, according to the computer system of the second embodiment, even if a bus failure occurs in the 2-bit bus line, each failed line is connected to the first spare bus line 13a and the second spare bus line. Line 13b can be substituted. Therefore, the system can be operated stably even before recovery measures such as replacement of a failed part are performed. Further, according to the present embodiment, it is possible to provide a more reliable computer system as compared with the bus multiplexing system, and it is possible to provide a cheaper computer system.

In this embodiment, by preparing two spare bus lines, it is possible to cope with the failure of the bus 12 up to the 2-bit bus line. By preparing more than three (x is 3 or more), it is possible to cope with the occurrence of a failure of the x-bit bus line generated in the bus 12.

Next, a computer system according to a third embodiment of the present invention will be described.

When a short circuit or the like occurs between adjacent lines of the bus, a fault occurs simultaneously in a plurality of lines. The present embodiment addresses such a failure.

FIG. 5 shows the details of the configuration of the bus transceiver, the fault line information register and the spare bus transceiver in the module of the computer system according to the present embodiment.

As shown in FIG.
, N are odd-numbered bus transceivers (Tr. Odd) 171 connected to odd-numbered lines of the bus 12,
An even bus transceiver (Tr. Even) 172 connected to each even line of the bus 12, a first spare bus transceiver (S-Tr. 1) 191 connected to the first spare bus line 13a, A second spare bus transceiver (S-Tr. 2) 192 connected to the second spare bus line 13b, and an odd bus transceiver 17
A first fault line information register (EL Reg. 1) 18A for holding fault line information to be introduced into the first and first spare bus transceivers 191, an even bus transceiver 172 and a second spare bus transceiver 19
2, a second fault line information register (EL Reg. 2) 18B for holding fault line information to be introduced into the bus 2, and a first ECC circuit for performing error detection and error correction on data of each odd-numbered line of the bus 12. (ECC1) 20
A and a second ECC circuit (ECC) for performing error detection and error correction on data of each even-numbered line of the bus 12.
C2) 20B.

Next, the operation of the third embodiment will be described.

In this computer system, the bit data of the odd-numbered line group and the bit data of the even-numbered line group of the bus 12 are subjected to error detection / correction by the first ECC circuit 20A and the second ECC circuit 20B, respectively. Done.

In some cases, two adjacent lines in the bus 12 are short-circuited, and a fault occurs simultaneously in these two lines and detected. In this computer system, the bit data of the odd-numbered line group and the bit data of the even-numbered line group are detected / corrected by the separate ECC circuits 20A and 20B, respectively. Even if it occurs, the error can be correctly corrected.

When a bus failure is detected in each of the ECC circuits 20A and 20B, the failure line information in the odd-numbered line group is written into the first failure line information register 18A, and the second failure line information is written. The fault line information in the even-numbered line group is written to the information register 18B.

The information held in the first fault line information register 18A is input to the first spare bus transceiver 191 and the odd bus transceiver 171 so that the fault line in the odd line group of the bus 12 is replaced with the first spare bus. It is switched to the bus line 13a. The information held in the second fault line information register 18B is input to the second spare bus transceiver 192 and the even bus transceiver 172, and the fault line in the even line group of the bus 12 is replaced with the second spare bus. The line is switched to the line 13b.

The operation described above is performed for all the modules 1, 2,... In the computer system as described in the previous embodiment.
n.

Therefore, according to the computer system of the third embodiment, even if an error occurs simultaneously in the adjacent lines of the bus 12, the system is maintained until recovery processing such as replacement of a faulty part is performed. A computer system that can be operated stably and has higher reliability can be provided.

In the computer system of the present embodiment, two ECC circuits 20A and 20B are provided for each module, and all lines of the bus 12 are divided into two groups, odd and even, to detect errors for each group. It is configured to perform error correction, but three or more E
A CC circuit may be provided to divide all lines of the bus 12 into three groups and perform error detection and error correction for each group.

[0055]

As described above, according to the present invention, a faulty bus can be replaced on a line-by-line basis by using a spare line. Can operate the computer system stably, and can provide a computer system having the same reliability as the bus multiplexing system and being inexpensive.

Further, according to the present invention, when a plurality of faulty lines occur in different bus cycles, each faulty line can be replaced with a different spare line, and thus fault recovery such as replacement of a faulty part can be performed. The computer system can be operated stably even before the treatment is performed, and a computer system that is superior in reliability and less expensive than the bus multiplexing system can be provided.

Further, according to the present invention, even if a plurality of faulty lines occur simultaneously on the bus, these faulty lines can be replaced by a plurality of spare lines.
To provide a computer system that can operate a computer system stably even before a failure recovery procedure such as replacement of a failure point is performed, and has the same reliability and an inexpensive computer system as a bus multiplex system. Can be.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a computer system according to a first embodiment of the present invention.

FIG. 2 is a diagram showing details of a configuration of a bus transceiver and a spare bus transceiver inside the module shown in FIG. 1;

FIG. 3 is a diagram showing a connection between a bus transceiver and a bus in the module shown in FIG. 1;

FIG. 4 is a diagram showing a configuration inside a module of a computer system according to a second embodiment of the present invention.

FIG. 5 is a diagram showing a configuration inside a module of a computer system according to a third embodiment of the present invention.

[Explanation of symbols]

 1, 2,..., N module 12 bus line 13 spare bus line 14 processor 15 memory 16 bus I / F 17 bus transceiver 18 fault line information register 19 spare bus transceiver 20 ECC circuit 71 input selector 91 output selector

Claims (6)

[Claims] 1. A module comprising: a plurality of modules; a bus connecting the modules; and a spare line replacing a faulty line in the bus, wherein the module detects a faulty line in the bus. Detecting means, when a fault line is detected by the fault detecting means, a fault notifying means for notifying the information of the fault line to all the modules, and based on the fault line information notified by the fault notifying means, Switching means for switching the detected faulty line to the spare line. 2. A module comprising: a plurality of modules; a bus connecting the modules; and a plurality of spare lines replacing a faulty line in the bus, wherein the module detects a faulty line in the bus. A failure detection unit that notifies a failure line information to all the modules when a failure line is detected by the failure detection unit; and a plurality of failure line information notified by the failure notification unit. A computer system comprising: storage means capable of storing; and switching means for switching the faulty line to the spare line based on the faulty line information stored by the storage means. 3. A module comprising: a plurality of modules; a bus connecting the modules; and a plurality of spare lines replacing a faulty line in the bus, wherein the module detects an error in data flowing through the bus. Error detection and correction means for alternately performing error correction for each of a plurality of line groups constituting the bus, and when an error is detected in a certain line group by the error detection and correction means, all information on the line that caused the error is obtained. A computer system comprising: a failure notifying unit that notifies the module of the above (1); and a switching unit that switches the error line to the spare line based on the error line information notified by the failure notifying unit. 4. A bus failure recovery method for a computer system having a plurality of modules, a bus connecting between the modules, and a spare line replacing a failed line in the bus, wherein: When a faulty line in the bus is detected, the information of the detected faulty line is notified to all the modules, and all the modules replace the faulty line based on the notified faulty line information with the spare line. A method for recovering a bus failure of a computer system, characterized by switching to (1). 5. A bus failure recovery method for a computer system having a plurality of modules, a bus connecting the modules, and a plurality of spare lines replacing a failed line in the bus. When a faulty line in the bus is detected, the information of the faulty line is notified to all the modules, and all the modules store one or more pieces of the information of the notified faulty line, and A bus failure recovery method for a computer system, wherein the failure line is switched to the spare line based on one or a plurality of pieces of failure line information obtained. 6. A bus failure recovery method for a computer system having a plurality of modules, a bus connecting the modules, and a plurality of spare lines replacing a failed line in the bus, wherein each of the modules comprises: An error detection and correction means for alternately performing error detection and error correction of data flowing through the bus for each of a plurality of line groups constituting the bus; When an error is detected in, the information of the line that caused the error is notified to all the modules,
A bus failure recovery method for a computer system, wherein all modules switch the error line to the spare line based on the notified error line information.