JPS58184940U - front end circuit - Google Patents

front end circuit

Info

Publication number
JPS58184940U
JPS58184940U JP8125682U JP8125682U JPS58184940U JP S58184940 U JPS58184940 U JP S58184940U JP 8125682 U JP8125682 U JP 8125682U JP 8125682 U JP8125682 U JP 8125682U JP S58184940 U JPS58184940 U JP S58184940U
Authority
JP
Japan
Prior art keywords
circuit
intermediate frequency
output
local oscillation
switching circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8125682U
Other languages
Japanese (ja)
Other versions
JPH0127303Y2 (en
Inventor
登山　徹也
Original Assignee
オンキヨー株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by オンキヨー株式会社 filed Critical オンキヨー株式会社
Priority to JP8125682U priority Critical patent/JPS58184940U/en
Publication of JPS58184940U publication Critical patent/JPS58184940U/en
Application granted granted Critical
Publication of JPH0127303Y2 publication Critical patent/JPH0127303Y2/ja
Granted legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来のフロントエンド回路の構成を示す図、第
２図および第３図は同、説明図、−第４図は本考案のフ
ロントエンド回路の構成を示す図、−第５図は同、説明
図である。 １はアンテナ入力回路、２は高周波増幅回路、３は混合
回路、４は局部発振回路、５は中間周波共振回路、７は
ダンピング用抵抗、８はスイッチング回路である。FIG. 1 is a diagram showing the configuration of a conventional front-end circuit, FIGS. 2 and 3 are explanatory diagrams, - FIG. 4 is a diagram showing the configuration of the front-end circuit of the present invention, and - FIG. It is an explanatory diagram of the same. 1 is an antenna input circuit, 2 is a high frequency amplifier circuit, 3 is a mixing circuit, 4 is a local oscillation circuit, 5 is an intermediate frequency resonant circuit, 7 is a damping resistor, and 8 is a switching circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] アンテナ入力回路１からの信号を高周波増幅回路２によ
って選択増幅した後、局部発振回路４からの局部発振出
力とともに混合回路３に入力し、当該混合回路３から出
力される混合出力を中間周波共振回路５に入力して当該
中間周波検出回路から中間周波信号を取出すようにした
構成においで、上記中間周波共振回路５の出力端をダン
ピング用抵抗７、当該抵抗に直列に接続されたスイッチ
ング回路８を介して接地し、当該スイッチング回路８を
電界強度検出電圧によって開閉制御するようによって開
閉制御するようにしたことを特徴とするフロントエンド
回路。After the signal from the antenna input circuit 1 is selectively amplified by the high frequency amplifier circuit 2, it is input to the mixing circuit 3 together with the local oscillation output from the local oscillation circuit 4, and the mixed output output from the mixing circuit 3 is sent to the intermediate frequency resonant circuit. 5 and extracts the intermediate frequency signal from the intermediate frequency detection circuit, the output terminal of the intermediate frequency resonant circuit 5 is connected to a damping resistor 7 and a switching circuit 8 connected in series to the resistor. A front end circuit characterized in that the switching circuit 8 is controlled to open and close by grounding the switching circuit 8 via the electric field strength detection voltage.
JP8125682U 1982-05-31 1982-05-31 front end circuit Granted JPS58184940U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8125682U JPS58184940U (en) 1982-05-31 1982-05-31 front end circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8125682U JPS58184940U (en) 1982-05-31 1982-05-31 front end circuit

Publications (2)

Publication Number Publication Date
JPS58184940U true JPS58184940U (en) 1983-12-08
JPH0127303Y2 JPH0127303Y2 (en) 1989-08-15

Family

ID=30090372

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8125682U Granted JPS58184940U (en) 1982-05-31 1982-05-31 front end circuit

Country Status (1)

Country Link
JP (1) JPS58184940U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010519818A (en) * 2007-02-15 2010-06-03 メド−エル エレクトロメディジニシェ ゲラテ ゲーエムベーハー Induction power and data transmission system based on class D and amplitude shift keying

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5395723U (en) * 1976-12-30 1978-08-04
JPS5733837A (en) * 1980-08-08 1982-02-24 Mitsubishi Electric Corp Receiving equipment

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5395723U (en) * 1976-12-30 1978-08-04
JPS5733837A (en) * 1980-08-08 1982-02-24 Mitsubishi Electric Corp Receiving equipment

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010519818A (en) * 2007-02-15 2010-06-03 メド−エル エレクトロメディジニシェ ゲラテ ゲーエムベーハー Induction power and data transmission system based on class D and amplitude shift keying

Also Published As

Publication number Publication date
JPH0127303Y2 (en) 1989-08-15

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