JPH0127303Y2 - - Google Patents

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Publication number
JPH0127303Y2
JPH0127303Y2 JP1982081256U JP8125682U JPH0127303Y2 JP H0127303 Y2 JPH0127303 Y2 JP H0127303Y2 JP 1982081256 U JP1982081256 U JP 1982081256U JP 8125682 U JP8125682 U JP 8125682U JP H0127303 Y2 JPH0127303 Y2 JP H0127303Y2
Authority
JP
Japan
Prior art keywords
circuit
intermediate frequency
field strength
frequency resonant
resonant circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1982081256U
Other languages
Japanese (ja)
Other versions
JPS58184940U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP8125682U priority Critical patent/JPS58184940U/en
Publication of JPS58184940U publication Critical patent/JPS58184940U/en
Application granted granted Critical
Publication of JPH0127303Y2 publication Critical patent/JPH0127303Y2/ja
Granted legal-status Critical Current

Links

Description

【考案の詳細な説明】 本考案はフロントエンド回路の改良に関する。[Detailed explanation of the idea] The present invention relates to improvements in front-end circuits.

一般に、チユーナーのフロントエンド回路は、
第1図に示すように、アンテナ入力回路1からの
信号を高周波増幅回路2によつて選択増幅した
後、混合回路3たとえばデユアルゲート・MOS
型電界効果トランジスタQ1の一方のゲート端子
G1に入力するとともに、他方のゲート端子G2
局部発振回路4からの局部発振出力を入力し、両
信号の混合出力を中間周波共振回路5を通して中
間周波信号(10.7MHz)を取出し、その後、この
中間周波信号を中間周波増幅回路6に入力するよ
うにした構成を有する。
Generally, the front end circuit of a tuner is
As shown in FIG. 1, after a signal from an antenna input circuit 1 is selectively amplified by a high frequency amplifier circuit 2, a mixing circuit 3 such as a dual gate/MOS
One gate terminal of type field effect transistor Q1
At the same time, the local oscillation output from the local oscillation circuit 4 is input to the other gate terminal G 2 , and the mixed output of both signals is passed through the intermediate frequency resonant circuit 5 to take out the intermediate frequency signal (10.7MHz). , has a configuration in which this intermediate frequency signal is input to an intermediate frequency amplification circuit 6.

このような構成において、中間周波増幅部で発
生する歪の原因として中間周波フイルタの群遅延
特性がフラツトでないことが挙げられるが、特
に、フロントエンドの中間周波共振回路5の群遅
延特性が歪発生の原因として問題になることがあ
る。
In such a configuration, one of the causes of distortion occurring in the intermediate frequency amplification section is that the group delay characteristic of the intermediate frequency filter is not flat, but in particular, the group delay characteristic of the front end intermediate frequency resonant circuit 5 causes distortion. This may cause problems.

すなわち、中間周波共振回路5の群遅延特性
は、第2図に示すようにコイルLのQLが大きい
ほど単蜂性の特性となり、歪が増大する。また、
コイルLのQLが小さいほどフラツトな特性とな
り、歪が減少する。このような現象を電界強度と
の関係において考察すると、電界強度が小さい場
合、群遅延特性は単蜂性となり、電界強度が十分
大きい場合は、トランジスタQ1が飽和してコイ
ルLのQLをダンプしたことと等価となり、群遅
延特性はほぼフラツトになる(第3図)。
That is, as shown in FIG. 2, the group delay characteristic of the intermediate frequency resonant circuit 5 becomes more monophonic as the Q L of the coil L becomes larger, and the distortion increases. Also,
The smaller the Q L of the coil L, the flatter the characteristics and the less distortion. Considering this phenomenon in relation to the electric field strength, when the electric field strength is small, the group delay characteristic becomes monophonic, and when the electric field strength is sufficiently large, the transistor Q 1 is saturated and the Q L of the coil L is This is equivalent to dumping, and the group delay characteristic becomes almost flat (Figure 3).

このように、中間周波共振回路5の群遅延特性
は、コイルLのQLが小さい場合、あるいは電界
強度が十分大きく、トランジスタQ1が飽和して
コイルLのQLがダンプされたと等価な場合にフ
ラツトになり歪が低減されるが、その反面、中間
周波共振回路5の利得が小さくなり、感度が悪く
なる。
In this way, the group delay characteristics of the intermediate frequency resonant circuit 5 are as follows: When the Q L of the coil L is small, or when the electric field strength is sufficiently large, it is equivalent to the transistor Q 1 being saturated and the Q L of the coil L being dumped. However, on the other hand, the gain of the intermediate frequency resonant circuit 5 becomes smaller and the sensitivity becomes worse.

したがつて、従来は、第1図に示すように中間
周波共振回路5と並列にダンピング抵抗Rを接続
することにより、コイルLのQLをダンピングし
て、感度と歪とのバランスをとつていた。そのた
め、電界強度が小さい場合は感度が不足し、電界
強度が十分大きく高感度が必要でない場合におい
ても十分な歪低減をすることができない欠点があ
つた。
Therefore, conventionally, as shown in Fig. 1, a damping resistor R is connected in parallel with the intermediate frequency resonant circuit 5 to damp the Q L of the coil L to balance sensitivity and distortion. was. Therefore, the sensitivity is insufficient when the electric field strength is low, and even when the electric field strength is sufficiently large and high sensitivity is not required, there is a drawback that sufficient distortion cannot be reduced.

本考案はこのような点に鑑みてなされたもの
で、電界強度が十分大きく高感度が必要でない場
合中間周波共振回路のコイルのQを積極的にダン
プすることにより、中間周波共振回路の群遅延特
性を十分フラツトにして歪を著しく低減し、か
つ、電界強度が小さい場合には高感度を保持する
ようにしたことを特徴とするものである。
The present invention was developed in view of these points, and when the electric field strength is large enough and high sensitivity is not required, the group delay of the intermediate frequency resonant circuit can be reduced by actively damping the Q of the coil of the intermediate frequency resonant circuit. It is characterized in that the characteristics are made sufficiently flat to significantly reduce distortion, and high sensitivity is maintained when the electric field strength is small.

以下、第4図の一実施例において説明する。図
中、第1図の従来例と同一部分については同一符
号を付し、その説明は省略する。
An embodiment of FIG. 4 will be explained below. In the figure, the same parts as those in the conventional example shown in FIG.

図において、中間周波共振回路5の出力端をダ
ンピング用抵抗7、この抵抗7に直列に接続され
たスイツチング回路8たとえばトランジスタQ2
を介して接地し、一方中間周波増幅回路6の所定
の位置から取出した中間周波信号をダイオードD
によつて整流した後、平滑して直流電圧に交換
し、この直流電圧を電界強度検出電圧としてトラ
ンジスタQ2の制御端子(ベース端子)に入力し
た構成である。
In the figure, the output end of the intermediate frequency resonant circuit 5 is connected to a damping resistor 7, and a switching circuit 8, for example, a transistor Q2, is connected in series to the damping resistor 7 .
The intermediate frequency signal taken out from a predetermined position of the intermediate frequency amplifier circuit 6 is grounded through the diode D.
After rectifying the voltage, it is smoothed and exchanged into a DC voltage, and this DC voltage is input to the control terminal (base terminal) of the transistor Q2 as a field strength detection voltage.

以上の構成について動作を説明する。 The operation of the above configuration will be explained.

(1) 電界強度が小さい場合 中間周波信号のレベルが小さく電界強度検出電
圧が小さいので、トランジスタQ2は遮断状態に
保持され、したがつて、高感度が保持される。す
なわち、従来例のように感度と歪とのバランスを
とることを目的としてコイルLのQLを抵抗Rに
よつてダンピングしていないので、第5図に示す
ように群遅延特性は単蜂性となり歪の点で改善は
ないが、高感度受信ができる。
(1) When the electric field strength is low Since the level of the intermediate frequency signal is low and the field strength detection voltage is small, the transistor Q2 is kept in a cut-off state, and therefore high sensitivity is maintained. In other words, unlike the conventional example, the Q L of the coil L is not damped by the resistor R in order to balance sensitivity and distortion, so the group delay characteristic is monophonic as shown in Figure 5. There is no improvement in terms of distortion, but high-sensitivity reception is possible.

(2) 電界強度が十分大きい場合 中間周波信号のレベルが大きく、電界強度検出
電圧がトランジスタQ2を導通させる十分なほど
大きくなると、トランジスタQ2が導通状態とな
り、中間周波共振回路5の出力端がダンピング用
抵抗7を介して接地される。そうすると、コイル
LのQLが十分にダンプされて小さくなるため、
中間周波共振回路5の群遅延特性が第5図に示す
ように十分フラツトになり、歪が著しく低減され
る。
(2) When the electric field strength is sufficiently large When the level of the intermediate frequency signal is large and the field strength detection voltage becomes large enough to make the transistor Q 2 conductive, the transistor Q 2 becomes conductive, and the output terminal of the intermediate frequency resonant circuit 5 becomes conductive. is grounded via the damping resistor 7. Then, the Q L of the coil L is sufficiently damped and becomes small, so
The group delay characteristic of the intermediate frequency resonant circuit 5 becomes sufficiently flat as shown in FIG. 5, and distortion is significantly reduced.

この場合、電界強度が十分大きいめ、高感度は
必要でない。
In this case, the electric field strength is sufficiently large, so high sensitivity is not required.

以上のように、本考案は電界強度が十分大きい
場合中間周波共振回路5のコイルのQを積極的に
ダンプするようにしたので、電界強度が小さい場
合は高感度で、電界強度が十分大きい場合は歪が
著しく低減され、良好な受信ができる優れた利点
を有する。
As described above, in the present invention, when the electric field strength is sufficiently large, the Q of the coil of the intermediate frequency resonant circuit 5 is actively damped, so when the electric field strength is small, the sensitivity is high, and when the electric field strength is sufficiently large, the sensitivity is high. has the advantage of significantly reduced distortion and good reception.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のフロントエンド回路の構成を示
す図、第2図および第3図は同、説明図、第4図
は本考案のフロントエンド回路の構成を示す図、
第5図は同、説明図である。 1……アンテナ入力回路、2……高周波増幅回
路、3……混合回路、4……局部発振回路、5…
…中間周波共振回路、7……ダンピング用抵抗、
8……スイツチング回路である。
FIG. 1 is a diagram showing the configuration of a conventional front-end circuit, FIGS. 2 and 3 are explanatory diagrams, and FIG. 4 is a diagram showing the configuration of the front-end circuit of the present invention.
FIG. 5 is an explanatory diagram of the same. 1...Antenna input circuit, 2...High frequency amplification circuit, 3...Mixing circuit, 4...Local oscillation circuit, 5...
...Intermediate frequency resonant circuit, 7...damping resistor,
8...Switching circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] アンテナ入力回路1からの信号を高周波増幅回
路2によつて選択増幅した後、局部発振回路4か
らの局部発振出力とともに混合回路3に入力し、
当該混合回路3から出力される混合出力を中間周
波共振回路5に入力して当該中間周波共振回路か
ら中間周波信号を取り出すようにした構成におい
て、上記中間周波共振回路5の出力端をダンピン
グ用抵抗7、当該抵抗に直列に接続されたスイツ
チング回路8を介して接地し、当該スイツチング
回路8を電界強度検出電圧によつて開閉制御し、
当該電界強度検出電圧が所定のレベルを越えたと
きに上記スイツチング回路8を導通させて、上記
中間周波共振回路5の群遅延特性がフラツトにな
るように制御するようにしたことを特徴とするフ
ロントエンド回路。
After selectively amplifying the signal from the antenna input circuit 1 by the high frequency amplifier circuit 2, the signal is inputted to the mixing circuit 3 together with the local oscillation output from the local oscillation circuit 4,
In a configuration in which a mixed output output from the mixing circuit 3 is input to an intermediate frequency resonant circuit 5 and an intermediate frequency signal is taken out from the intermediate frequency resonant circuit, the output end of the intermediate frequency resonant circuit 5 is connected to a damping resistor. 7. Grounding via a switching circuit 8 connected in series to the resistor, and controlling opening/closing of the switching circuit 8 by the electric field strength detection voltage;
The front panel is characterized in that when the field strength detection voltage exceeds a predetermined level, the switching circuit 8 is brought into conduction to control the group delay characteristic of the intermediate frequency resonant circuit 5 to be flat. end circuit.
JP8125682U 1982-05-31 1982-05-31 front end circuit Granted JPS58184940U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8125682U JPS58184940U (en) 1982-05-31 1982-05-31 front end circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8125682U JPS58184940U (en) 1982-05-31 1982-05-31 front end circuit

Publications (2)

Publication Number Publication Date
JPS58184940U JPS58184940U (en) 1983-12-08
JPH0127303Y2 true JPH0127303Y2 (en) 1989-08-15

Family

ID=30090372

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8125682U Granted JPS58184940U (en) 1982-05-31 1982-05-31 front end circuit

Country Status (1)

Country Link
JP (1) JPS58184940U (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8023586B2 (en) * 2007-02-15 2011-09-20 Med-El Elektromedizinische Geraete Gmbh Inductive power and data transmission system based on class D and amplitude shift keying

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5733837A (en) * 1980-08-08 1982-02-24 Mitsubishi Electric Corp Receiving equipment

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5852737Y2 (en) * 1976-12-30 1983-12-01 ヤマハ株式会社 Receiving machine

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5733837A (en) * 1980-08-08 1982-02-24 Mitsubishi Electric Corp Receiving equipment

Also Published As

Publication number Publication date
JPS58184940U (en) 1983-12-08

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