JPS58184749A - 半導体用リ−ドピンのろう付方法 - Google Patents

半導体用リ−ドピンのろう付方法

Info

Publication number
JPS58184749A
JPS58184749A JP57068209A JP6820982A JPS58184749A JP S58184749 A JPS58184749 A JP S58184749A JP 57068209 A JP57068209 A JP 57068209A JP 6820982 A JP6820982 A JP 6820982A JP S58184749 A JPS58184749 A JP S58184749A
Authority
JP
Japan
Prior art keywords
brazing
plated
ceramic substrate
lead
component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57068209A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0226787B2 (enExample
Inventor
Hitoshi Tsuji
斉 辻
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tanaka Kikinzoku Kogyo KK
Original Assignee
Tanaka Kikinzoku Kogyo KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tanaka Kikinzoku Kogyo KK filed Critical Tanaka Kikinzoku Kogyo KK
Priority to JP57068209A priority Critical patent/JPS58184749A/ja
Publication of JPS58184749A publication Critical patent/JPS58184749A/ja
Publication of JPH0226787B2 publication Critical patent/JPH0226787B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H10W70/093
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/24Reinforcing the conductive pattern
    • H05K3/244Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3421Leaded components
    • H05K3/3426Leaded components characterised by the leads
    • H05K3/3465

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
JP57068209A 1982-04-23 1982-04-23 半導体用リ−ドピンのろう付方法 Granted JPS58184749A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57068209A JPS58184749A (ja) 1982-04-23 1982-04-23 半導体用リ−ドピンのろう付方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57068209A JPS58184749A (ja) 1982-04-23 1982-04-23 半導体用リ−ドピンのろう付方法

Publications (2)

Publication Number Publication Date
JPS58184749A true JPS58184749A (ja) 1983-10-28
JPH0226787B2 JPH0226787B2 (enExample) 1990-06-12

Family

ID=13367172

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57068209A Granted JPS58184749A (ja) 1982-04-23 1982-04-23 半導体用リ−ドピンのろう付方法

Country Status (1)

Country Link
JP (1) JPS58184749A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003072288A1 (de) * 2002-02-28 2003-09-04 Infineon Technologies Ag Verbindung mit einer diffusionslotstelle und verfahren zu ihrer herstellung

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003072288A1 (de) * 2002-02-28 2003-09-04 Infineon Technologies Ag Verbindung mit einer diffusionslotstelle und verfahren zu ihrer herstellung
US7368824B2 (en) 2002-02-28 2008-05-06 Infineon Technologies Ag Diffusion solder position, and process for producing it

Also Published As

Publication number Publication date
JPH0226787B2 (enExample) 1990-06-12

Similar Documents

Publication Publication Date Title
US4418857A (en) High melting point process for Au:Sn:80:20 brazing alloy for chip carriers
JP2518987B2 (ja) 還元性雰囲気を用いた基板はんだ付け方法
US5543584A (en) Structure for repairing electrical lines
KR0124924B1 (ko) 회로기판의 패드로의 납땜층 형성방법 및 회로기판으로의 전자부품 실장방법
KR20010112057A (ko) 반도체 모듈 및 반도체 장치를 접속한 회로 기판
JPH0528000B2 (enExample)
KR20120094850A (ko) 도전성 접합 재료 및 도체의 접합 방법
US3751799A (en) Solder terminal rework technique
US3413711A (en) Method of making palladium copper contact for soldering
EP0082271B1 (en) Methods of brazing adjoining surfaces of elements, brazing alloys, and structures comprising brazed joints
US4465223A (en) Process for brazing
JPS58184749A (ja) 半導体用リ−ドピンのろう付方法
JPS60121063A (ja) 球状ろう材付リ−ドピンの製造方法
EP0167075B1 (en) Process for bonding current carrying elements to a substrate
EP0055368B1 (en) Process for brazing
CN110744163B (zh) 一种抗热迁移微焊点结构及其制备方法
US6943435B2 (en) Lead pin with Au-Ge based brazing material
JP3470789B2 (ja) 配線基板及びその製造方法
JP3214638B2 (ja) 半導体パッケージ用のセラミック製リッド及びその製造方法
KR100479243B1 (ko) 전기도금된리드를가진반도체장치의제조방법
JPH0214787B2 (enExample)
JPH0417994A (ja) はんだ組成物
JPH0550142B2 (enExample)
JPH0226786B2 (enExample)
Harada et al. A new Ni-W thin film metallization for solder interconnections and design method of metallization thickness