JPS58184647A - デ−タ転送方式 - Google Patents
デ−タ転送方式Info
- Publication number
- JPS58184647A JPS58184647A JP6688482A JP6688482A JPS58184647A JP S58184647 A JPS58184647 A JP S58184647A JP 6688482 A JP6688482 A JP 6688482A JP 6688482 A JP6688482 A JP 6688482A JP S58184647 A JPS58184647 A JP S58184647A
- Authority
- JP
- Japan
- Prior art keywords
- data
- byte
- data transfer
- bytes
- buffer memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Information Transfer Systems (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6688482A JPS58184647A (ja) | 1982-04-21 | 1982-04-21 | デ−タ転送方式 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6688482A JPS58184647A (ja) | 1982-04-21 | 1982-04-21 | デ−タ転送方式 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58184647A true JPS58184647A (ja) | 1983-10-28 |
| JPS6245576B2 JPS6245576B2 (enExample) | 1987-09-28 |
Family
ID=13328762
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6688482A Granted JPS58184647A (ja) | 1982-04-21 | 1982-04-21 | デ−タ転送方式 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58184647A (enExample) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02254540A (ja) * | 1989-03-29 | 1990-10-15 | Fujitsu Ltd | 命令カウンタ制御方式 |
| US7136971B2 (en) | 1987-12-14 | 2006-11-14 | Intel Corporation | Memory controller for synchronous burst transfers |
| WO2009037798A1 (ja) * | 2007-09-21 | 2009-03-26 | Mitsubishi Electric Corporation | データ転送装置及びデータ転送方法 |
-
1982
- 1982-04-21 JP JP6688482A patent/JPS58184647A/ja active Granted
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7136971B2 (en) | 1987-12-14 | 2006-11-14 | Intel Corporation | Memory controller for synchronous burst transfers |
| JPH02254540A (ja) * | 1989-03-29 | 1990-10-15 | Fujitsu Ltd | 命令カウンタ制御方式 |
| WO2009037798A1 (ja) * | 2007-09-21 | 2009-03-26 | Mitsubishi Electric Corporation | データ転送装置及びデータ転送方法 |
| US8073992B2 (en) | 2007-09-21 | 2011-12-06 | Mitsubishi Electric Corporation | Data transfer device and data transfer method |
| JP4937355B2 (ja) * | 2007-09-21 | 2012-05-23 | 三菱電機株式会社 | データ転送装置及びデータ転送方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6245576B2 (enExample) | 1987-09-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5446915A (en) | Parallel processing system virtual connection method and apparatus with protection and flow control | |
| US6754735B2 (en) | Single descriptor scatter gather data transfer to or from a host processor | |
| US7653763B2 (en) | Subsystem boot and peripheral data transfer architecture for a subsystem of a system-on- chip | |
| US6173353B1 (en) | Method and apparatus for dual bus memory transactions | |
| JPH11507749A (ja) | 分割バッファアーキテクチュア | |
| US6029233A (en) | Circuit for moving data between remote memories and computer comprising such a circuit | |
| EP0464848B1 (en) | Structure for enabling direct memory-to-memory transfer | |
| JPS58184647A (ja) | デ−タ転送方式 | |
| US5265228A (en) | Apparatus for transfer of data units between buses | |
| JP2000029826A (ja) | 多重レベルキャッシングを有する3ポ―トfifoデ―タバッファ | |
| JPS5949624A (ja) | デ−タ転送装置 | |
| US6233628B1 (en) | System and method for transferring data using separate pipes for command and data | |
| EP0446335B1 (en) | Packet/fast packet switch for voice and data | |
| JP2533886B2 (ja) | デ―タ転送方式 | |
| WO2004036267A2 (en) | Method of queuing fibre channel receive frames | |
| JPH01236342A (ja) | Dmaコントローラ | |
| US7167942B1 (en) | Dynamic random access memory controller | |
| JPS6162961A (ja) | 入出力機器 | |
| JPH05233482A (ja) | データ転送システム | |
| JPS62203257A (ja) | 情報処理装置 | |
| JP3450392B2 (ja) | インタフェース装置及び周辺機器 | |
| JPH02245959A (ja) | 入出力制御装置におけるデータ転送方式 | |
| JPS61123950A (ja) | メモリアクセス制御方式 | |
| JPS5831459A (ja) | 磁気バブルメモリ装置 | |
| JPS60114927A (ja) | フアイルメモリアクセス制御方式 |