JPS58182854A - Resin-sealed semiconductor device and manufacture thereof - Google Patents
Resin-sealed semiconductor device and manufacture thereofInfo
- Publication number
- JPS58182854A JPS58182854A JP57065272A JP6527282A JPS58182854A JP S58182854 A JPS58182854 A JP S58182854A JP 57065272 A JP57065272 A JP 57065272A JP 6527282 A JP6527282 A JP 6527282A JP S58182854 A JPS58182854 A JP S58182854A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- sheet
- semiconductor device
- wiring board
- main surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
本発明４まレジン封圧型半導体装置およびその製造方法
に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a resin sealed semiconductor device and a method for manufacturing the same.
チップ・オン・ボード型のレジン封止型半導体装置は、
第１図に示すように、プリント基板のような配線基板１
の主面の搭載領域に半導体素子（チップ）２を固定する
とともに、このチップ２の図示しない電極と配４１Ｔｌ
基板１０図示しない配線層とを導輪（ワイヤ）３で接続
し、さらにチップ２およびワイヤ３を被うように配ｌＩ
ｉ！基板１の主面にレジン４を塗布硬化させた構造とな
っている。Chip-on-board type resin-sealed semiconductor devices are
As shown in FIG. 1, a wiring board 1 such as a printed circuit board
A semiconductor element (chip) 2 is fixed to a mounting area on the main surface of the chip 2, and an electrode (not shown) of this chip 2 and a wiring 41Tl
The substrate 10 is connected to a wiring layer (not shown) using a guide ring (wire) 3, and is further arranged so as to cover the chip 2 and the wire 3.
i! It has a structure in which a resin 4 is applied and hardened on the main surface of a substrate 1.
この際、前記レジンの封止厚さ、封止領域を所望形態に
するために、レジン塗布前に配線基板の主面にレジン塗
布領域を取り囲むように園体固定砕やシリコングリスに
よる固定枠５を所望厚さに形成している。そして、この
固定枠５の形成後に固定枠５内にレジンを滴下塗布して
いる。At this time, in order to make the sealing thickness of the resin and the sealing area into the desired shape, before applying the resin, a fixing frame 5 is placed on the main surface of the wiring board with a fixing frame made of powder or silicone grease so as to surround the resin coating area. is formed to a desired thickness. After the fixed frame 5 is formed, resin is applied dropwise into the fixed frame 5.
しかし、このよ５なレジン封止は、固定枠の効果がバラ
ツクとともに、封止レジンの形状ＩＬｓレジン鳳、粘度
さらには表面張力によるため、形状形成が完全ではな（
、封止レジンの厚さが現点より厚くなって薄個化に逆行
したり、あるいは薄くなりすぎてチップ２が透けて見え
たり、あるいは露出したりして外観不良や耐湿性低下を
来し、好ましくない。However, in this type of resin sealing, the shape formation is not perfect because the effect of the fixing frame varies, the shape of the sealing resin, resin strength, viscosity, and surface tension (
, the thickness of the sealing resin may become thicker than it is now, going against the trend of thinning, or it may become too thin and the chip 2 may be seen through or exposed, resulting in poor appearance and reduced moisture resistance. , undesirable.
したがって、本発明の目的は封止レジンの薄畠化を図る
とともに、外観不良や耐湿性低下を防止することにある
。Therefore, an object of the present invention is to reduce the thickness of the sealing resin and to prevent poor appearance and deterioration in moisture resistance.
このような目的を達成するために本発明）末、配線基板
と、この配線基板の主面に固定した半導体素子と、この
半導体素子の電極と配線基板の配線層を接続する導線と
、導線および半導体素子を被うように配線基板の主面に
取り付けられた封止レジンからなるレジン封止型半導体
装置において、前記封止レジンの上面には絶縁性のシー
トが取り付けられてなるものである。また、製造にあっ
ては、レジンの塗布工櫛後のレジンが未硬化の時にシー
トをレジン上に載ぜてレジンの表面張力を利用してレジ
ンをシート全下向に密着させるようにしてなるものであ
る。In order to achieve such an object, the present invention comprises a wiring board, a semiconductor element fixed to the main surface of the wiring board, a conducting wire connecting the electrode of the semiconductor element and the wiring layer of the wiring board, and a conducting wire and a semiconductor element fixed to the main surface of the wiring board. A resin-sealed semiconductor device includes a sealing resin attached to the main surface of a wiring board so as to cover a semiconductor element, and an insulating sheet is attached to the upper surface of the sealing resin. In addition, during manufacturing, the sheet is placed on the resin when the resin is uncured after being applied, and the surface tension of the resin is used to make the resin adhere to the entire downward direction of the sheet. It is something.
以−ト、実施例により本発明を説明する。The present invention will now be explained with reference to Examples.
１に２図（ａｌ〜（山は本発明の一実施例によるレジン
封止型半導体装置の製造方法を示す断面図である。Figures 1 and 2 are cross-sectional views showing a method for manufacturing a resin-sealed semiconductor device according to an embodiment of the present invention.
すなわち、同図（ａｌで示すように、プリント基板から
なる配線基板１を用意した後、配線基板ｌ主面の中央の
窪んだベレット取付部に半導体素子（チップ）２を取り
付けるとともに、配Ｓ基板１の主面に設けた図示しない
配線層とチップ２の図示しない電極とをワイヤ（導１り
３で接続する。That is, as shown in FIG. A wiring layer (not shown) provided on the main surface of the chip 1 and an electrode (not shown) of the chip 2 are connected by wires (conductors 1 and 3).
つぎに、同図ｆｂｌで示すように、封止用のレジン４を
配線基板１の主面に塗布してワイヤ３およびチップ２を
被った後、レジン４が流動性を有する未硬化状態で同図
ｔｃｌＫ示すように絶縁性の薄いシート６をレジン４上
に載置する。このシート６はワイヤ３の外端を固定する
配線層部分をも被うような大きさになＪている。シート
６をレジン４上に載せると、レジン４はその表面張力に
よってシート６の下面全域に密着する結果、配線基板１
上に広く広がっていたレジン４は中央に引き戻されるよ
うになって、同図（ｄｉで示すように、略シート６の下
に一ホの厚さで封入されるようになる。そこで、レジン
４をキュアして硬化させ、同図１ｄｌに示すような構造
のレジン封止型半導体装［１７を製造する。Next, as shown at fbl in the same figure, a sealing resin 4 is applied to the main surface of the wiring board 1 to cover the wires 3 and the chip 2, and then the same is applied in an uncured state where the resin 4 has fluidity. As shown in Figure tclK, an insulating thin sheet 6 is placed on the resin 4. This sheet 6 is sized so as to cover the wiring layer portion to which the outer ends of the wires 3 are fixed. When the sheet 6 is placed on the resin 4, the resin 4 adheres to the entire bottom surface of the sheet 6 due to its surface tension, and as a result, the wiring board 1
The resin 4, which had been spread widely above, is pulled back to the center and is enclosed approximately one inch thick under the sheet 6, as shown in the same figure (di). is cured and hardened to produce a resin-sealed semiconductor device [17] having a structure as shown in FIG. 1dl.
このような実施例によれば、溶融状態のレジン４の上に
絶縁性のシート６を載置する結果、シート６の自重と、
レジン４の表面張力によって封止レジン形状はシート６
の形状と一致しかつ低く封止される。レジン４とシート
６とからなるパッケージの高さは、レジン４の塗布量の
ばらつき程度ではシート面積が広いこともあってそれほ
ど東北しない。また、低くても、チップ２．ワイヤ３は
シート６で完全に被われることから耐温性は充分維持で
きるようになる。According to this embodiment, as a result of placing the insulating sheet 6 on top of the molten resin 4, the weight of the sheet 6 and
Due to the surface tension of the resin 4, the shape of the sealing resin is the sheet 6.
Matches the shape of and is sealed low. The height of the package consisting of the resin 4 and the sheet 6 is not so high depending on the variation in the amount of the resin 4 applied, partly because the sheet area is wide. Also, even if it is low, the chip is 2. Since the wire 3 is completely covered with the sheet 6, sufficient temperature resistance can be maintained.
また、シート６が透明である場合、シート６を介してワ
イヤ等が目視できる状態史も耐湿性には便箋支障はない
ことから、外観不良とする必要もないと思える。なお、
この場合、シート６を不透明体にしておけば、ワイヤ等
が見えるための外観不良に起きなくなる。Furthermore, if the sheet 6 is transparent, the fact that wires and the like can be visually seen through the sheet 6 does not affect the moisture resistance of the stationery, so there is no need to make the appearance defective. In addition,
In this case, if the sheet 6 is made of an opaque material, poor appearance due to visible wires will not occur.
なお、本発明は前記実施例に限定されない。たとえば、
シート６の露出面となる面にあらかじめ必要なマークを
印刷しておけば、パッケージ後の面倒なマーキング（印
刷）作業を末不要となる。また、シート６は峡品の品種
２等級によって色を変えるようにしてもよい。Note that the present invention is not limited to the above embodiments. for example,
If necessary marks are printed in advance on the exposed surface of the sheet 6, the troublesome marking (printing) work after packaging becomes unnecessary. Further, the color of the sheet 6 may be changed depending on the second grade of the product.
さらに、配線基板としてはセラミック基板あるいはリー
ドフレーム等でもよい。Further, the wiring board may be a ceramic board, a lead frame, or the like.
以上のように、本発明によれげノくソケージの薄型化を
図ることができるとともに、耐湿性の向上、外観不良の
低下を図ることができる。As described above, according to the present invention, it is possible to reduce the thickness of the cage, and also to improve moisture resistance and reduce appearance defects.
第１図は従来のレジン封止型半導体装置の断面図、第２
図１ａ１〜（ｄｉは本卸明の一実施例によるレジン封止
型中導体装置の糎遣方法を示す断面図である。
ｌ・・・配線基板、２・・・牛導体素子、３・・・導線
、４・・・レジン、６・・・Ｐ−ト、７・・・レジン封
止塵中導体装置。
第 １ 図
第 ２ 図
２４３−Figure 1 is a cross-sectional view of a conventional resin-sealed semiconductor device;
1a1-(di are cross-sectional views showing a method of pasting a resin-sealed medium conductor device according to an embodiment of the present invention. 1... Wiring board, 2... Conductor element, 3...・Conductor wire, 4...Resin, 6...P-t, 7...Resin-sealed dust conductor device. Fig. 1 Fig. 2 Fig. 243-
Claims (1)
素子と、この半導体素子の電極と配線基板の配線層を接
続する導線と、導線および半導体素子を被うように配線
基板の主面に取っ付ゆられた封止レジンからなるレジン
封止型半導体装置において、前記封止レジンの上面には
絶縁性のシートが取っ付げられていることを特徴とする
レジン封止型半導体装置。 ２、配線基板の主面に半導体素子を固定する固定工程と
、前記半導体素子の電極と配線基板の配線層を導線で接
続する接続工程と、前記半導体素子および導線を被うよ
うにレジンを配線基板の主面に塗布する塗布工程と、前
記レジンを硬化させる硬化工程と、からなるレジン封止
型半導体装置の製造方法にお（・て、前記塗布工程後に
絶縁性シートを未硬化のレジン上に載置した後、レジン
の硬化を行なうことを特徴とするレジン封圧型半導体装
置の製造方法。 ３、前記シートの露出面にはあらかじめマーク表示が成
されていることを特徴とする４１！Ｐ１／ｆ軸求の範囲
第２項記載のレジン封圧型半導体装置の製造方法。[Scope of Claims] L A wiring board, a semiconductor element fixed to the main surface of the wiring board, a conducting wire connecting an electrode of the semiconductor element to a wiring layer of the wiring board, and a conductive wire that covers the conducting wire and the semiconductor element. A resin-sealed semiconductor device comprising a sealing resin attached to the main surface of a wiring board, characterized in that an insulating sheet is attached to the upper surface of the sealing resin. Stop type semiconductor device. 2. A fixing step of fixing the semiconductor element to the main surface of the wiring board, a connecting step of connecting the electrode of the semiconductor element and the wiring layer of the wiring board with a conductive wire, and wiring the resin so as to cover the semiconductor element and the conductor wire. A method for manufacturing a resin-encapsulated semiconductor device comprising a coating step of coating the main surface of a substrate, and a curing step of curing the resin. 3. A method for manufacturing a resin-sealed semiconductor device, characterized in that the resin is cured after being placed on the sheet. 3. A mark is displayed on the exposed surface of the sheet in advance. 41!P1 2. The method for manufacturing a resin-sealed semiconductor device according to item 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57065272A JPS58182854A (en) | 1982-04-21 | 1982-04-21 | Resin-sealed semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57065272A JPS58182854A (en) | 1982-04-21 | 1982-04-21 | Resin-sealed semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58182854A true JPS58182854A (en) | 1983-10-25 |
Family
ID=13282119
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57065272A Pending JPS58182854A (en) | 1982-04-21 | 1982-04-21 | Resin-sealed semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58182854A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62101053A (en) * | 1985-10-28 | 1987-05-11 | Toshiba Corp | Thin type electronic circuit unit |
| JPS62183151A (en) * | 1986-02-06 | 1987-08-11 | Hitachi Maxell Ltd | Semiconductor device |
| US5098630A (en) * | 1985-03-08 | 1992-03-24 | Olympus Optical Co., Ltd. | Method of molding a solid state image pickup device |
| CN104051362A (en) * | 2013-03-14 | 2014-09-17 | 英飞凌科技奥地利有限公司 | Semiconductor Package with Top-Side Insulation Layer |
-
1982
- 1982-04-21 JP JP57065272A patent/JPS58182854A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5098630A (en) * | 1985-03-08 | 1992-03-24 | Olympus Optical Co., Ltd. | Method of molding a solid state image pickup device |
| JPS62101053A (en) * | 1985-10-28 | 1987-05-11 | Toshiba Corp | Thin type electronic circuit unit |
| JPH0410743B2 (en) * | 1985-10-28 | 1992-02-26 | ||
| JPS62183151A (en) * | 1986-02-06 | 1987-08-11 | Hitachi Maxell Ltd | Semiconductor device |
| CN104051362A (en) * | 2013-03-14 | 2014-09-17 | 英飞凌科技奥地利有限公司 | Semiconductor Package with Top-Side Insulation Layer |
| DE102014103432B4 (en) | 2013-03-14 | 2021-08-12 | Infineon Technologies Austria Ag | Semiconductor package with top-side insulating layer and method for manufacturing the same |
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