JPS62108554A - Hybrid integrated circuit device and manufacture thereof - Google Patents
Hybrid integrated circuit device and manufacture thereofInfo
- Publication number
- JPS62108554A JPS62108554A JP24947185A JP24947185A JPS62108554A JP S62108554 A JPS62108554 A JP S62108554A JP 24947185 A JP24947185 A JP 24947185A JP 24947185 A JP24947185 A JP 24947185A JP S62108554 A JPS62108554 A JP S62108554A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- resin
- coating
- substrate
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明達混成集積回路装置及びその製造方法に関し、特
に樹脂封止外装を簡略化した混成集積回路装置及びその
製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a hybrid integrated circuit device and a method for manufacturing the same, and particularly to a hybrid integrated circuit device with a simplified resin-sealed exterior and a method for manufacturing the same.
従来の混成集積回路装置はセラミック基板をベースにし
たものが主流であり、半導体チップを搭載した場合は、
まず半導体チップの保護コートを行い、最後に外装コー
トを行っている。セラミック基板以外の基板を用いた場
合も同様である４次に、従来のセラミック基板を用いた
混成集積回路の製造方法を第２図（ａ）〜（ｅ）により
説明する。Conventional hybrid integrated circuit devices are mainly based on ceramic substrates, and when equipped with semiconductor chips,
First, a protective coating is applied to the semiconductor chip, and finally an exterior coating is applied. The same applies to the case where a substrate other than a ceramic substrate is used.Fourth, a method of manufacturing a hybrid integrated circuit using a conventional ceramic substrate will be explained with reference to FIGS. 2(a) to 2(e).
まず、第２図（ａ）に示すように配線の形成されたセラ
ミック基板の上に半導体チップ２を付着し、次いでボン
ディングワイヤ５により配線する。First, as shown in FIG. 2(a), a semiconductor chip 2 is attached onto a ceramic substrate on which wiring is formed, and then wiring is made using bonding wires 5.
次に、第２図（ｂ）に示すように半導体チップ保護コー
ト樹脂７により半導体チップ２をコーティングする。次
に、第２図（ｃ）に示すように搭載部品３を付着すると
共に外部リード４をとりつける。次に、第２１ｇ（ｄ）
に示すように、半導体チップ２や搭載部品３を搭載した
セラミック基板をバッファコート樹脂によりコーティン
グする。しかる後最後に外装樹脂６により全体を封止す
るとセラミック基板を用いた従来の混成集積回路装置は
完成する。Next, as shown in FIG. 2(b), the semiconductor chip 2 is coated with a semiconductor chip protective coating resin 7. Next, as shown in FIG. 2(c), mounting parts 3 are attached and external leads 4 are attached. Next, 21st g(d)
As shown in FIG. 2, a ceramic substrate on which a semiconductor chip 2 and mounting components 3 are mounted is coated with a buffer coat resin. After that, the whole is finally sealed with an exterior resin 6, and a conventional hybrid integrated circuit device using a ceramic substrate is completed.
上述した従来のセラミック基板を用いた混成集積回路装
置の製法では半導体チップ実装後まず保護コートを行な
い、次いで製品構造によっては部品実装後、基板の膜回
路を保護するために基板全体をシリコン樹脂等で薄くコ
ーティングし、最後に外装樹脂をコーティングするプロ
セスがとられている。In the conventional manufacturing method for hybrid integrated circuit devices using ceramic substrates as described above, a protective coating is first applied after semiconductor chips are mounted, and then, depending on the product structure, after parts are mounted, the entire substrate is coated with silicone resin, etc. to protect the film circuits on the board. The process is to apply a thin layer of paint, and then finally coat the exterior with resin.
一般のトランスファモールド等でパッケージされた半導
体集積回路ではリードフレームに半導体チップを実装後
１回の樹脂封止で完成されており混成集積回路装置では
１回又は２回多く樹脂コーティング工程があり工程並び
に価格面から見て不利である。Semiconductor integrated circuits packaged by general transfer molding etc. are completed with one resin sealing after mounting the semiconductor chip on a lead frame, while hybrid integrated circuit devices require one or two more resin coating steps. This is disadvantageous from a price point of view.
ところが、セラミックを基板に用いた混成集積回路装置
では、エポキシ樹脂等の外装樹脂と基板の熱膨張係数が
一桁違うため耐熱試験を行うと半導体チップ２のボンデ
ィングワイヤ５の断線又はセラミック基板上の膜回路の
クラック、剥離等の不具合が発生しやすいという欠点が
あった。However, in a hybrid integrated circuit device using a ceramic substrate, the coefficient of thermal expansion of the exterior resin such as epoxy resin and the substrate are different by one order of magnitude, so when a heat resistance test is performed, the bonding wire 5 of the semiconductor chip 2 may be disconnected or the ceramic substrate may be disconnected. It has the disadvantage that defects such as cracking and peeling of the membrane circuit are likely to occur.
本発明の目的は、混成集積回路の製造工程の簡略化、短
納期化及び資材の低減を可能とし得る混成集積回路装置
及びその製造方法を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a hybrid integrated circuit device and a method for manufacturing the same that can simplify the manufacturing process of a hybrid integrated circuit, shorten the delivery time, and reduce the amount of materials used.
本発明の第１の発明の混成集積回路装置は、熱膨張係数
が外装樹脂と近いガラスエポキシ等を素材としたプリン
ト板よりなる基板と、該基板上に少なくとも直接搭載さ
れた半導体チップと、該半導体チップを保護コーティン
グすることなくコーティングされた外装樹脂とを含んで
構成される。A hybrid integrated circuit device according to a first aspect of the present invention includes a substrate made of a printed board made of glass epoxy or the like having a coefficient of thermal expansion close to that of an exterior resin, a semiconductor chip mounted at least directly on the substrate, and a semiconductor chip mounted at least directly on the substrate. It is composed of a semiconductor chip coated with an exterior resin without a protective coating.
また、本発明の第２の発明の混成集積回路装置の製造方
法は、熱膨張係数が外装樹脂に近いガラスエポキシ等を
素材としたプリント板よりなる基板にリードを挿入する
工程と、半導体チップ及びその他の部品をはんだ等で実
装する工程と、半導体チップをボンディングする工程と
、該半導体チップに保護コーティングすることなく外装
樹脂をコーディングする工程とを含んで構成される。Further, the method for manufacturing a hybrid integrated circuit device according to the second aspect of the present invention includes a step of inserting leads into a substrate made of a printed board made of glass epoxy or the like having a coefficient of thermal expansion close to that of the exterior resin; The method includes a step of mounting other components with solder or the like, a step of bonding the semiconductor chip, and a step of coating the semiconductor chip with an exterior resin without applying a protective coating.
次に、本発明の実施例について図面を参照して説明する
。第１図（ａ）〜（ｃ）は本発明の一実施例並びにその
製造方法を説明するために工程順に示した断面図である
。Next, embodiments of the present invention will be described with reference to the drawings. FIGS. 1(a) to 1(c) are cross-sectional views shown in the order of steps to explain an embodiment of the present invention and its manufacturing method.
まず、第１図（ａ）に示すように、外部リード４をガラ
スエポキシ基板１に挿入し、半導体チッ１２、搭載部品
（図では積層セラミックコンデンサを図示）３及び外部
リード４を接続する材料（。First, as shown in FIG. 1(a), the external leads 4 are inserted into the glass epoxy substrate 1, and the material ( .
はんだ又はＡ８ペースト等）を印刷又は塗布等で塗布す
る０次に半導体チップ２１部品３を実装する。The semiconductor chip 21 component 3 is mounted on the 0th order by applying solder, A8 paste, etc.) by printing or coating.
接着材料としてはんだを使用する場合ははんだリフロー
、洗浄を実施し、Ａ８ペーストを使用する場合はＡ、１
ペーストの焼成を行なう。When using solder as an adhesive material, perform solder reflow and cleaning, and when using A8 paste, use A, 1.
Bake the paste.
次に、第１図（ｂ）に示すように、半導体チップ２１部
品３実装後、半導体チップのワイヤボンディングをボン
ディングワイヤ５で１００〜１５０℃の低温で行なう。Next, as shown in FIG. 1(b), after the semiconductor chip 21 and the components 3 are mounted, wire bonding of the semiconductor chip is performed using bonding wires 5 at a low temperature of 100 to 150°C.
Ｆｔ後に、第１図（ｃ）に示すように、外装樹脂６で全
体を被覆する。図ではエポキシのパウダーコーティング
の例を示している。ガラスエポキシ基板１と外装のエポ
キシ樹脂６の熱膨張に１％数はほぼ同様であるため、温
度サイクル試験等耐熱試験を行なっても信頼性上不具合
いは発生しない。またエポキシ樹脂の不純物含有量の小
さいもの（不純物含有量で数１０ρＰａ１以下）を使用
すれば耐湿試験にて半導体チップ２に悪影響を与えるこ
とはない。After Ft, the entire structure is covered with an exterior resin 6, as shown in FIG. 1(c). The figure shows an example of epoxy powder coating. Since the glass epoxy substrate 1 and the exterior epoxy resin 6 have almost the same thermal expansion ratio of 1%, no defects in reliability will occur even if a heat resistance test such as a temperature cycle test is performed. Furthermore, if an epoxy resin with a small impurity content (impurity content of several tens of ρPa1 or less) is used, the semiconductor chip 2 will not be adversely affected in the moisture resistance test.
なお、外装樹脂としてはフェノール、シリコン等でもよ
いし、外装はパウダーコーティング以外ディッピング、
トランスファモールド等でもよい。The exterior resin may be phenol, silicone, etc., and the exterior may be coated with dipping, coating, etc. other than powder coating.
Transfer molding or the like may also be used.
以上説明したように本発明は基板をセラミックからガラ
スエポキシに変更し、製造工程を変更することにより、
工程が簡略化、短縮し、材料に関しては、半導体チップ
コート樹脂及び基板全体を薄くコーティングする（バッ
ファコートと呼ぶ）樹脂を削除することができる。As explained above, the present invention changes the substrate from ceramic to glass epoxy and changes the manufacturing process.
The process is simplified and shortened, and in terms of materials, it is possible to eliminate the semiconductor chip coating resin and the resin that thinly coats the entire substrate (referred to as a buffer coat).
第１図（ａ）〜（ｃ）は本発明の一実施例及びその製造
方法を説明するために工程順に示した断面図、第２図（
ａ）〜（ｅ）は従来の混成集積回路装置及びその製造方
法を説明するために工程順に示した断面図である。
１・・・ガラスエポキシ基板、２・・・半導体チップ、
３・・・搭載部品、４・・・外部リード、５・・・ボン
ディングワイヤ、６・・・外装樹脂、７・・・半導体チ
ップ保護コート樹脂、８・・・セラミック基板、９・・
・バッファコート樹脂。
ＩｊＪす７工本°キシ屋４に
＄ １ 回FIGS. 1(a) to (c) are cross-sectional views shown in the order of steps to explain one embodiment of the present invention and its manufacturing method, and FIG.
1A to 1E are cross-sectional views shown in the order of steps for explaining a conventional hybrid integrated circuit device and its manufacturing method. 1...Glass epoxy substrate, 2...Semiconductor chip,
3... Mounted components, 4... External leads, 5... Bonding wires, 6... Exterior resin, 7... Semiconductor chip protective coating resin, 8... Ceramic substrate, 9...
・Buffer coat resin. IjJsu 7 engineering book ° Kishiya 4 $ 1 time
Claims (2)
素材としたプリント板よりなる基板と、該基板上に少な
くとも直接搭載された半導体チップと、該半導体チップ
を保護コーティングすることなくコーティングされた外
装樹脂とを含むことを特徴とする混成集積回路装置。(1) A substrate made of a printed board made of glass epoxy or the like with a coefficient of thermal expansion close to that of the exterior resin, a semiconductor chip mounted at least directly on the substrate, and a semiconductor chip coated without a protective coating. A hybrid integrated circuit device comprising an exterior resin.
素材としたプリント板よりなる基板にリードを挿入する
工程と、半導体チップ及びその他の部品をはんだ等で実
装する工程と、半導体チップをボンディングする工程と
、該半導体チップに保護コーティングすることなく外装
樹脂をコーティングする工程とを含むことを特徴とする
混成集積回路装置の製造方法。(2) The process of inserting leads into a board made of a printed board made of glass epoxy, etc. whose thermal expansion coefficient is close to that of the exterior resin, the process of mounting semiconductor chips and other components with solder, etc., and the process of bonding semiconductor chips 1. A method for manufacturing a hybrid integrated circuit device, comprising the steps of: coating the semiconductor chip with an exterior resin without applying a protective coating to the semiconductor chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24947185A JPS62108554A (en) | 1985-11-06 | 1985-11-06 | Hybrid integrated circuit device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24947185A JPS62108554A (en) | 1985-11-06 | 1985-11-06 | Hybrid integrated circuit device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62108554A true JPS62108554A (en) | 1987-05-19 |
Family
ID=17193448
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24947185A Pending JPS62108554A (en) | 1985-11-06 | 1985-11-06 | Hybrid integrated circuit device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62108554A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63302709A (en) * | 1987-05-30 | 1988-12-09 | Furukawa Electric Co Ltd:The | Electrical connection box incorporating electronic circuitry |
| JPH02105446A (en) * | 1988-10-13 | 1990-04-18 | Nec Corp | Hybrid integrated circuit |
| JP2004055846A (en) * | 2002-07-19 | 2004-02-19 | Matsushita Electric Works Ltd | Method for isolating wiring pattern of printed wiring board and fire detector equipped with printed wiring board whose wiring pattern is isolated thereby |
-
1985
- 1985-11-06 JP JP24947185A patent/JPS62108554A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63302709A (en) * | 1987-05-30 | 1988-12-09 | Furukawa Electric Co Ltd:The | Electrical connection box incorporating electronic circuitry |
| JPH02105446A (en) * | 1988-10-13 | 1990-04-18 | Nec Corp | Hybrid integrated circuit |
| JP2004055846A (en) * | 2002-07-19 | 2004-02-19 | Matsushita Electric Works Ltd | Method for isolating wiring pattern of printed wiring board and fire detector equipped with printed wiring board whose wiring pattern is isolated thereby |
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