JPS62101053A - Thin type electronic circuit unit - Google Patents

Thin type electronic circuit unit

Info

Publication number
JPS62101053A
JPS62101053A JP60241159A JP24115985A JPS62101053A JP S62101053 A JPS62101053 A JP S62101053A JP 60241159 A JP60241159 A JP 60241159A JP 24115985 A JP24115985 A JP 24115985A JP S62101053 A JPS62101053 A JP S62101053A
Authority
JP
Japan
Prior art keywords
sealing resin
chip
wiring substrate
substrate
electronic circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60241159A
Other languages
Japanese (ja)
Other versions
JPH0410743B2 (en
Inventor
Yoshitaka Fukuoka
義孝 福岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP60241159A priority Critical patent/JPS62101053A/en
Publication of JPS62101053A publication Critical patent/JPS62101053A/en
Publication of JPH0410743B2 publication Critical patent/JPH0410743B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PURPOSE:To inhibit the deformation of a wiring substrate due to a temperature cycle, and to prevent the accident, etc. of the disconnection of a bonding wire by coating the outside of an IC chip on the wiring substrate with a sealing resin and laminating a substrate for coating onto the sealing resin. CONSTITUTION:The whole mounting surface of a wiring substrate 5 containing the outside of an IC chip 6 is coated with a sealing resin 8, such as an epoxy resin, a silicone resin, etc. A substrate 9 for coating, which consists of the same base material as the wiring substrate 5 and has thickness of 0.1-0.8mm, is laminated onto the sealing resin 8. Since structure in which the sealing resin having a different thermal expansion coefficient is held between the comparatively thin and flexible wiring substrate and the substrate 9 for coating composed of the same base material and the IC chip 6 is buried into the sealing resin 8 is formed, the wiring substrate 5 is not warped and deformed even when a temperature cycle and a thermal shock are applied, thus generating no defective connection and disconnection due to the application of tension and compressive force to connecting sections, etc. for bonding wires.

Description

【発明の詳細な説明】 ［発明の技術分野］ 本発明は、ＩＣチップを内蔵した簿型電子回路ユニット
に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a book-shaped electronic circuit unit incorporating an IC chip.

［発明の技術向背Ｈ］ 近年、ＩＣカード、ゲームカード、薄型型１σ等の電子
機器に使用するため、ＩＣチップを内蔵した薄型電子回
路ユニットの需要が増大しつつある。[Technical Background of the Invention H] In recent years, the demand for thin electronic circuit units with built-in IC chips has been increasing for use in electronic devices such as IC cards, game cards, and thin 1σ type devices.

従来からこのような薄型重子回路ユニットとしては、第
４図に示すように表面に導体パターン（図示を省略）が
形成された、ガラスーエボーｔシ、紙−エポキシ、紙−
フ１ノール、ポリミド等の基材からなる配線基板１上の
所定の位行にＩ　Ｃチップ２をグイボンドし、これをＡ
ｌｌ線等のボンディングワイヤ３で導体パターンとセス
的に接続するとともに、このＩＣデツプ２の外側をエポ
キシ樹脂やシリコーン樹脂のような封庄用樹脂４７：封
１トした構）省の回路ユニットが用いられていた。Conventionally, such thin multilayer circuit units include glass-evo t, paper-epoxy, and paper-epoxy, which have a conductor pattern (not shown) formed on the surface as shown in FIG.
An IC chip 2 is bonded to a predetermined position and row on a wiring board 1 made of a base material such as phenol or polymide, and then
A circuit unit is connected to the conductor pattern with a bonding wire 3 such as a ll wire, and the outside of the IC depth 2 is sealed with a sealing resin 47 such as epoxy resin or silicone resin. It was used.

［背慎技術の問題点］ このような構造の薄型電子回路ユニットにＪ５いては、
配線基板１を構成する基８の熱膨張係数（１，０〜１，
８Ｘ　４０−５／　’Ｃ）と１４止用樹脂４の熱膨張係
数（２，０〜６．ＯＸ　１０’　／　℃）が大きく異な
り、′しかも配１５Ａ基板１の厚さが０．２〜０．８ｍ
ｉと比較的薄いものとなっている。このため、低温−高
温の温度サイクルを繰り返したり熱衝撃を加えた場合、
配線基板１の反り、復帰のサイクルが繰り返されること
になり、これによって、封止用樹脂４内に埋めこまれた
ボンディングワイヤ３に張ノコや圧縮力が加わって、接
続不良や断線が生じるおそれがあった。[Problems with unscrupulous technology] J5 is a thin electronic circuit unit with such a structure.
Thermal expansion coefficient (1,0 to 1,
The coefficient of thermal expansion (2.0 to 6.OX 10'/°C) of the resin 4 for fixing 14 and 14 is significantly different, and the thickness of the 15A substrate 1 is 0.2 to .8m
i and is relatively thin. For this reason, if the temperature cycle between low and high temperatures is repeated or thermal shock is applied,
The cycle of warping and returning of the wiring board 1 will be repeated, and as a result, the bonding wire 3 embedded in the sealing resin 4 will be subjected to compressive force and there is a risk of connection failure or disconnection. was there.

［発明の目的］ 本発明は、このような従来の問題を解決するためになさ
れたもので、温度変化による配線基板の変形が抑えられ
た信頼性の高い薄型電子回路ユニットを提供することを
目的とする。[Object of the Invention] The present invention has been made to solve such conventional problems, and an object of the present invention is to provide a highly reliable thin electronic circuit unit in which deformation of the wiring board due to temperature changes is suppressed. shall be.

［発明の概要］ すなわち本発明の薄型電子回路ユニットは、表面に導体
パターンが形成された配線基板上にＩＣチップを実装す
るとともに、このＩＣチップの外側を封止用樹脂で覆い
、ざらに該封止用樹脂の上に前記配線基板と同じ基材か
らなる被覆用基板を積層することにより、温度サイクル
による配線基板の変形を抑えボンディングワイヤの断線
事故等を防止したものである。[Summary of the Invention] That is, the thin electronic circuit unit of the present invention includes an IC chip mounted on a wiring board having a conductive pattern formed on its surface, and the outside of the IC chip is covered with a sealing resin to roughly seal the area. By laminating a covering substrate made of the same base material as the wiring board on top of the sealing resin, deformation of the wiring board due to temperature cycles is suppressed and accidents such as disconnection of bonding wires are prevented.

［発明の実施例１ 以下本発明を図面に示ず実施例について説明する。[Embodiment 1 of the invention DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to embodiments, which are not shown in the drawings.

第１図は本発明の薄型電子回路ユニットの一実施例の断
面図である。FIG. 1 is a sectional view of an embodiment of a thin electronic circuit unit of the present invention.

この図において、符号５はガラス−エポキシ、紙−エポ
キシ、紙−フェノール、ポリイミド等のフレキシブルな
基材からなり、片面に印刷法等により導体パターンが形
成された、厚さが０．１〜０．８■の配線基板を示して
いる。この配線基板５の導体パターン上にはＩＣチップ
６が搭載さ−れており、ＩＣチップ６のインナーパッド
と導体パターンとはＡＬＬ線や／１線のようなボンディ
ングワイヤ７で電気的に接続されている。In this figure, reference numeral 5 is made of a flexible base material such as glass-epoxy, paper-epoxy, paper-phenol, polyimide, etc., and has a conductor pattern formed on one side by a printing method, etc., and has a thickness of 0.1 to 0. .8■ wiring board is shown. An IC chip 6 is mounted on the conductor pattern of the wiring board 5, and the inner pad of the IC chip 6 and the conductor pattern are electrically connected by a bonding wire 7 such as an ALL wire or a /1 wire. ing.

また、このようなＩＣチップ６の外側を含む配線基板５
の実装面全体には、エポキシ樹脂、シリコーン樹脂等の
封止用樹脂８が被覆されている。Further, a wiring board 5 including the outside of such an IC chip 6
The entire mounting surface of is coated with a sealing resin 8 such as epoxy resin or silicone resin.

ざらに封止用樹脂８の上には、配線基板５と同じ基材か
らなり厚さが０．１〜０，８ｍｉの被覆用基板９がｇＩ
層されている。A coating substrate 9 made of the same base material as the wiring board 5 and having a thickness of 0.1 to 0.8 mm is placed on the rough sealing resin 8.
Layered.

このよ、うに構成される実施例の薄型電子回路ユニット
においては、同じ基材からなる比較的薄くてフレキシブ
ルな配線基板と被覆用基板９で熱膨張係数の異なる封止
用樹脂が挾み込まれており、かつこの封止用樹脂８内に
ＩＣチップ６がＪ！ｌ！設された構造になっているので
、温度サイクルや熱衝撃が加えられてｂ配ＰＪ暴板５の
反りゃ変形が生じるようなことがなく、従っでボンディ
ングワイヤの接続部等に張力や圧縮力が加わり接続不良
や断線が生じることがない。In the thin electronic circuit unit of the embodiment configured as described above, sealing resins having different coefficients of thermal expansion are sandwiched between a relatively thin and flexible wiring board and a covering board 9 made of the same base material. and the IC chip 6 is placed inside this sealing resin 8. l! This structure prevents the PJ board 5 from warping or deforming due to temperature cycles or thermal shocks, and therefore prevents tension and compression from bonding wire connections, etc. This prevents connection failures and disconnections.

次に本発明の別の実施例を第２図ないし第３図にそれぞ
れ示す。これらの図において、第１図と共通する部分に
は同じ符号を付し説明を省略する。Next, other embodiments of the present invention are shown in FIGS. 2 and 3, respectively. In these figures, parts common to those in FIG. 1 are designated by the same reference numerals, and explanations thereof will be omitted.

第２図においては、フレキシブルな絶縁基板の少くとも
片面の仝休に、導体膜あるいは導体箔のような導電層１
０が形成されて被覆用基板９が構成されており、かつこ
の導電層１０はＧＮＤ電位に保持されている。In FIG. 2, a conductive layer 1 such as a conductive film or conductive foil is provided on at least one side of the flexible insulating substrate.
0 is formed to constitute the covering substrate 9, and this conductive layer 10 is held at the GND potential.

このように構成される実施例の薄型電子回路ユニットに
おいては、前記の特長の他に耐ノイズ特性に優れている
という利点を有する。In addition to the above-mentioned features, the thin electronic circuit unit of the embodiment configured as described above has an advantage of excellent noise resistance.

また第３図に示す実施例では、封止用樹脂８が、配置ｉ
板全体ではなくＩＣチップ６の周囲のみに被着されてお
り、その上にＩＣチップ６およびボンディングワイヤ７
を覆う大きざの被覆用基板９が積層された構造となって
いる。この実施例においては、材料コストおよびスペー
スをできるだけ節約しつつ初期の目的を達成することが
できる。Further, in the embodiment shown in FIG. 3, the sealing resin 8 is
It is not attached to the entire board but only around the IC chip 6, and the IC chip 6 and bonding wires 7 are placed on top of it.
It has a structure in which covering substrates 9 having a size that covers the layers are laminated. In this embodiment, the initial objective can be achieved while saving material costs and space as much as possible.

なお、以上の実施例では１個のＩＣチップ６が実装され
た例につい°τ説明したが、本発明はこのような実施例
に限定されるものではなく、複数のＩＣチップ６が同じ
配線基板５上に実装されたユニットについても同様に構
成することができる。In the above embodiment, an example in which one IC chip 6 is mounted has been described, but the present invention is not limited to such an embodiment, and a plurality of IC chips 6 are mounted on the same wiring board. A similar configuration can be applied to a unit mounted on 5.

［発明の効果コ 以上の説明から明らかなように、本発明の薄型電子回路
ユニットは、熱膨張係数が比較的大きい１１止用樹脂の
内部にＩＣチップを１４止し、その両側にこれと熱膨張
係数が異なりかつ同じ基材からなる配線基板と被覆用基
板とを積層して構成されているので、温度サイクル等に
よる配線基板の変形Ｊ−３よびそれに伴なうボンディン
グワイヤの断線等がなく、信頼性の高いものである。[Effects of the Invention] As is clear from the above explanation, the thin electronic circuit unit of the present invention has 14 IC chips fixed inside a 11 fixing resin having a relatively large coefficient of thermal expansion, and heat conductors on both sides of the IC chip. Since it is constructed by laminating the wiring board and the covering board, which have different expansion coefficients and are made of the same base material, there is no deformation of the wiring board due to temperature cycles, etc., and there is no accompanying breakage of the bonding wire. , is highly reliable.

【図面の簡単な説明】[Brief explanation of drawings]

第１図４【いし第３図はそれぞれ本発明の薄型電子回路
ユニットの実施例の断面図、第４図は従来の薄型電子回
路ユニツ１−の断面図である。 １．５・・・・・・配線基板 ２．６・・・・・・ＩＣチップ ３．７・・・・・・ボンディングワイヤ４．８・・・・
・・村山用樹脂 ９・・・・・・・・・・・・被覆用基板１０・・・・・
・・・・導電層 出願人　　　　　　株式会社　東芝 代理人　弁理士　　須　山　佐　− 第１図 粥　２図 第３図 第４図FIGS. 1-4 are sectional views of embodiments of the thin electronic circuit unit of the present invention, and FIG. 4 is a sectional view of a conventional thin electronic circuit unit 1-. 1.5... Wiring board 2.6... IC chip 3.7... Bonding wire 4.8...
...Resin 9 for Murayama......Covering substrate 10...
... Conductive layer applicant Toshiba Corporation Patent attorney Sa Suyama - Figure 1 Congee Figure 2 Figure 3 Figure 4

Claims (3)

【特許請求の範囲】[Claims] （１）表面に導体パターンが形成された配線基板上にＩ
Ｃチップを実装するとともに、このＩＣチップの外側を
封止用樹脂で覆い、さらに該封止用樹脂の上に前記配線
基板と同じ基材からなる被覆用基板を積層して成ること
を特徴とする薄型電子回路ユニット。(1) I
A C chip is mounted, the outside of this IC chip is covered with a sealing resin, and a covering substrate made of the same base material as the wiring board is further laminated on the sealing resin. A thin electronic circuit unit. （２）配線基板および被覆用基板が、いずれもフレキシ
ブルな基板であることを特徴とする特許請求の範囲第１
項記載の薄型電子回路ユニット。(2) Claim 1, characterized in that both the wiring board and the covering board are flexible boards.
The thin electronic circuit unit described in Section 1. （３）被覆用基板の片面あるいは両面の全体に導電層が
形成され、かつこの導電層がＧＮＤ電位に保たれている
ことを特徴とする特許請求の範囲第１項記載の薄型電子
回路ユニット。(3) A thin electronic circuit unit according to claim 1, characterized in that a conductive layer is formed on one or both surfaces of the covering substrate, and the conductive layer is maintained at a GND potential.
JP60241159A 1985-10-28 1985-10-28 Thin type electronic circuit unit Granted JPS62101053A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60241159A JPS62101053A (en) 1985-10-28 1985-10-28 Thin type electronic circuit unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60241159A JPS62101053A (en) 1985-10-28 1985-10-28 Thin type electronic circuit unit

Publications (2)

Publication Number Publication Date
JPS62101053A true JPS62101053A (en) 1987-05-11
JPH0410743B2 JPH0410743B2 (en) 1992-02-26

Family

ID=17070137

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60241159A Granted JPS62101053A (en) 1985-10-28 1985-10-28 Thin type electronic circuit unit

Country Status (1)

Country Link
JP (1) JPS62101053A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999028969A1 (en) * 1997-12-03 1999-06-10 Advanced Micro Devices, Inc. Integrated circuit chip package and method of making the same
JP2008153601A (en) * 2006-12-20 2008-07-03 Fujitsu Ltd Mounting structure and semiconductor device
JP2017204494A (en) * 2016-05-09 2017-11-16 オリンパス株式会社 Electronic substrate for medical equipment

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58182854A (en) * 1982-04-21 1983-10-25 Hitachi Ltd Resin-sealed semiconductor device and manufacture thereof
JPS5988853A (en) * 1982-11-12 1984-05-22 Nec Corp Package of large scaled integrated circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58182854A (en) * 1982-04-21 1983-10-25 Hitachi Ltd Resin-sealed semiconductor device and manufacture thereof
JPS5988853A (en) * 1982-11-12 1984-05-22 Nec Corp Package of large scaled integrated circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999028969A1 (en) * 1997-12-03 1999-06-10 Advanced Micro Devices, Inc. Integrated circuit chip package and method of making the same
US6124546A (en) * 1997-12-03 2000-09-26 Advanced Micro Devices, Inc. Integrated circuit chip package and method of making the same
JP2008153601A (en) * 2006-12-20 2008-07-03 Fujitsu Ltd Mounting structure and semiconductor device
JP2017204494A (en) * 2016-05-09 2017-11-16 オリンパス株式会社 Electronic substrate for medical equipment

Also Published As

Publication number Publication date
JPH0410743B2 (en) 1992-02-26

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