JPS58182768A - History recording system - Google Patents

Abstract

PURPOSE:To realize a history recording system of an instruction that requires no high-speed operation of real time and without losing the instruction information, by inhibiting the execution of an instruction until the collection of instruction information is through. CONSTITUTION:A history recording system is connected to a central processor 1 via an input/output bus 2. This recording system comprises a bus interface circuit 4 which produces an instruction information signal A1, an instruction reception information signal A2 and a busy informing signal A10, a history recording indicating flip-flop FF5 which delivers a history recording indicating signal A3, a history recording controller 6 which generates an instruction execution enable signal A5, two AND gate circuits 7 and 8, an instruction information recording circuit 9 which receives a recording start indication A6 to perform collection and recording of the instruction information A1 and then delivers a collection end informing signal A8, and an instruction execution processing circuit 10 which executes an instruction with an instruction execution start indicating signal A9, i.e., the output of the gate 8 and then delivers an instruction process end informing signal A9 after the execution of the instruction.

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD The present invention relates to an instruction history recording method in a data processing device.

Prior Art Conventionally, in this type of instruction history recording system, a circuit for monitoring the acceptance of instructions and recording information on generated instructions and a circuit for executing instructions are provided independently. A method of performing both at the same time has been widely adopted. In this method, the instruction history recording circuit needs to complete recording in real time before instruction information is lost. That is, the collection of instruction information must be completed before the instruction execution processing circuit finishes processing the instruction and starts processing the next instruction. Therefore, it is necessary to design the history recording circuit in accordance with the shortest instruction execution processing time, and the circuit must often be made faster. As a result, the hardware becomes expensive and power consumption increases. Another disadvantage is that there is a risk of failure in collecting command information.

OBJECTS OF THE INVENTION It is an object of the present invention to provide a method for recording the history of instructions, which eliminates the above-mentioned drawbacks.

Structure of the Invention The method of the present invention includes: a display means for indicating that an external command has been accepted; an instruction means for instructing to record the history of the command; an acceptance display by the display means; and an instruction by the instruction means. stop instruction means for instructing to stop the execution of the instruction in response; recording means for recording the instruction in response to the stop of execution by the stop instruction means; and recording means for recording the stopped instruction after being recorded by the recording means. and means for instructing to restart execution.

Embodiments of the Invention Next, the present invention will be described in detail with reference to the drawings. Referring to the figure, one embodiment of the present invention includes a bus interface circuit that is connected to a central processing unit 1 via an input/output bus 2 and generates instruction information A1, an instruction acceptance notification signal A2, and a busy notification signal AIO. 4. History recording instruction signal A
A history recording instruction flip-flop (F/F'
)5. Command acceptance notification signal A2 and command history recording instruction signal A
6. A history recording control flip-flop (F/F) that generates a recording enable signal A4 and an instruction execution enable signal A5 which is its inverted logic signal based on 3. Two AND gate circuits 7 and 8. The command information recording circuit 9° receives the recording start instruction signal A6 which is the output of the AND gate circuit 7, collects and records the command information A1, and outputs 8 as the collection completion notification signal, and the command which is the output of the AND gate 8. The instruction execution processing circuit 10 executes instruction execution processing in response to an execution start instruction signal A9, and outputs an instruction processing completion notification signal A9 after completion.

Next, the operation of the embodiment of the present invention shown in FIG. 1 will be described in detail. When the command supplied by the central processing unit 1 to the peripheral control device 3 via the input/output bus 2 is set in the bus interface circuit 4, the circuit 4 outputs the command information A1 and at the same time outputs the command acceptance notification signal A2 to 1. ”. At the same time, the busy notification signal AIO number informs the central processing unit 1 that the instruction is being executed. Whether or not to record the history of the instruction information is determined by the history recording instruction F/F.
This can be specified by setting or resetting 5. If command history recording is not required, history recording instruction F/F 5
is reset, and the history recording instruction signal = 5-A3 becomes °゛0''. The command acceptance notification signal A2 becomes “1”
In response to this, the value of the history recording instruction signal A3 is stored in the history recording control F/F6. That is, the recording enable signal A4 becomes ``O'''', the recording start instruction signal A6, which is the output of the AND gate circuit 7, also becomes ``O'', and the command information recording circuit 9 does not operate. Since A5 becomes "1'", the input condition of the AND gate circuit 8 is satisfied. In response to the instruction execution start instruction signal A7 of 1"', the instruction execution processing circuit 10 starts operating and transmits the instruction information A1. Input and execute commands. When the processing is completed, an instruction execution completion notification signal A9 is output to the bus interface circuit 4, and the instruction acceptance notification signal A2 and busy notification signal AIO are reset to prepare for acceptance of the next instruction. If you want to record the history of commands, use the B history recording instruction F/F.
5 is set, and the history recording instruction signal A3 is It, 11.
become. Command acceptance notification signal A.

When 2 becomes 1, the value of the history recording instruction signal A3 is stored in the history recording control F/F 6, the recording enable signal A4 becomes 1'', and the instruction execution enable signal 6-A5 becomes 0''. The instruction execution start instruction signal A7 of the AND gate circuit 8 becomes O'', and the instruction execution processing circuit 10 does not operate. The command information recording circuit 9 starts collecting command information A1. When the collection is completed, the command information recording circuit 9 outputs the collection completion notification signal A8, resets the history recording control F/F6, sets the recording enable signal A4 to ll011, and sets the command execution enable signal A5 to (
tl, set it to 7+. Note that the method of recording collected information in the activated command information recording circuit 9 is not directly related to the present invention and will therefore be omitted. The output of the AND gate circuit 7 becomes tlO#L, and instead, the instruction execution start instruction signal A7 of the AND gate circuit 8 is set to 1'', and the instruction execution processing circuit 10 operates in the same way as when there is no history recording instruction. and inputs the instruction information A1 to execute the instruction. When the processing is completed, the instruction execution completion notification signal A9 is output to the bus interface circuit 4, and the instruction acceptance notification signal A2 and the busy notification signal AIO are reset. to prepare for receiving the next command.

Incidentally, when the history recording control F/F 6 is reversed, whiskers may occur in the recording start instruction signal A6 and the instruction execution start instruction signal A6, but this is because the instruction information recording circuit 9 and the instruction execution processing It is removed by synchronizing in circuit 10.

Effects of the Invention The present invention realizes an instruction history recording method that does not require loss of instruction information and does not require high-speed real-time performance by prohibiting instruction execution processing until the collection of instruction information is completed. There is an effect that it can be done.

[Brief explanation of the drawing]

The figure shows an embodiment of the present invention.

Claims (1)

[Scope of Claims] Display means for indicating that an external command has been accepted, instruction means for instructing to record the history of the command, and response to the acceptance display by the display means and the instruction by the instruction means. a stop instructing means for instructing to stop the execution of the command; a recording means for recording the command in response to the stop of execution by the stop instructing means; and a recording means for recording the stopped command after recording according to the recording means number. A history recording method comprising means for instructing to restart execution.