JPS58182526U - timed circuit - Google Patents
timed circuitInfo
- Publication number
- JPS58182526U JPS58182526U JP7791382U JP7791382U JPS58182526U JP S58182526 U JPS58182526 U JP S58182526U JP 7791382 U JP7791382 U JP 7791382U JP 7791382 U JP7791382 U JP 7791382U JP S58182526 U JPS58182526 U JP S58182526U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- resistor
- capacitor
- timed circuit
- switching element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
」 第1図は従来の時限回路の電気回路図、第2図
り は本考案の一実施例による同電気回路図、第3図
シ は同容量の電圧と時間との関係を示す図である。
【 1・・・・・・電源、3. 6. 8. 9・
・曲抵抗、4・・曲V 容量、5・・・・・・スイッ
チング素子、7・・曲設定回路1、 10・・・・・・
ダ7fオード。Figure 1 is an electrical circuit diagram of a conventional timed circuit, Figure 2 is an electrical circuit diagram of the same according to an embodiment of the present invention, and Figure 3 C is a diagram showing the relationship between voltage and time for the same capacity. [1...Power supply, 3. 6. 8. 9・
- Song resistance, 4... Song V capacitance, 5... Switching element, 7... Song setting circuit 1, 10...
Da 7f ode.
Claims (1)
にスイッチング素子5と抵抗6の直列匡路を、更にスイ
ッチング素子5に設定回路7をぐ接続した時限回路にお
いて、抵抗3と容量4の拐続点をダイオード10を介し
て抵抗8.9に接わし、抵抗8,9の各他端を電源1の
両端に接続したことを特徴とする時限回路。In a time-limiting circuit in which a series circuit of a resistor 3 and a capacitor 4 is connected to a power supply 1, a series circuit of a switching element 5 and a resistor 6 is connected to both ends of a capacitor 14, and a setting circuit 7 is connected to the switching element 5. A timer circuit characterized in that a connection point of a capacitor 4 is connected to a resistor 8 and 9 via a diode 10, and the other ends of each of the resistors 8 and 9 are connected to both ends of a power source 1.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7791382U JPS58182526U (en) | 1982-05-27 | 1982-05-27 | timed circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7791382U JPS58182526U (en) | 1982-05-27 | 1982-05-27 | timed circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58182526U true JPS58182526U (en) | 1983-12-05 |
Family
ID=30087160
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7791382U Pending JPS58182526U (en) | 1982-05-27 | 1982-05-27 | timed circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58182526U (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5020556B1 (en) * | 1969-06-23 | 1975-07-16 |
-
1982
- 1982-05-27 JP JP7791382U patent/JPS58182526U/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5020556B1 (en) * | 1969-06-23 | 1975-07-16 |
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