JPS58125430U

JPS58125430U - timer circuit

Info

Publication number: JPS58125430U
Application number: JP2337782U
Authority: JP
Inventors: 博之田中
Original assignee: 松下電器産業株式会社
Priority date: 1982-02-19
Filing date: 1982-02-19
Publication date: 1983-08-26

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

゛　第１図は従来のタイマー回路の電気的結線図、第２
図は本考案のタイマー回路における一実施例の電気的結
線図、第３図は他の実施例の電気的結線図である。Ｑ１〜Ｑ４・・・・・・トランジスタ、Ｒａ、　Ｒｂ、
　Ｒ□〜Ｒ６・・・　　゛・・・抵抗、Ｃ１・・・・・
・コンデンサ、Ｄｌ・・・・・・ダイオード、Ｓｌ−□
・・・・・・スイッチ。゛ Figure 1 is an electrical wiring diagram of a conventional timer circuit, Figure 2
The figure is an electrical wiring diagram of one embodiment of the timer circuit of the present invention, and FIG. 3 is an electrical wiring diagram of another embodiment. Q1 to Q4...transistor, Ra, Rb,
R□～R6... ゛...Resistance, C1...
・Capacitor, Dl...Diode, Sl-□
······switch.

Claims

[Scope of utility model registration request]

A first transistor that turns on when the switch is turned on, a second transistor that turns on when this transistor is turned on, which is connected in series to the power supply line, and a second transistor that is connected to the output side of the second transistor. It comprises a capacitor that is gradually charged by the output of the transistor when it is turned on, and a third transistor that forcibly turns off the second transistor when the voltage across the capacitor reaches a preset constant value. timer circuit.