JPS58181315A - Staircase wave generating circuit - Google Patents

Abstract

PURPOSE:To obtain a staircase wave with a good linearity without increasing the capacitance of a capacitor, by resetting the staircase wave generated at an integration circuit with a compared output with a reference value of the wave generated at one clock delay. CONSTITUTION:The integration circuit 10 outputs a staircase wave V in synchronizing with a clock input signal CL. The step wave V charges a capacitor 16 via a switching element 15. When a non-inverting input exceeds a value of a reference voltage Vr applied to an inverting input terminal, a voltage comparator 18 inverts an output V2 from a low to a high level and closes a switching element 19. A capacitor 13 is short-circuited and an output V of the integration circuit 10 reaches 0 volt. The output V2 is inverted from a high to a low level with one clock delay and the switching element 19 is opened at the same time. Similarly, the operation from the beginning is repeated and the staircase wave output V is obtained repetitively with a prescribed period from the output side of the integration circuit 10.

Description

[Detailed description of the invention] Regarding generation circuits.

In this type of conventional staircase wave generation circuit, as shown in the circuit diagram of FIG. A current flows and charges the capacitor 2. At this time, since diode 3 is turned off, capacitor 4 is not charged.

Therefore, no charge is discharged from the capacitor 4. When the polarity of the input clock pulse CL becomes positive, diode 1 is turned off, diode 4 is turned on, and the charge stored in capacitor 2 is sent to capacitor 4 as shown by arrow B through diode τ3. Charge this. If the capacitance of the capacitor 2 is C1%, and the capacitance of the capacitor 4 is C2, and C2>c is selected, most of the charge in the capacitor 2 is efficiently sent to the capacitor 4. Similarly, when the above operation is repeated, the output voltage ■ is discharged stepwise through the transistor 5, and the output voltage V
becomes O volt. By repeating such operations, a staircase wave output V is obtained at the output terminal, as seen in the operational waveform diagram of FIG.

However, in order to provide linearity to the output in such a conventional staircase wave generation circuit, the condition C2>is required as described above. If the capacitance C1 is made extremely small in order to satisfy this requirement, the accuracy per step of the staircase wave output will deteriorate (due to stray capacitance, charge leakage, etc.). Generally speaking, in such conventional circuits, the capacitance C1 is 00
01μF1C2 needs to be about 0.1μF, but such a large capacitance is not suitable for integration. Furthermore, as the staircase wave output voltage increases, the amount of charge transferred from the capacitor C1 to the capacitor C2 is small, resulting in a decrease in linearity.

An object of the present invention is to provide a staircase wave generation circuit that can be easily applied to an integrated circuit and can provide an output with good linearity in terms of performance.

According to the present invention, the operational amplifier circuit includes a first capacitor, a second capacitor, the second capacitor connected between the output side and the inverting input terminal, and a switching circuit in synchronization with a clock input signal. A reference voltage is applied to the first capacitor through one contact, and the reference voltage is applied to the first capacitor through the other contact.
a first switching circuit that applies a discharge voltage from a canoccictor to an inverting input terminal of the operational amplifier circuit; a third canoccitor; a fourth capacitor; , a voltage comparator circuit to which the reference voltage is applied to an inverting input terminal; an output of the arithmetic circuit is applied to the third capacitor via one contact switched in synchronization with a clock input signal; a second switching circuit that applies a discharge voltage from the third capacitor/-E' capacitor to the fourth capacitor and supplies the discharge voltage to a non-inverting input terminal of the voltage comparison circuit; and a third switching circuit that shorts both ends of the second capacitor in response to the output of the voltage comparison circuit, and a staircase wave generation circuit is obtained that extracts the staircase wave from the output side of the arithmetic circuit. .

Next, an embodiment according to the present invention will be described with reference to the block diagram of FIG. 3 and the operational waveform diagram of FIG. 4. In the figure, 11 is a switching element controlled by a clock input signal, 12 and 13 are capacitors, and 14 is an arithmetic circuit, which constitute an integrating circuit. 15 is a switching element that is controlled by a clock input signal like the switching element 11, and 16.17 is a capacitor i.
9, 18 is a voltage comparator, and 19 is a switching element that short-circuits both ends of the canister 13. The switching element 11 is closed to the application side of the reference voltage V when the clock input signal is at a high level, and is closed to the operational amplifier circuit 14 side when the clock input signal is at a low level. When the level is high, it is closed to the integration circuit lo side, and when it is low level, it is closed to the voltage comparison circuit 18 side.

Now, the output ■ of the integrating circuit 1o is the initial value. If it is volts, the output of the integrating circuit 1o rises in a staircase wave synchronized with the clock input signal CL, as shown in FIG. At this time, the rising voltage ■8t8p of the output ■ per cycle of the clock pulse is: ■ = U・V... Song (1) step
It becomes C2r. The staircase wave (2) thus obtained charges the capacitor 16 via the switching element 15. Here, if the capacitance of the capacitor 16 is C3 and the capacitance of the capacitor 17 is 04, and the relationship C3>C4 is selected, the voltage v1 given to the non-inverting input terminal of the voltage comparator 18 is the output of the integrating circuit 1o. It becomes the same waveform as the output V of the integrating circuit 1o, with a delay of one clock from V. In the voltage comparison circuit 18, when the non-inverting input (1) exceeds the value of the reference voltage (2) applied to the inverting input terminal, the output V2k is inverted from a low level to a high level and the switching element 19 is closed. As a result, the capacitor 13 is short-circuited, and the output V of the integrating circuit 10 becomes O volts instantly. After one clock delay, the non-inverting input (1) of the voltage comparison circuit 18 becomes O volts, the output (2) inverts from high level to low level, and at the same time, the switching element 19 is opened. Thereafter, the operation from the beginning is repeated in the same manner, and the staircase wave output V is repeatedly obtained from the output side of the integrating circuit 10 at a constant period.

As is clear from the above explanation, according to the present invention, the capacitance of the capacitor can be increased by resetting the staircase wave generated in the integrating circuit using the comparison output with the reference value of the staircase wave generated with a delay of one clock. The MO8 integrated circuit not only provides a step wave with good linearity due to a stable step voltage without large jumps, but also has less stray capacitance because the capacitance of the capacitor and capacitor can be reduced, and there is no charge leakage. The reliability can be demonstrated by applying this method to other systems, and the effects obtained are significant.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing an example of a conventional staircase wave generation circuit;
The figure is a time chart showing the operating waveforms of the conventional example in Fig. 1, Fig. 3 is a circuit diagram showing an embodiment of the staircase wave generation circuit according to the present invention, and Fig. 4 is the operating waveform of the embodiment in Fig. 3. It is a time chart showing. In the figure, 10 is an integrating circuit, 11, 15° 19 is a switching element, 12, 13, 16° 17 is a capacitor,
14 is an operational amplifier circuit, and 18 is a voltage comparison circuit. Figure 1 Figure 2 Figure V. Figure 3 Figure 4 V2.

Claims (1)

[Claims] 1 A first capacitor, a second capacitor, an operational amplifier circuit in which the second capacitor is connected between an output side and an inverting input terminal, and one contact that is switched in synchronization with a clock input signal. a first switching circuit that applies a reference voltage to the first capacitor through the contact point and applies a discharge voltage from the first capacitor to the inverting input terminal of the operational amplifier circuit through the other contact; and a third capacitor. G, a fourth capacitor, a voltage comparator circuit in which the fourth capacitor is connected to a non-inverting input terminal and the reference voltage is applied to the inverting input terminal; The output of the operational amplifier circuit is applied to the third capacitor through one contact, and the discharge voltage from the third capacitor is applied to the fourth capacitor through the other contact. a second switching circuit that applies the voltage to the non-inverting input terminal of the voltage comparison circuit, and a third switching circuit that shorts both ends of the second capacitor in response to the output of the voltage comparison circuit; A staircase wave generation circuit that extracts a staircase wave from the output side of an operational amplifier circuit.