JP3519354B2 - Saw wave generation circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CRT deflection waveform generating circuit. More specifically, the present invention relates to a semiconductor integration technology of a circuit for generating a vertical deflection waveform. 2. Description of the Related Art A sawtooth wave generating circuit for vertical deflection of a television or the like includes a capacitor as shown in, for example, "NHK Television Technical Textbook (1)" edited by Japan Broadcasting Corporation, P210, (1989). A method of charging with a constant current source is generally used. In this circuit system, in order to obtain a sawtooth wave having a constant amplitude even when the vertical deflection frequency changes, a vertical synchronization signal is first passed through a CR filter to obtain a DC voltage proportional to the vertical deflection frequency. The current value proportional to the DC voltage may be set as the current value of the constant current source. [0003] However, the vertical deflection frequency is generally 50H.
z to 120 Hz, and the time constant of the CR filter needs to be sufficiently lower than the vertical deflection frequency, so that the capacitance value of the capacitor is 0.01 μF to 1 μM.
A large capacitance value of about F was required, and it was impossible to incorporate it in an integrated circuit. SUMMARY OF THE INVENTION An object of the present invention is to realize a sawtooth wave generating circuit synchronized with an input whose period changes using a capacitor that can be formed in an integrated circuit. [0005] In order to achieve the above object, the present invention employs the following means. The voltage value of the sawtooth wave output from the sawtooth wave generation circuit is used to detect the loss of synchronization. Since the voltage value of the sawtooth wave changes linearly with the passage of time, the voltage value of the sawtooth wave when the synchronization input is turned on is subtracted from the peak voltage of the sawtooth wave, and is proportional to the degree of loss of synchronization. Obtained voltage value. The voltage controlled oscillator is controlled by a voltage value obtained by integrating this voltage value to achieve synchronization. According to the present invention, one capacitor is charged to the voltage value of the sawtooth wave. Another capacitor is charged to a reference voltage. Next, the charge amount stored in the two capacitors is subtracted by a subtraction circuit. If the electric charges stored in the two capacitors are equal, the output of the subtraction circuit becomes 0, and the output of the voltage controlled oscillator does not change. 2
If the amounts of charge stored in the two capacitors are different, the output frequency of the voltage controlled oscillator changes so as to approach the frequency of the input. Therefore, the characteristic of whether or not to synchronize can be determined only by the relative ratio of the two capacitors, and does not require a large value as the capacitance value. An embodiment of the present invention will be described with reference to FIGS. 1, 2 and 3. FIG. In FIG. 1, a synchronization pulse is input to an input terminal. The input terminal is a reset terminal of the counter 2, S
C input terminal of W control circuit 3, control terminal of switch 9, control terminal of switch 16, voltage controlled oscillator (VCO)
17 reset terminal. The output of counter 2 is M
Except for one SB, it is input to the DA converter. The MSB output of the counter 2 is connected to the A input terminal of the SW control circuit 3, and the output from one LSB from the MSB of the counter 2 is simultaneously connected to the B input terminal of the SW control circuit 3. One output of the DA converter 1 is an output terminal, and the other is a switch 1
0, switch 12, and one end of switch 14. The other end of the switch 10 is commonly connected to one end of the switch 9 and one end of the capacitor 6. The other end of the switch 12 is commonly connected to one end of the capacitor 5 and one end of the switch 13. Is commonly connected to one end of the capacitor 4 and one end of the switch 15. [0008] The other end of the capacitor 6 is connected to one end of the switch 16, one end of the switch 11, the other end of the switch 13,
Commonly connected to the other end of the switch 15. The other end of the capacitor 5, the other end of the capacitor 4, the other end of the switch 9, and the other end of the switch 11 are each connected to the ground potential. The other end of the switch 16 is commonly input to the inverting input terminal of the operational amplifier 8 and one end of the capacitor 7. The other end of the capacitor 7 is connected to the output terminal of the operational amplifier 8 and the VCO 1
7 are commonly connected. The non-inverting input terminal of the operational amplifier 8 is connected to the ground potential. The output of the voltage controlled oscillator 17 is connected to the clock input terminal of the counter 2 and the SW
The D input terminal of the control circuit 3 is commonly connected. An output CLK1 of the SW control circuit 3 is commonly connected to control terminals of a switch 10 and a switch 11. Outputs CLK2, CLK2M, CL of SW control circuit 3
K3 and CLK3M are a switch 12 and a switch 1 respectively.
3, connected to the control terminals of the switches 14 and 15. FIG. 2 shows the operation timing and input / output waveforms of the circuit of FIG. In the left half of FIG. 2, the dotted line indicates that the VCO oscillation frequency is higher than the synchronization pulse frequency, and the solid line indicates that the VCO oscillation frequency is higher than the synchronization pulse frequency. Indicates low case. The right half of FIG. 2 shows a case where the oscillation frequency of the VCO matches the frequency of the synchronization pulse. Hereinafter, the circuit operation will be described with time. First, a case where the oscillation frequency of the VCO is higher than the frequency of the synchronization pulse will be described. When the input synchronization pulse changes from H to L, CLK1 changes from L to H, and the capacitor 6 is connected to the DA converter 1. At the same time, the reset of the counter 2 is released, and the counter 2 starts counting the output of the VCO 17. The output of the counter 2 increases with the passage of time, and the output of the DA converter 1 also increases. When the output of the MSB-1 of the counter 2 changes from L to H, CLK1 changes from H to L, and the capacitor 6 is disconnected from the output of the DA converter 1. At this time, the voltage of VP / 2 is held in the capacitor 6. At the same time, CLK2
Changes from L to H, and the capacitor 5 is connected to the DA converter 1. Next, only the MSB of the output of the counter 2 is H,
At the time when the others become L, the output of the DA converter 1 becomes 0 and CLK2 changes from H to L.
Holds the voltage of VP. At the same time, since CLK3 changes from L to H, the capacitor 4 is connected to the output of the DA converter 1. Next, when the input synchronization pulse changes from L to H, CLK3 changes from H to L, and if the voltage value of the sawtooth wave at this time is VA, the voltage of VA is held in the capacitor 4. You. At the same time, CLK2M and CLK3M change from L to H, and the switch 16 is closed, so that the charges held in the capacitors 4, 5, and 6 are transferred to the capacitor 7. Capacitors 4, 5, 6, and 7 each have a capacitance of C
4, C5, C6, and C7, and assuming that the voltage previously held in the capacitor 7 is VK, the output V of the operational amplifier 8
OP is: VOP =-(VA.C4 + VP.C5-VP.C6 / 2) C7 + VK (1) Here, if C5: C6 = 1: 2, VOP = -C4.VA / C7 + VK (2) From the equation (2), the output VOP of the operational amplifier 8 is smaller than the past voltage value VK. The oscillation frequency of the VCO 17 decreases as the VOP decreases, and the output frequency decreases and approaches the input frequency. By repeatedly performing the above-described operation, VA gradually approaches 0, and when VA = 0, the input and the output are synchronized. [0013] Next, the VCO
The case where the oscillation frequency is lower will be described. When the input synchronization pulse changes from H to L, CLK1 changes from L to H.
And the capacitor 6 is connected to the DA converter 1. At the same time, the reset of the counter 2 is released, and the counter 2
It starts counting the output of CO17. The output of the counter 2 increases with the passage of time, and the output of the DA converter 1 also increases. The output of MSB-1 among the outputs of counter 2 is L
When the signal changes from H to H, CLK1 changes from H to L, and the capacitor 6 is disconnected from the output of the DA converter 1. At this time, the voltage of VP / 2 is held in the capacitor 6. At the same time, CLK2 changes from L to H, and the capacitor 5 is connected to the DA converter 1. Next, the input synchronization pulse changes from L to H.
When CLK2 changes from H to L when the voltage value of the sawtooth wave at this time is VB, the capacitor 5
The voltage of VB is maintained. At the same time, CLK2M changes from L to H
Since the switch 16 is also closed, the electric charge held in the capacitors 4 and 5 is transferred to the capacitor 7. Capacitors 4, 5, and 7 are represented by C4, C5, C6,
Assuming that C7 is the voltage value held in the capacitor 7 in the past as VK, the output VOP of the operational amplifier 8 is VOP =-(VB.C5 -VP.C6 / 2) C7 + VK (3) where C5: If C6 = 1: 2, VOP = -C5. (VP.VB) / C7 + VK (4) From the equation (4), the output VOP of the operational amplifier 8 is VP> VB. Also increase. The oscillation frequency of the VCO 17 increases as VOP increases, and the output frequency increases and approaches the input frequency. By repeating the above-described cycle, VB gradually approaches VP, and the input and output are synchronized when VP = VB. FIG. 3 shows the SW control circuit 3 in the circuit of FIG.
This is an embodiment of the present invention. As described above, the SW control circuit 3
CLK1, CLK from four input signals A, B, C, D
2, five switch control signals CLK2M, CLK3 and CLK3M. CLK1 is the counter 2 MS
AND output of the inversion of the B output, the inversion of the MSB-1 output of the counter 2, and the inversion of the input synchronization pulse. Therefore, the sawtooth wave of the output of the DA converter 1 changes from 0 to VP
/ H. CLK2 is the inverted output of the MSB output of the counter 2 and the AND output of the MSB-1 output of the counter 2. Therefore, the sawtooth wave of the output of the DA converter 1 is VP
When it becomes larger than / 2, it becomes H. CLK2M is CLK2M
When 2 is H, this is a control signal for transferring the charge charged in the capacitor 5 through the switch 12 to the capacitor 7 through the switch 13. Therefore, the RS flip-flop 20 is set at CLK2, and the output of the RS flip-flop 20 and the input synchronization pulse are ANDed. CLK3 is the same as the MSB output of the counter output, and is output within one input cycle. It is H during the second sawtooth wave. CLK3M is a control signal for transferring the charge charged in the capacitor 4 through the switch 14 to the capacitor 7 through the switch 15 when CLK3 is H. Therefore, the RS flip-flop 19 is set at CLK3, and its output and the input signal are ANDed. RS flip-flop 18
And the AND gate 21 are connected to the RS flip-flop 1
Provided to reset 9, 20. If the number of bits of the counter is N, the output frequency of the VCO 17 is 2N-1 times the input frequency. At this time, the number of bits of the DA converter 1 is N-1 bits.
The circuit of FIG. 4 is another embodiment of the subtraction circuit in the sawtooth wave generation circuit of the present invention. FIG. 5 shows the operation timing of the circuit of FIG. FIG. 4 shows a holding circuit 32 of the circuit of FIG.
1 shows a portion where switch control signals CLK4 and CLK4M are added. Except for the hold circuit 32, the same circuit as that of FIG. 1 is used. Switch control signal CLK
4. The CLK4M generation circuit can be easily inferred from the circuit of FIG. The additional capacitor 29 is added to increase the synchronization speed when three or more sawtooth waves exist in one input cycle. The following operation is shown in FIGS.
This will be described with reference to FIG. When three or more sawtooth waves exist in one input cycle, the capacitor 29, the switches 30, 31, and the switch control signals CLK4, CLK4M
If there is no, the input voltage of the VCO 17 decreases by the amount shown in the equation (2). When three or more waves exist, VA = V
Because of P, the decrement is given by equation (2). ΔVOP = −C4 · VP / C7 (5) The value shown by equation (5) is the number of sawtooth waves of three or more in one input cycle. But they have the same value. That is, even if the input frequency and the output frequency are largely separated, the frequency change width of the VCO is the same. In order to increase the synchronization speed, when the input frequency and the output frequency are far apart, the decrease represented by the equation (5) may be increased in proportion to the degree of the separation. A capacitor 29, switches 30, 31, and switch control signals CLK4, CLK4M have been added for this purpose. CLK4 is the output sawtooth wave 3
It becomes High at the rise of the wave, and the switch 31 is turned ON. At the same time as the third output sawtooth wave falls, the switch 31 is turned off, and the capacitor 29 holds the peak value VC of the third output sawtooth wave. At the rise of the next input, CLK4M becomes High, the switch 30 is turned on, and the electric charge held in the capacitor 29 is
Will be forwarded to Therefore, assuming that the capacitance value of the capacitor 29 is C29, the decrease in the input voltage of the VCO 17 is as follows: ΔVOP = −C4 · VP / C7−C29 · VC / C7 (6) Expressions (6) and (5) are compared. And the degree of reduction is increased by VC × C29 / C7. That is, the decrease can be increased in proportion to the degree of separation between the input frequency and the output frequency. The dotted line in FIG. 5 shows the change in the input voltage of VCO 17 before adding capacitor 29, and the solid line shows the change in the input voltage of VCO 17 after adding capacitor 29. By adding the capacitor 29, VCO1
The decrease of 7 is large. In the circuit shown in FIG. 4, the capacitor 29, the switches 30, 31 and the switch control signals CLK4, CLK4M are used to hold the peak value of the third output sawtooth wave.
Was added. Furthermore, the input frequency is lower than the output frequency,
When four or more output sawtooth waves are generated within one cycle of the input, by adding a capacitor, a switch, and a switch control signal corresponding to the increased sawtooth wave, the characteristics can be improved. According to the present invention, the characteristics of the circuit can be determined by the ratio of the capacitors as shown in the equations (2) and (4).
A circuit independent of the absolute value of the capacitor can be provided.
Therefore, since a circuit can be formed with a capacitor having a small absolute value, it is suitable for use in an integrated circuit.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows a circuit diagram of an embodiment of the present invention. FIG. 2 shows operation timing of the embodiment of the present invention. FIG. 3 shows the contents of a SW control circuit in the embodiment (FIG. 1) of the present invention. FIG. 4 shows a circuit diagram of another embodiment of the present invention. FIG. 5 shows operation timing of another embodiment of the present invention. [Description of Signs] 1 DA converter 2 Counter 3 SW control circuit 4-7 Capacitor 8 Operational amplifier 9-16 Switch 17 Voltage control oscillator (VCO) 18-20 Flip-flop with set / reset 22-25 AND gate 26-28 Inverter 29 Capacitor 30, 31 Switch 32 Hold circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03K 4/08 G09G 1/04 H04N 3/16 H04N 3/27

Claims (1)

(57) [Claim 1] An input signal which is a synchronization pulse is reset to a reset terminal.
A counter that counts the oscillation frequency that is input from a slave and that is output to a voltage-controlled oscillator that controls the oscillation frequency by a control voltage, and a DA that converts the output of the counter into an analog signal.
A converter, a subtraction circuit that inputs an output of the DA converter, and an integration circuit that integrates an output of the subtraction circuit and uses the integrated output signal as the control voltage of the voltage-controlled oscillator. a first capacitor charged to the reference voltage value, two charged to the output voltage value of the DA converter
, The charge amount of the two capacitors is sequentially subtracted from the charge amount of the first capacitor ,
A sawtooth wave generating circuit for outputting a sawtooth wave.