JPS59216320A - Saw tooth wave generating circuit - Google Patents

Saw tooth wave generating circuit

Info

Publication number
JPS59216320A
JPS59216320A JP9172483A JP9172483A JPS59216320A JP S59216320 A JPS59216320 A JP S59216320A JP 9172483 A JP9172483 A JP 9172483A JP 9172483 A JP9172483 A JP 9172483A JP S59216320 A JPS59216320 A JP S59216320A
Authority
JP
Japan
Prior art keywords
capacitor
pulse
voltage
electric charge
charged
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9172483A
Other languages
Japanese (ja)
Inventor
Takashi Ito
孝 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP9172483A priority Critical patent/JPS59216320A/en
Publication of JPS59216320A publication Critical patent/JPS59216320A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K4/00Generating pulses having essentially a finite slope or stepped portions
    • H03K4/02Generating pulses having essentially a finite slope or stepped portions having stepped portions, e.g. staircase waveform
    • H03K4/023Generating pulses having essentially a finite slope or stepped portions having stepped portions, e.g. staircase waveform by repetitive charge or discharge of a capacitor, analogue generators

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Pulse Circuits (AREA)

Abstract

PURPOSE:To generate a high-linearity saw tooth wave by charging temporarily the electric charge in a capacitor with a constant voltage and transferring this electric charge to another capacitor in steps with complementary switching of switches to integrate the electric charge. CONSTITUTION:When a pulse A having a period t2 is inputted to a monostable multivibrator 1, the monostable multivibrator 1 outputs a pulse B synchronously with the rise of this pulse A. In a time zone t1 when this pulse B is generated, the electric charge charged in a capacitor 2 is discharged to set the voltage at a terminal point C to zero as shown by a waveform C. Switches 8 and 9 are interlocked with each other as shown by waveforms E and F and are operated complimentarily, and an electric charge C2V0 is charged in a capacitor 7 by the power supply of a voltage V0 if the switch 8 is opened and the switch 9 is closed, and this charged electric charge is transferred to a capacitor 2 and the negative input terminal of an operational amplifier 6 otherwise.

Description

【発明の詳細な説明】 この発明は入力パルスの周期または反転間隔に同期して
ピークを持つのこぎり波の発生回路に関し、特に、静電
容量値および抵抗値に直接依存せずにfc化に適するよ
うに設計されたのこぎり波発生回路に関するものである
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sawtooth wave generating circuit that has a peak in synchronization with the period or inversion interval of an input pulse, and is particularly suitable for fc conversion without directly depending on capacitance and resistance values. The present invention relates to a sawtooth wave generation circuit designed as follows.

第11i!!Iは従来ののこぎり波発生回路の一例を示
す図である。
11th i! ! I is a diagram showing an example of a conventional sawtooth wave generation circuit.

まず、第1図を参照して従来ののこぎり波発生回路の構
成について説明する。第1図において、単安定マルチバ
イブレータ1は、入力パルスAの立上がりに同期したパ
ルスBを出力する。前記パルスBが発生しない期間はト
ランジスタ4はオフ状態となり、静電容量値C7のコン
デンサ2は電源VOによって抵抗IRの抵抗3を介して
充電される。また、前記パルスBが発生する期間はトラ
ンジスタ4はオン状態となり、コンデンサ2に充電され
た電荷は放電される。
First, the configuration of a conventional sawtooth wave generation circuit will be explained with reference to FIG. In FIG. 1, a monostable multivibrator 1 outputs a pulse B synchronized with the rising edge of an input pulse A. During the period when the pulse B is not generated, the transistor 4 is in an off state, and the capacitor 2 having a capacitance value C7 is charged by the power source VO via the resistor 3 of the resistor IR. Further, during the period in which the pulse B is generated, the transistor 4 is in an on state, and the electric charge stored in the capacitor 2 is discharged.

第2図は11図に示すのこぎり波発生回路の動作を説明
するための波形図である。
FIG. 2 is a waveform diagram for explaining the operation of the sawtooth wave generation circuit shown in FIG. 11.

次に、第2図を参照して第1図に示すのこぎり波発生回
路の動作について説明する。単安定マルチバイブレータ
1に入力されるパルスAは第2図(A>に示プように1
2の周期を持っており、前記パルスAに同期して単安定
マルチバイブレータ1から発生するパルスBも第2図(
B)に示すようにt2の周期を持っている。上述のよう
にパルスBが発生している期間t、ではコンデンサ2は
放電されて0点での電圧はOとなり、パルスBが発生し
ていない期間12−1 、ではコンデンサ2は充電され
、0点での電圧′は第2図に示すように指数関数的に増
大し、入カバ°ルスAの立上がりに同期してピーク値V
pに至るのこぎり波となる。
Next, the operation of the sawtooth wave generating circuit shown in FIG. 1 will be explained with reference to FIG. The pulse A input to the monostable multivibrator 1 is 1 as shown in FIG.
The pulse B generated from the monostable multivibrator 1 in synchronization with the pulse A is also shown in Fig. 2 (
As shown in B), it has a period of t2. As mentioned above, during period t when pulse B is generated, capacitor 2 is discharged and the voltage at the 0 point becomes O, and during period 12-1 when pulse B is not generated, capacitor 2 is charged and becomes 0. The voltage at the point increases exponentially as shown in Figure 2, and reaches the peak value V in synchronization with the rise of the incident coverage A.
It becomes a sawtooth wave that reaches p.

前記ピーク値Vpは、コンデンサ2の静電容量をC1抵
抗3の抵抗値をR1電m電圧をVoとすると、 で与えられる。
The peak value Vp is given by the following equation, where the capacitance of the capacitor 2 is C1, the resistance value of the resistor 3 is R1, the voltage is R1, and the voltage is Vo.

ここで、前記t2が前記t1より十分に大きいとする。Here, it is assumed that t2 is sufficiently larger than t1.

第2図(C)ののこぎり波のカーブの傾斜は(1)式に
おける時定−ORに依存し、周期t2が長い場合は大き
な時定数が必要である。したがって、大容量のコンデン
サまたは高抵抗値の抵抗が必要となり、第1図に示した
従来ののこぎり波発生回路のIC化は困難であった。
The slope of the sawtooth curve in FIG. 2(C) depends on the time constant -OR in equation (1), and if the period t2 is long, a large time constant is required. Therefore, a capacitor with a large capacity or a resistor with a high resistance value is required, and it is difficult to integrate the conventional sawtooth wave generating circuit shown in FIG. 1 into an IC.

それゆえに、この発明の主たる目的は、上述の欠点を解
消し、静電容量値および抵抗値に直接依存しないIC化
に適したのこぎり波発生回路を提供することである。
Therefore, the main object of the present invention is to eliminate the above-mentioned drawbacks and to provide a sawtooth wave generation circuit suitable for IC implementation that does not directly depend on capacitance and resistance values.

この発明は要約すれば、一定電圧印加手段により一旦第
2のコンデンサに電荷を充電し、開閉器の相補的開閉に
よって前述の電荷を第1のコンデンサに転送する動作を
繰返し、第1のコンデンサを段階的に充電することによ
り、のこぎり波の発生を時定数CRに依存しないように
構成したものである。
To summarize, the present invention can be summarized as follows: the second capacitor is once charged with a charge using a constant voltage application means, and the operation of transferring the above-mentioned charge to the first capacitor by complementary opening and closing of the switch is repeated, and the first capacitor is then charged. By charging in stages, the generation of sawtooth waves is made independent of the time constant CR.

この発明の目的およびその他の目的と特徴は以下に図面
を参照して行なう詳細な説明から一膚明らかとなろう。
The objects and other objects and features of the present invention will become apparent from the detailed description given below with reference to the drawings.

第3図はこの発明の一実施例を示す回路図である。FIG. 3 is a circuit diagram showing an embodiment of the present invention.

次に、第3図に示す実施例の構成について説明する。入
力パルスの立上がりに同期したパルスを発生させる単安
定マルチバイブレータ1は、内部に開閉器を含む初期設
定回路5に接続される。単安定マルチバイブレータ1が
入力パルスに応答してパルスを出力している時間帯は、
初期設定回路5は並列に接続されている静電容量値C4
のコンデンサ2の電荷を放電し、コンデンサ2の電圧を
0とする。また、単安定マルチバイブレータ1がパルス
を出力していない時間帯は前述のコンデンサ2の放電は
中止される。また、コンデンサ2は同時に、演算itI
IIM器6と並列に接続されて積分器を構成している。
Next, the configuration of the embodiment shown in FIG. 3 will be explained. A monostable multivibrator 1 that generates a pulse synchronized with the rising edge of an input pulse is connected to an initial setting circuit 5 that includes a switch inside. During the time period when monostable multivibrator 1 is outputting pulses in response to input pulses,
The initial setting circuit 5 has a capacitance value C4 connected in parallel.
The electric charge of the capacitor 2 is discharged, and the voltage of the capacitor 2 is set to 0. Further, during the time period when the monostable multivibrator 1 is not outputting pulses, the above-mentioned discharging of the capacitor 2 is stopped. At the same time, the capacitor 2 is connected to the calculation itI.
It is connected in parallel with the IIM unit 6 to form an integrator.

このコンデンサ2の一方の端子C点の電圧がこの積分器
の積分出力すなわちこの実施例の出力電圧である。
The voltage at one terminal C point of this capacitor 2 is the integrated output of this integrator, that is, the output voltage of this embodiment.

一方、一定電圧Voの電源が設けられており、開閉器9
を介して静電容量値C2のコンデンサ7の一方の端子り
点に接続されている。また、上述のコンデンサ7の端子
−D点は同時に、開閉器8を介して、コンデンサ2の前
述の0点の反対側の端子および演算増幅器6の負入力端
子に接続されている。N閉器8および9はスイッチング
制御回路10からの制御信号に基づいて相補的に時間t
On the other hand, a power supply with a constant voltage Vo is provided, and the switch 9
The capacitor 7 is connected to one terminal of the capacitor 7 having a capacitance value C2. Further, the above-mentioned terminal -D point of the capacitor 7 is simultaneously connected to the terminal on the opposite side of the above-mentioned 0 point of the capacitor 2 and the negative input terminal of the operational amplifier 6 via the switch 8 . The N-closers 8 and 9 complementarily control the time t based on the control signal from the switching control circuit 10.
.

の周期で開閉するものである。It opens and closes at a cycle of .

第4図は第3図に示す実施例を説明するための波形図で
ある。
FIG. 4 is a waveform diagram for explaining the embodiment shown in FIG. 3.

次に、第4図を参照して第3図に示す実施例の動作につ
いて説明する。単安定マルチバイブレ−タ1は、第4図
(A>に示す周期t2のパルスAが入力されると、パル
スへの立上がりに同期して第4図(B)に示すパルスB
@発生する。初期設定回路5は開閉器を内部に含み、パ
ルスBが発生している時間it+においては、コンデン
サ2に充電されている電荷を放電して第4図(C)に示
すようにコンデンサ2の一方の端子C点の電圧を0とす
る。また、パルスBが発生していない時間帯12−1.
においては、初期設定回路5は上述のコンデンサ2の放
電を中止する。開閉器8および9は第4図(E)、(F
)に示すように連動して相補的に開閉する開閉器であり
、開閉器8が間き、開閉器9が閉じてい場合は電圧Vo
の電源によってコンデンサ7にはC2VOの電荷が充電
され、開閉器8が閉じ開閉器9が開くとコンデンサ7に
充電された前述の電荷C2Vθはコンデンサ2および演
算増幅器6の負入力端子へ転送される。
Next, the operation of the embodiment shown in FIG. 3 will be explained with reference to FIG. When the monostable multivibrator 1 receives a pulse A with a period t2 shown in FIG. 4 (A>), the monostable multivibrator 1 generates a pulse B shown in FIG. 4 (B) in synchronization with the rising edge of the pulse.
@Occur. The initial setting circuit 5 includes a switch therein, and during the time it+ when the pulse B is generated, the electric charge stored in the capacitor 2 is discharged and one side of the capacitor 2 is opened as shown in FIG. 4(C). Let the voltage at terminal C point be 0. In addition, the time period 12-1 in which pulse B is not generated.
In this case, the initial setting circuit 5 stops discharging the capacitor 2 described above. Switches 8 and 9 are shown in Fig. 4 (E) and (F).
), these are switches that open and close in a complementary manner in conjunction with each other, and when switch 8 is open and switch 9 is closed, the voltage Vo
The capacitor 7 is charged with an electric charge of C2VO by the power supply, and when the switch 8 closes and the switch 9 opens, the above-mentioned charge C2Vθ charged in the capacitor 7 is transferred to the negative input terminal of the capacitor 2 and the operational amplifier 6. .

初期設定回路5がコンデンサ2の放電を中止している期
間において、コンデンサ7に充電されている電荷Qは前
述のようにQ ” C2Vo・・・(1)であり、この
電荷が演算増幅器6を介してコンデンサ2に転送される
とコンデンサ2の0点側の電荷はQ−−C,V。・・・
(2)となる。したがって(1)、(2)式よりVc 
−C2/ C+  ” V。
During the period when the initial setting circuit 5 stops discharging the capacitor 2, the charge Q charged in the capacitor 7 is Q''C2Vo...(1) as described above, and this charge charges the operational amplifier 6. When transferred to the capacitor 2 via the capacitor 2, the charge on the 0 point side of the capacitor 2 becomes Q--C, V.
(2) becomes. Therefore, from equations (1) and (2), Vc
-C2/C+”V.

となる。becomes.

ここで、コンデンサ2の電圧がOになってからのWM開
閉器の閉路回数をNとすると、N回時における0点の電
圧VC(N)は、 Vc  (N)−Vo  ’ N ” C2/CI ・
” (3)となる。
Here, if the number of times the WM switch is closed after the voltage of capacitor 2 becomes O is N, the voltage VC (N) at the 0 point at N times is Vc (N) - Vo' N '' C2/ CI・
” (3).

入力パルスの1周期中の閉路回数は12/1 。The number of circuit closures in one cycle of the input pulse is 12/1.

なので、Vc  (N)が入力パルスの1周期に同期し
てとるピーク値は、 P =  Vo  −1z /j 6 ・Ct /C+
 −(4)となる。
Therefore, the peak value that Vc (N) takes in synchronization with one cycle of the input pulse is P = Vo -1z /j 6 ・Ct /C+
-(4).

したがって、上述の(4)式によれば、ピーク値Vpは
抵抗値には依存せずに、開閉器8.9の開閉周期t、と
入力パルスAの周期t2との比、コンデンサ2,7の静
電容量比C2/C,、および[!ffi圧Vaによって
決まり、このため静電容量値や抵抗値に直接影響されな
い。
Therefore, according to the above equation (4), the peak value Vp does not depend on the resistance value, but depends on the ratio of the switching period t of the switch 8.9 to the period t2 of the input pulse A, the capacitors 2, 7 The capacitance ratio C2/C, and [! It is determined by the ffi pressure Va, and therefore is not directly influenced by the capacitance value or resistance value.

ところで、上述の実施例では、交互に開閉する2つの開
閉器8,9を使用したが、たとえば2つの固定接点と1
つの可動片を持ついわゆる双極型間閉器を開閉器8.9
を統合したものとして用いても同様の効果が得られる。
By the way, in the above-mentioned embodiment, two switches 8 and 9 that open and close alternately are used, but for example, two fixed contacts and one switch are used.
So-called bipolar switchgear with two movable pieces 8.9
A similar effect can be obtained by using them as an integrated version.

以上のように、この発明によれば、一定電圧によって第
2のコンデンサに一旦電荷を充電し、開閉器の相補的開
閉によって前述の電荷を第1のコンデンサへ段階的に転
送して積分することによってのこぎり波を発生するよう
にしたので使用する静電容量値に直線依存せず、したが
って8吊の小さなコンデンサが使え、容易にIC化が可
能なのこぎり波発生回路を得ることができる。
As described above, according to the present invention, the second capacitor is once charged with a charge using a constant voltage, and the charge is transferred stepwise to the first capacitor by complementary opening and closing of the switch and integrated. Since the sawtooth wave is generated by the above, it is not linearly dependent on the capacitance value used, and therefore eight small capacitors can be used, and a sawtooth wave generation circuit that can be easily integrated into an IC can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来ののこぎり波発生回路の一例を示す回路図
である。第2図は従来ののこぎり波発生回路の動作を説
明1゛るための波形図である。第3図はこの発明の一実
施例の回路図である。第4図は第3図に示す実施例の動
作を説明するための波形図である。 図において、1は単安定マルチバイブレータ、2.7は
コンデンサ、3は抵抗、4はトランジスタ、5は初期設
定回路、6はS粋増幅器、8.9は開閉器、10はスイ
ッチング制御手段を示す。 代理人   大 岩 増 雄 第2図 第3図 第4図
FIG. 1 is a circuit diagram showing an example of a conventional sawtooth wave generating circuit. FIG. 2 is a waveform diagram for explaining the operation of a conventional sawtooth wave generating circuit. FIG. 3 is a circuit diagram of an embodiment of the present invention. FIG. 4 is a waveform diagram for explaining the operation of the embodiment shown in FIG. 3. In the figure, 1 is a monostable multivibrator, 2.7 is a capacitor, 3 is a resistor, 4 is a transistor, 5 is an initial setting circuit, 6 is an S-type amplifier, 8.9 is a switch, and 10 is a switching control means. . Agent Masuo Oiwa Figure 2 Figure 3 Figure 4

Claims (3)

【特許請求の範囲】[Claims] (1) 入力パルスの周期または反転間隔に同期したピ
ークを有するのこぎり波発生回路であって、 第1のコンデンサと、 前記入力パルスに同期して前記第1のコンデンサの電圧
を初期設定する手段と、 一定電圧を印加する電圧印加手段と、 前記電圧印加手段により充電される第2のコンデンサと
、 前記第2のコンデンサの電荷を受けて前記第1のコンデ
ンサを充電する積分手段と、 前記第2のコンデンサを前記電圧印加手段と前記積分手
段とに交互に接続するように切換えるスイッチング手段
とを備えた、のこぎり波発生回路。
(1) A sawtooth wave generation circuit having a peak synchronized with the period or inversion interval of an input pulse, comprising: a first capacitor; and means for initializing the voltage of the first capacitor in synchronization with the input pulse; , a voltage applying means for applying a constant voltage, a second capacitor charged by the voltage applying means, an integrating means for receiving the electric charge of the second capacitor and charging the first capacitor, and the second capacitor. a sawtooth wave generating circuit, comprising: switching means for alternately connecting a capacitor of 1 to the voltage applying means and the integrating means;
(2) 前記初期設定手段は入力パルスの立上がりまた
は立下がりに同期して前記第1のコンデンサの電圧をO
とする特許請求の範囲第1項記載ののこぎり波発生回路
(2) The initial setting means lowers the voltage of the first capacitor in synchronization with the rising or falling edge of the input pulse.
A sawtooth wave generation circuit according to claim 1.
(3) 前記WI2のコンデンサは、一端が等価的に接
地され、他端が前記第1のコンデンサと前記積分手段と
に前記スイッチング手段を介して接(4) 前記スイッ
チング手段の切換周期は、
(3) One end of the capacitor of WI2 is equivalently grounded, and the other end is connected to the first capacitor and the integrating means via the switching means. (4) The switching period of the switching means is
JP9172483A 1983-05-23 1983-05-23 Saw tooth wave generating circuit Pending JPS59216320A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9172483A JPS59216320A (en) 1983-05-23 1983-05-23 Saw tooth wave generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9172483A JPS59216320A (en) 1983-05-23 1983-05-23 Saw tooth wave generating circuit

Publications (1)

Publication Number Publication Date
JPS59216320A true JPS59216320A (en) 1984-12-06

Family

ID=14034446

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9172483A Pending JPS59216320A (en) 1983-05-23 1983-05-23 Saw tooth wave generating circuit

Country Status (1)

Country Link
JP (1) JPS59216320A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2606564A1 (en) * 1986-11-12 1988-05-13 Crystal Semiconductor Corp DEVICE AND METHOD FOR GENERATING REFERENCE VOLTAGES
GB2368474A (en) * 2000-09-28 2002-05-01 Seiko Epson Corp Sawtooth or triangular waveform generator

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2606564A1 (en) * 1986-11-12 1988-05-13 Crystal Semiconductor Corp DEVICE AND METHOD FOR GENERATING REFERENCE VOLTAGES
GB2368474A (en) * 2000-09-28 2002-05-01 Seiko Epson Corp Sawtooth or triangular waveform generator
GB2369733A (en) * 2000-09-28 2002-06-05 Seiko Epson Corp Waveform generator display device and electronic apparatus
GB2369733B (en) * 2000-09-28 2003-02-26 Seiko Epson Corp Waveform generator display device and electronic apparatus
US6600349B2 (en) 2000-09-28 2003-07-29 Seiko Epson Corporation Waveform generator, display device and electronic apparatus

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