JPS58178553A - Matrix array - Google Patents

Abstract

PURPOSE:To eliminate a linear defect even if a matrix array which has a plurality of gate lines, a plurality of source lines perpendicularly crossing the gate lines through an insulating layer and nonlinear switching elements provided at the intersections of the gate and source lines, is exposed with static electricity by increasing the electric breakdown voltage of an insulating layer larger than that of the switching elements. CONSTITUTION:A picture element of an array is composed of an MOS FET5 which switches a signal, a condenser 6 for holding a data signal and a liquid crystal panel 7, the gate of an FET5 is connected to a gate line 4, and the source is connected to source line 3, condenser 6 and panel 7. In this structure, the electric breakdown voltage of the insulating layer formed between the lines 3 and 4 increases to larger than the breakdown voltage of the FET5 in such a manner that, even if the matrix array is exposed with static electricity, a linear defect is not produced. In this manner, the defect is limited to the defect of the picture element, and its correction is facilitated.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a matrix array using nonlinear switching elements, and more particularly to a construction method for facilitating the correction of defects in the matrix array.

Recently, the development of large area display devices using one-trix arrays has been very active, and is expected to find wide-ranging applications such as small information devices and hump-type televisions. As a flat-panel, large-capacity display device, one in which switching elements are arranged in a matrix array is considered to be the most promising.

FIG. 1 is a layout diagram showing an example of the structure of an active matrix array substrate in which non-5i11 switching elements are arranged in a matrix array. The area indicated by 1 in the figure is a display area, in which non-linear elements 2 are arranged in a matrix, 3 is a data signal line (first line) to the non-linear elements 2, and 4 is a non-linear element. Linear element 2
This is the timing signal line (gauge line) to the ,
Defects that are likely to occur when a matrix array substrate is configured as shown in Figure 1 include pattern defects that occur during patterning of each line and non-titam elements, insulation defects at the intersections of source lines and gate lines, and non-linear elements. 2, poor insulation. Of these, pattern defects can be reduced to a fairly low level through process improvements and thorough dust-free measures, while insulation defects can be reduced by improving the quality of the insulating layer and increasing Kd. Even if it is possible to initially reduce the number of defects and the thickness, insulation defects between lines often occur after the matrix array is completed due to static electricity, etc. As can be seen in Figure 1, this static electricity defect occurs when the source twin or gate line receives static electricity or air outside the display area of the panel, resulting in poor insulation at the intersection of that line and a line perpendicular to it. As a result, the data signal leaks to the gauge line, the timing signal leaks to the source line, and the display of all pixels on the line including the insulation defect becomes defective, resulting in a so-called line defect, which deteriorates the display characteristics. It goes wrong.

When such an insulation defect occurs, the only way to correct it is to cut the source twin or gate line after the insulation defect has occurred; this type of correction method will cause the source twin or gate line to become disconnected. All pixels connected to this disconnected line remain as non-lighting defects, and line defects cannot be excluded.When constructing a matrix array on a single-crystal silicon substrate, diodes and resistors for static electricity storage are required. It is possible to protect the matrix array from static electricity by building it in a silicon substrate, but if the matrix array is configured on a glass plate, it is difficult to set up a protection circuit for static electricity, and therefore the insulation failure as described above may occur. The present invention was made in view of the above-mentioned problems, and it is difficult to mass-produce matrix arrays. It is designed to be small and prevent twin-shaped defects from forming even when exposed to static electricity, and provides an extremely effective means for increasing the mass production yield of matrix arrays.

The present invention will be explained in detail below with reference to the drawings.

Figure 2 shows an example of a matrix array using MOBtjJi field effect transistors as non-linear elements, and is an example of the 11iil matrix array liquid crystal display device.
This shows an elementary equivalent circuit. Reference numeral 5 is a Mol type field effect transistor for switching data signals, and reference numeral 6 is a capacitor used for holding data signals. 7 is a liquid crystal panel, 7-1 is a liquid crystal drive electrode formed corresponding to a liquid crystal drive element, and 7-
2 is the upper glass panel. As can be seen from the equivalent circuit in FIG.
It is limited to the weaker of the two, the gate breakdown voltage of the overflow field effect transistor. Therefore, in order to prevent dielectric breakdown at the intersection of the source line and the gate line, the gate breakdown voltage of the M08N and transistor 5 should be lower than the breakdown voltage at this intersection. , even if a large potential difference occurs between the two gauges, dielectric breakdown occurs at the gate of the MoI field effect transistor, and breakdown at the line intersection disappears. In addition, the leakage between the source twin and the gate fin that occurs in this way can be avoided by separating the Mol type field effect transistor 5 from the source twin or the gate line, so that the defect in the pixel can be detected on the panel display. It becomes nothing but.

The method of separation is, for example, by separating the gate electrode of MOa type field effect) Hunsister 5 from the gate line 4;
Alternatively, the source electrode of the transistor 5 may be separated from the source twin 5. Next, check the insulation voltage at the intersection of the source twin, gate, and line, and MO8! The gauge breakdown voltage of l-voltage effect transistors will be described. The third example shows a specific example of the display pixel in the equivalent circuit of Figure 2.
Figure (α) # Ch), Hei 1111 (l)
8 is an MO8m field effect transistor, and 9 is a gate line that partially extends above the transistor and serves as a gate electrode. Further, 10 is a source twin connected to the source electrode of the transistor. The cross section of this plan view (1) when cut along the dotted lines is C-shaped, and the insulating layer between the source line 10 and the gate 2-in-9 is 15, and is an M08 type field effect transistor. The gate insulating film is 12. Further, 14 is a glass substrate. Methods for forming insulating films include thermal oxidation of semiconductor films, chemical vapor deposition (own method), sputtering, and anodic oxide films. Insulating layers that can also be used include silicon dioxide, silicon dioxide,
For example, in FIG. 5, the semiconductor thin film 8 is polycrystalline silicon, the gate insulating film 12 is a thermally oxidized silicon film, and the insulating film 15 is a silicon nitride film, an Al-based film, etc.
Let us consider the case of forming by the VD method. The thermal oxide film of silicon has a high breakdown voltage of 8~9 x 10” V/am@
On the other hand, in the case of silicon dioxide formed by O'VD method, the withstand voltage is as low as about 4 to 5 x 106 V/as. In order to make the withstand voltage higher than the gate withstand voltage of an MO8 field effect transistor, the thickness of the interlayer insulating film 1s may be made to be at least twice the thickness of the gate insulating film 12. For example, the thickness of the gate insulating film 13 may be 200
When the thickness of the interlayer insulating layer is 5000 Å, the gate breakdown voltage of the transistor is 160 to 180 Å, and on the other hand, when the interlayer insulating layer is 5000 Å, the breakdown voltage is 200 to 180 Å.
It will be 250 volts. Therefore, the breakdown voltage between the fins is higher than the gate breakdown voltage of the transistor, and the method of making the breakdown voltage of the zero interlayer insulation film higher than the breakdown voltage of the gate insulation film, which achieves the object of the present invention, is to use silicon dioxide as an insulator as described above. Utilizing the difference in pressure resistance due to the difference in formation method,
Alternatively, other than the method of varying the film thickness, it is possible to achieve this by combining different materials for the two insulating films, such as silicon dioxide and silicon nitride film, silicon dioxide and arsena, silicon nitride film and alumina, etc.

As described above, if the electrical breakdown voltage at the intersection of the gauge line and the source line is set higher than the gate breakdown voltage of the MOa field effect transistor, when the matrix array is exposed to static electricity, the electrostatic breakdown point will always be MO1111. As is clear from FIG. 3(a), the modification of the seat between the source line and the gate line is only required for the charge effect transistor. This is possible by separating from line 10, and by this correction, only the pixel concerned by each display defect is required. In this way, unlike line defects, pixel defects do not cause any display problems, especially in large-capacity display devices.

Although the explanation has been given using a liquid crystal display device using a Mos type field effect transistor as an example of a non-linear element, other non-linear elements such as an element with a three-layer structure consisting of a metal and an insulating film (
M! M) Any element may be used, and the display may be of any type other than liquid crystal, such as plasma, electroluminescence, etc. Purpose 4 of the present invention: Using a nonlinear element as a switching element, a plurality of gate lines and a plurality of source lines can be connected. In matrix arrays, the dielectric strength voltage between lines is made higher than that of the switching elements, and this makes it possible to correct twin defects caused by electrostatic damage such as static electricity into pixel defects, and improves the display panel. This greatly increases the effectiveness of mass production, and the effect is particularly great when a matrix array is constructed on a glass substrate and it is impossible to provide electrostatic countermeasure devices (diodes, resistors, etc.) within the substrate.

[Brief explanation of drawings]

1'6!4 is a layout diagram showing an example of the structure of a matrix array, and FIG. 2 is a wiring diagram showing an equivalent circuit of an example of a matrix array display device using liquid crystal as a display body. FIG. 3 is a structural diagram showing an example in which the present invention is applied to the example of FIG. 2, in which (α) is a plan view and Cb) is a sectional view. 2......Switching element 5.9.
...Gate line 4.10...Source line 5, $...MOHWl field effect transistor line 5...Gate insulating film 15... ...Interlayer insulating film ((2) Figure 3 = 224-

Claims (1)

[Scope of Claims] t A plurality of gate lines, a double B input line formed orthogonally to the plurality of gate lines via the plurality of gate lines and an insulating layer, and a plurality of gate lines and the plurality of gate lines. A matrix array comprising non-linear switching elements provided at intersections of a plurality of source lines, wherein the electrical breakdown voltage of the insulating layer is greater than the electrical breakdown voltage of the non-linear switching elements. 2. The matrix array according to claim 1, wherein the matrix array is formed on a glass plate.