JPS58130562A - Thin film transistor matrix substrate - Google Patents

Thin film transistor matrix substrate

Info

Publication number
JPS58130562A
JPS58130562A JP57012730A JP1273082A JPS58130562A JP S58130562 A JPS58130562 A JP S58130562A JP 57012730 A JP57012730 A JP 57012730A JP 1273082 A JP1273082 A JP 1273082A JP S58130562 A JPS58130562 A JP S58130562A
Authority
JP
Japan
Prior art keywords
gate
breakdown voltage
line
crossover part
thin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57012730A
Other languages
Japanese (ja)
Other versions
JPH036668B2 (en
Inventor
Koichi Oguchi
小口 幸一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP57012730A priority Critical patent/JPS58130562A/en
Publication of JPS58130562A publication Critical patent/JPS58130562A/en
Publication of JPH036668B2 publication Critical patent/JPH036668B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Liquid Crystal (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To facilitate the repair work, in a transparent insulating substrate wherein thin film transistors are arranged at the intersections of a plurality of gate lines and data lines which cross at a right angle, by making the breakdown voltage of the gate insulating film of each transistor smaller than the insulation breakdown voltage at the crossover part of each line. CONSTITUTION:The thin film transistor 5 is connected to each crossover part 6 of the data line 1 and the gate line 2. In this constitution, when the insulation breakdown voltage of the insulation film of the crossover part 6 is relatively small, the lines 1 and 2 are shorted at the crossover part 6. This shortage results in the line fault, which is a serious problem is a liquid crystal display device. Therefore, the breakdown voltage of the gate insulating film of the thin film transistor 5 that is corrected to the crossover part 6 is made smaller than the breakdown voltage of the crossover part 6. If static electricity flows at an emergency, the breakdown is limited to one of the transistors 5 and the accident such as the line fault is decreased to zero.

Description

【発明の詳細な説明】 不発明に、博+m )ランジスタ(以下では略してTI
PTと書く)基板に関するものである。さらに本発明1
1TFテマトリツクス基板の1気特性に関するものであ
る。
[Detailed Description of the Invention] Inventively, B+m) transistor (hereinafter abbreviated as TI)
(written as PT) is related to the board. Furthermore, present invention 1
This relates to the 1-temperature characteristics of a 1TF te matrix substrate.

近年、従来のCRTディスプレイに代る新しいディスプ
レイの開発が盛んに行なわnる桶になって来た。その中
ても液晶ディスプレイは、薄型であシ、低電圧低電力動
作が可能であるため、パーソナルな情報機器のディスプ
レイあるいは携帯可能な情報機器のディスプレイとして
注目さn1電卓腕時計はもとより、家電、自動車のディ
スプレイとして大きな市場が期待されている。この様な
中で今後液晶ディスプレイに要求さnる特性は、大容量
表示能力であろう。すなわち、最初(ゲスタテイック駆
動から時分割駆動となり、液晶材料の開発によル横方向
の走査線の畿が約60不程度まで表示出来、る様になっ
て来たのが現状である。しかし液晶材料開発も限界に来
ておシ、これ以上表示走査層の数管増やすには、アクテ
ィブマトリックス方式を採用しなけnば難しい。この様
なW景から、最近、アクティブマトリックス方式を用い
た沿晶表不袈債の開発が盛んに行なわnている。
In recent years, new displays to replace conventional CRT displays have been actively developed. Among these, liquid crystal displays are thin and can operate at low voltage and low power, so they are attracting attention as displays for personal information devices and portable information devices, as well as N1 calculators and watches, home appliances, and automobiles. A large market is expected for this display. Under these circumstances, a characteristic that will be required of liquid crystal displays in the future will be large capacity display capability. In other words, with the shift from gestatic drive to time-division drive, and the development of liquid crystal materials, it has now become possible to display horizontal scanning lines with a width of about 60 degrees. Material development has reached its limit, and it is difficult to increase the number of display scanning layers further without adopting an active matrix method.In light of this W view, recently, crystalline crystallization using an active matrix method has been developed. Development of non-exclusive bonds is actively underway.

アクティブマトリックス方式の中でも、MOS(金属−
醗化物−半導体素子)アレイ管用いた奄のと、TFTア
レイを用いたものがある。前者は周辺ドライバーがオン
チップ出来るため小面積、簡密常表示体装澹として通し
ており、後者は大面積、高V!!度の表示体装誼に通し
ている。また表示品繊の点からは、後者の場合はTPT
プレイは透明絶縁jlk板上に形成出来るため液aS示
モードとしてはTNモードが可能であり、コントラスト
は鳩い。
Among active matrix methods, MOS (metal-
There are two types: one using an array tube (fluoride-semiconductor element) and the other using a TFT array. The former has a small area and a simple high-density display because the peripheral driver can be on-chip, while the latter has a large area and high V! ! The degree of display is consistent with the body design. In addition, from the viewpoint of the indicated product fiber, in the latter case, TPT
Since the play can be formed on a transparent insulating JLK board, the TN mode is possible as the liquid aS display mode, and the contrast is sharp.

従来のTPTアクティブマトリックスS板の平面図、断
面構造図及び回路図を第1図に示す。第1図(al[T
 F Fアクティブマトリックス基板の画1象表示−城
のS酸単位である一画素の平面図である0図中の1にデ
ータgA号ライン、2はゲート信号ライン、3はIjl
@表示電極である。このIIiIg11表示電檎は通表
示電属1極でもよいし、また透明導寒s’m極でもよい
。4はTFTのソース領域とデー タフインとのコンタ
クトホール、及ヒT P T Oドレイン領域と画gI
表示電極とのコンタクトホールである。5はTPTであ
る。6dデ一タ18号ラインとゲート信号ラインのクロ
スオー/<  g分であり、通常は、このデータ信号ラ
イイとゲート信号ラインとは酸化膜あるいは窒化層等の
薄庫絶縁膜にて電気的に分離さnている0図中の一点一
一にて囲まれた領域が一画素の領域である。第18!1
(a)中のムーム断面1mtIJI41 h(bztc
示”r。図中)7はTIFTのゲート酸化層、8t’j
TFTのソース−ドレイン拡散領域、9は絶m¥iであ
る。第1図(0)は−1!j素の回路自である。このよ
うな従来のτIFTアクティブマトリックス!ilK&
いてt’l、第211に示す如くゲートライン及びデー
タラインは1職の外l1111Iに端子取シ出し用のパ
ッドがθ灯らnておシ、こnらはドライバ胞路へとm続
さnている・この端子取9出し用パッドは一本のゲート
ラインあるいれ一本のデータラインに少なくとも−wあ
nばよい。このTPTアクティブマトリックス道*Fi
、第1図にて示した如く絶縁基叛上にTFTアレイを形
成しているために静電気に対して非常に弱いという欠点
がある。例えばTPTアクティブマトリックス基板の外
Ii!i1部の端子取り出しパッドから静電気が入ると
、靜v1槃はTPTのゲート絶−一もしくはゲートライ
ンとデータラインのクロスオーバ一部の絶−一のどちら
かを破壊する。
FIG. 1 shows a plan view, a sectional structure diagram, and a circuit diagram of a conventional TPT active matrix S board. Figure 1 (al[T
FF Active matrix substrate picture representation - A plan view of one pixel which is a castle's S acid unit. In the picture, 1 is the data gA line, 2 is the gate signal line, and 3 is the Ijl
@Display electrode. This IIIiIg11 display electrode may be a single electrode with a transparent conductor, or may be a transparent conductive s'm electrode. 4 is a contact hole between the TFT source region and data in, and the TFT drain region and image gI.
This is a contact hole with the display electrode. 5 is TPT. 6d data line No. 18 and gate signal line cross-over/<g min. Normally, this data signal line and gate signal line are electrically separated by a thin insulation film such as an oxide film or a nitride layer. The area surrounded by points 11 in the diagram is a one pixel area. No. 18!1
(a) Moum cross section 1mtIJI41h(bztc
(in the figure) 7 is the gate oxide layer of TIFT, 8t'j
The TFT source-drain diffusion region 9 is absolutely m\i. Figure 1 (0) is -1! It is the j-element circuit itself. Such a conventional τIFT active matrix! ilK&
t'l, as shown in No. 211, the gate line and data line are connected to the outside of the 1st position, and the pad for terminal extraction is lighted at θ, and these are connected to the driver channel. The pad for bringing out the terminal 9 should be connected to at least one gate line or one data line. This TPT active matrix path*Fi
As shown in FIG. 1, since the TFT array is formed on an insulating substrate, it has the drawback of being extremely susceptible to static electricity. For example, outside of TPT active matrix substrate Ii! When static electricity enters from the terminal extraction pad of the i1 section, the static electricity destroys either the gate of the TPT or the part of the crossover between the gate line and the data line.

靜111気Fi通常電圧が数千ボルトから数万ボルトで
あるので、もし靜II気が入nば必ずこれらの絶縁−に
破壊し、ショート状態か低抵抗にて接続さnることにな
る。したがって、TPTアクティブマトリックス基板の
製造プロセスにおいては、静電気対震ン十分付なう必豊
かある。ま7iTFTアクティブマトリックス1板士に
MOBils板において行なわnている如く抵抗やダイ
オード回路を入nた静1気保循回路を入nられnばよい
が、今のところ物性上刃・らこnらの静WX保護回路’
iT IFTアクティブマトリックス基板上に形成する
ことはむづかしい。したがってTPTアクティブマトリ
ックス差板においては、靜1気が入った場合には、どこ
か特定の場所が破壊する様に股引し、その場所は後でレ
ーザー等による配線の切断にて修正することを考える必
要がある。
Since the normal voltage for the insulation is from several thousand volts to tens of thousands of volts, if the insulation is applied, it will definitely break down to these insulations, resulting in a short circuit or connection with low resistance. Therefore, in the manufacturing process of the TPT active matrix substrate, it is necessary to provide sufficient electrostatic countermeasures. It would be better if the 7iTFT active matrix 1 board could be equipped with a static circulation circuit with resistors and diode circuits, as is done in the MOBils board, but for now, the physical properties 'Static WX protection circuit'
iT IFT is difficult to form on active matrix substrates. Therefore, in the case of a TPT active matrix difference plate, if a problem occurs, it is recommended to pull it out in such a way as to destroy it in a specific location, and then repair that location later by cutting the wiring using a laser or the like. There is a need.

本発明はこのような静電気に弱いTPT了クチイブマト
リックス基板において、万−静電気が入った時、ある特
定の場所で破壊する様にし、この場所は後で修正すると
いう考え方に基づいたTFTアクティブマトリックス基
板に関するものであり、以下具体的な実施例管あげて説
明する。
The present invention is a TFT active matrix based on the idea that when static electricity enters a TPT active matrix substrate that is weak against static electricity, it will be destroyed at a specific location, and this location will be repaired later. The present invention relates to a substrate, and will be explained below using specific examples.

ais s txi(&)u、T]FT7/?(ブw)
 リy9x4板に静電気が入った時、ゲートライン2と
データライン1のクロスオーバーs6の絶I#―が破壊
した場合會示す。このクロスオーバ一部が破壊する場合
は、TFT5のゲート絶縁膜の絶縁破壊電圧よりもこの
クロスオーバ一部の絶縁膜の絶−破壊電圧の方が小さい
場合である。この場合には、このクロスオーバ一部でゲ
ートラインとデータラインがショートするためKlll
a表示体装潰等に応用した場合には線欠陥となって表わ
れるために大きな問題となる。したがってjlll!3
図(b)の10及び第3図(c)のIIK示す如くこの
クロスオーバーStねさんでゲートラインあるいはデー
タラインの両@tレーザーで修正する必費がある。例え
ば第3図(b)の如くゲートラインt−2カ所レーザー
にて切断し、このゲートラインの両側に設けた端子取)
出しパッドからゲートca号管入nれは良い。しかしこ
の場合に、両側の端子取シ出しパッドに同じゲート情1
r入nるためには、ゲートドライバ回路は2系列必賛と
なる。ゲートドライバ回路t−2系列入nることはコス
トの点η為ら難しいため普通Fi隣シのゲートラインの
信号を入力することになる。この場合、l111#)合
うゲートラインは同じ表示をすることになり表示欠陥と
なる。wJ3図(c)の場合も同じ′″Cある。
ais s txi (&) u, T] FT7/? (B lol)
A case is shown in which the disconnection I#- of the crossover s6 between gate line 2 and data line 1 is destroyed when static electricity enters the 9x4 board. When a portion of this crossover breaks down, the breakdown voltage of the insulating film of this portion of the crossover is smaller than the breakdown voltage of the gate insulating film of the TFT 5. In this case, the gate line and data line are shorted in a part of this crossover, so Kllll
When applied to the destruction of a display body, etc., it becomes a big problem because it appears as a line defect. Therefore jllll! 3
As shown at 10 in FIG. 3(b) and IIK in FIG. 3(c), it is necessary to correct both the gate line and the data line with @t laser in this crossover St-nes. For example, as shown in Figure 3(b), the gate line t-2 places are cut with a laser, and the terminals are provided on both sides of this gate line)
The entry from the exit pad to the gate is good. However, in this case, the same gate information is applied to the terminal exit pads on both sides.
In order to enter R, two series of gate driver circuits are required. Since it is difficult to input the gate driver circuit t-2 series due to the cost η, the signal from the gate line adjacent to Fi is usually input. In this case, the matching gate lines (l111#) will display the same display, resulting in a display defect. The same ``''C exists in the case of wJ3 figure (c).

一方、第4図(a)に示す如くクロスオーバ一部の絶−
破mw圧をゲート絶ill膜の破tIs電圧よシ大きく
した場合には、静電槃の入力によって必ずゲート絶−1
4が破壊さnる。この時ゲート電極とソース拡散層がシ
ョートすると前P実施例にて示した様な表示欠陥(線欠
陥)となる。しかしこの場合には、第4図(bJ及び(
c)にて示す如く、各□□□中の12及び13の部分管
レーザーで切断すnI/is易に線欠陥が点欠陥に変換
できることになる。すなわち、クロスオーバ一部の絶縁
破壊電圧を、TPTのゲート絶縁破壊電圧よりも天真<
シておくことによシ、外部から入る静′lI気により破
壊する場合には必ずゲート絶縁膜が破壊することになり
、この場合の方が容易にレーザーにて修正が出来る。
On the other hand, as shown in Fig. 4(a), a part of the crossover
If the rupture mw pressure is made larger than the rupture tIs voltage of the gate isolation film, the gate isolation will always be -1 due to the input of the electrostatic force.
4 will be destroyed. At this time, if the gate electrode and the source diffusion layer are short-circuited, a display defect (line defect) as shown in the previous P embodiment occurs. However, in this case, Figure 4 (bJ and (
As shown in c), line defects can be easily converted into point defects by cutting with the 12 and 13 partial tube laser in each □□□. In other words, the breakdown voltage of a part of the crossover is lower than the gate breakdown voltage of TPT.
If the gate insulating film is destroyed by static air entering from the outside, the gate insulating film will definitely be destroyed, and in this case it can be repaired more easily with a laser.

本発明は上P実施例において説明した如く、静電気に弱
いTIF’!’アクティブマトリックスS板において、
ゲートラインとデータラインのクロスオーバ一部の絶縁
破壊電圧をゲート屡の絶縁破壊電圧よシも大きくするこ
とにより、万−静w凭で破壊し次場合に容易にレーザー
で修正が出来るようにし7j??Tアクテイブマトリツ
クス基板に関するものであシ、液晶表示体装置やエレク
トロルンネツセンス表示体装置用のTIFTアクティブ
マトリックス基板の歩留シ向上、コスト低減に大きく貢
献するものである。
As explained in the above P embodiment, the present invention uses TIF'! which is weak against static electricity! 'In the active matrix S board,
By increasing the dielectric breakdown voltage of a portion of the crossover between the gate line and the data line as compared to the dielectric breakdown voltage of the gate, it can be destroyed in a single vacuum and can be easily repaired using a laser in the next case. ? ? The present invention relates to TIFT active matrix substrates and greatly contributes to improving the yield and reducing costs of TIFT active matrix substrates for liquid crystal display devices and electroluminescence display devices.

例えば本発明の如くクロスオーバ一部の絶縁破壊電圧七
ゲート破壊電圧よりも大きくする方法は多くある。すな
わちクロスオーバ一部の絶−膜とTPTのケート絶II
s膜t−一の膠質で構成する場合にはクロスオーバ一部
の絶縁膜の膜厚をゲート層厚よりも厚くすnばよい0例
えばゲート絶縁膜oNjlttoooXとした時、クロ
スオーバ一部の絶−膜の膜厚は1oooX以上の200
0〜1o oo oX程度が望ましい。またクロスオー
バ一部の絶−膜厚とゲート絶縁膜厚が同じでも破壊電圧
がクロスオーバ一部の方が大きくなる様にプロセス設計
、パターン設引することが望ましい。
For example, as in the present invention, there are many ways to make the dielectric breakdown voltage of the crossover part larger than the gate breakdown voltage. In other words, the cross-over part of the insulation film and the TPT insulation II
In the case of s film t-1 made of colloid, the film thickness of the insulating film in a part of the crossover may be made thicker than the gate layer thickness.For example, when the gate insulating film is oNjlttooooX, -The film thickness is 1oooX or more 200
A value of about 0 to 1 o oo oX is desirable. Further, it is desirable to design the process and design the pattern so that even if the insulation film thickness of the crossover part and the gate insulating film thickness are the same, the breakdown voltage is larger in the crossover part.

例えば絶縁−として810.Illll−る場合、多少
のリン濃度の違いによ)破壊電圧は異なる。またB10
.形成後のアニール1jAwIの違いによっても破壊電
圧は異なる。さらに配111!itlの段差形!R−に
よっても破壊電圧は異なるのでTIPTアクティブマト
リックス4板のデバイス設計、プロセス設計には十分注
意が必要である。
For example, 810. In this case, the breakdown voltage will differ depending on the slight difference in phosphorus concentration. Also B10
.. The breakdown voltage also differs depending on the annealing 1jAwI after formation. Furthermore, the distribution is 111! itl step shape! Since the breakdown voltage varies depending on R-, sufficient care must be taken in the device design and process design of the four TIPT active matrix boards.

第5図は、透明絶縁基板、上に形成したTPTアクティ
ブマトリックス基@ 14 iH用い7(Tliモード
(ツイストネマ千ツクモード]の液晶表示体装置の断面
図である。15は上側ガラス基鈑、16はスペーサ、1
7は液晶層、18tlj偏光板、19は反射板である・
このTNモード液晶表示体装置社コントラストも高く明
るい表示が得らn1小潅ポケツトテレビ用のディスプレ
イとしてハ最適である。
FIG. 5 is a cross-sectional view of a liquid crystal display device using a transparent insulating substrate and a TPT active matrix group @ 14 iH formed thereon (Tli mode (twisted nematic mode). 15 is an upper glass substrate, 16 is a Spacer, 1
7 is a liquid crystal layer, 18tlj polarizing plate, 19 is a reflection plate・
This TN mode liquid crystal display device provides a high contrast and bright display, making it ideal as a display for N1 small pocket televisions.

【図面の簡単な説明】[Brief explanation of drawings]

8111図及びM2図社従来の’rF?アクティブマト
リックス基板の構成及び胞路管説明する図、第3図及び
第4図は、本発明によるTFTアクティブマトリックス
基板の*Wta明するために用いた回路図、第5図は本
発明によるTFTアクティブマトリックス基板を用いた
液晶表示体装置の構造図。 1・・・データライン 2・・・ゲートライン 3・・・液晶駆動電極 4・・・コンタクトホール 5・・・丁FT 6・・・クロスオーバ一部 7・・・ゲート絶縁膜 8・・・ソース、ドレイン拡散領域 9・・・絶縁基板 10・・・ゲートライ/のレーザー溶断部11・・・デ
ータラインのレーザー溶断部12・・・TFTのゲート
電極のレーザー溶断部13・・・ソース抗散電極のレー
ザー溶断部14・・・TPTアクティブマトリックス基
板15・・・上側カラス板 16・・・スペーサ 17・・液晶層 18・・・偏光板 19・・・反引板 以   上 (C) 第1図 第2[1 第3図 第4図
8111 figure and M2 figure company's conventional 'rF? Figures 3 and 4 are circuit diagrams used to explain the structure and cell channels of the active matrix substrate, and Figure 5 is a circuit diagram used to explain the structure of the TFT active matrix substrate according to the present invention. A structural diagram of a liquid crystal display device using a matrix substrate. 1... Data line 2... Gate line 3... Liquid crystal drive electrode 4... Contact hole 5... FT 6... Crossover part 7... Gate insulating film 8... Source and drain diffusion region 9...Insulating substrate 10...Laser fusing part 11 of gate line/laser fusing part 12 of data line...Laser fusing part 13 of gate electrode of TFT...Source diffusion Laser-fused portion of electrode 14... TPT active matrix substrate 15... Upper glass plate 16... Spacer 17... Liquid crystal layer 18... Polarizing plate 19... Anti-pulling plate and above (C) 1st Figure 2 [1 Figure 3 Figure 4

Claims (1)

【特許請求の範囲】 … 祷砂本のゲートラインと、それに直交する祷数杢の
データラインの各交点に薄膜トランジスタを配譚した薄
胛トランジスタマトリックス基板ニオイて、[I#)ラ
ンジスタのゲート絶縁膜の破壊電圧は、該ゲートライン
と該データラインのクロスオーバー−の絶−ms’ts
圧よpも小さいことt*mとする薄膜トランジスタマト
リックス1板。 12+4−)ランジスタを配オした基板は透明絶縁基板
であることtI#eとする特許請求の範囲第一項P載の
薄−トランジスタマトリックス基板
[Claims] ... A thin-film transistor matrix substrate in which thin-film transistors are arranged at each intersection of a gate line and a data line orthogonal thereto, and a gate insulating film of an [I#] transistor. The breakdown voltage of the gate line and the data line is
Thin film transistor matrix 1 plate, where the pressure and p are also small, t*m. 12+4-) The thin transistor matrix substrate according to claim 1 P, wherein the substrate on which the transistors are arranged is a transparent insulating substrate.
JP57012730A 1982-01-29 1982-01-29 Thin film transistor matrix substrate Granted JPS58130562A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57012730A JPS58130562A (en) 1982-01-29 1982-01-29 Thin film transistor matrix substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57012730A JPS58130562A (en) 1982-01-29 1982-01-29 Thin film transistor matrix substrate

Publications (2)

Publication Number Publication Date
JPS58130562A true JPS58130562A (en) 1983-08-04
JPH036668B2 JPH036668B2 (en) 1991-01-30

Family

ID=11813551

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57012730A Granted JPS58130562A (en) 1982-01-29 1982-01-29 Thin film transistor matrix substrate

Country Status (1)

Country Link
JP (1) JPS58130562A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58178553A (en) * 1982-04-13 1983-10-19 Seiko Epson Corp Matrix array

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58178553A (en) * 1982-04-13 1983-10-19 Seiko Epson Corp Matrix array

Also Published As

Publication number Publication date
JPH036668B2 (en) 1991-01-30

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