JPS58178428A - Data processor - Google Patents

Data processor

Info

Publication number
JPS58178428A
JPS58178428A JP57061055A JP6105582A JPS58178428A JP S58178428 A JPS58178428 A JP S58178428A JP 57061055 A JP57061055 A JP 57061055A JP 6105582 A JP6105582 A JP 6105582A JP S58178428 A JPS58178428 A JP S58178428A
Authority
JP
Japan
Prior art keywords
option
option setting
setting item
data
contents
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57061055A
Other languages
Japanese (ja)
Inventor
Kazutoshi Washio
鷲尾 和俊
Seiichiro Yamamoto
征一郎 山本
Toshiaki Koyama
俊明 小山
Hiroshi Iwamoto
博志 岩本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57061055A priority Critical patent/JPS58178428A/en
Publication of JPS58178428A publication Critical patent/JPS58178428A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44Arrangements for executing specific programs
    • G06F9/445Program loading or initiating

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Stored Programmes (AREA)

Abstract

PURPOSE:To eliminate the pin neck of an LSI and a package by reading the contents of an option setting part before a device is used and writing them in the option setting contents storage register in the device successively. CONSTITUTION:When the power source of a data processor is turned on or when an initial microprogram is loaded, an option setting item processing part 25 follows a predetermined procedure to start reading the setting contents of the option setting part 21 through a scan interface control part 29. After this reading operation, predetermined processing for every read option setting item is carried out. Then, the processing part 25 writes option data in the option setting item storage register 23 lastly. Once all optional data are set in the register 23, the device is usable.

Description

【発明の詳細な説明】 発明の対象 本発明はオブシ曽ン設定部の設定内容により装置動作が
決定されるデータ処理装置に関する。
DETAILED DESCRIPTION OF THE INVENTION Object of the Invention The present invention relates to a data processing apparatus in which the operation of the apparatus is determined by the settings of an obscene setting section.

なおここで云うオプシ胃ンとは、当該データ処理装置に
接続される相手装置の動作モードや、接続される回線の
種類等、システム環境により選択する項目や顧客のシス
テム使用形態等により選択する項目の総称を意味する。
Note that the optional operations mentioned here refer to items that are selected depending on the system environment, such as the operation mode of the partner device connected to the data processing device, the type of line to be connected, etc., and the items that are selected depending on the customer's system usage pattern. It means a general term for.

オグシ1ン設定項目の具体例としては、装置アドレス、
メモリサイズ、動作モード、回線属性等の設定がある。
Specific examples of setting items include device address,
There are settings for memory size, operation mode, line attributes, etc.

従来技術 従来のデータ処理装置においては、オプション設定内容
の取り込みは、第1図に示すように、スイッチ4及びプ
ルアンプ抵抗3より成るオプション設定部10オプショ
ン項目と同数の出力信号を、直接装置動作決定部2へ引
き込む方式であった。この方式では、オプシ■ン設定部
1と装置lr動作決定部2間にオプション項目と同数の
信号線が必要であり、両部が別のパッケージ内にある場
合、パッケージのピンネックの原因となっていた。又、
LSI化されたデータ処理装置においては、ジャンパー
線、又はスイッチで成っているオプシ冒ン設定部1はL
SI化田来ない為LSI外に置かざるを得なく、LSI
のピンネックとなり・LSI数が増加するという欠点が
あった。
PRIOR ART In a conventional data processing device, as shown in FIG. 1, an option setting section 10 consisting of a switch 4 and a pull amplifier resistor 3 outputs the same number of output signals as option items to directly determine the device operation. It was a method to draw them into part 2. In this method, the same number of signal lines as the option items are required between the option setting section 1 and the device lr operation determining section 2, and if both sections are in different packages, this may cause a pin neck in the package. Ta. or,
In an LSI-based data processing device, the option setting section 1 consisting of a jumper wire or switch is connected to the LSI.
Since it cannot be converted into an SI, it has to be placed outside the LSI, and the LSI
This has the disadvantage of causing a pin neck and increasing the number of LSIs.

兄明の目的 本発明の目的は、前述の欠点を除去したデータ処理装置
を提供することにあり、オプシ曹ン設定項目処理部によ
るオプションデータM!取り込み法によるL S Iあ
るいはパッケージのピンネックを解消する手段を提供す
ることにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a data processing device that eliminates the above-mentioned drawbacks, and to provide a data processing device that eliminates the above-mentioned drawbacks. The object of the present invention is to provide a means for eliminating pin necks in LSI or packages caused by the loading method.

本発明の特徴とするところは、オプシ曹ン設定内容によ
り装置動作が決まるデータ処理装置において、オプショ
ンデータの設定内容を読み取る手段と1読み取った内容
に必要な処理を加え装置内の任意のレジスタにセットす
る手段とを具備することにより、装置使用前にオプショ
ンデータの内容を読み取り、読み取った内容に必要な処
理を加えた後、順次装置内のオプシ■ン設定内容記憶レ
ジスタに書き込むという方式を採用したことにある。
The present invention is characterized in that, in a data processing device where the device operation is determined by the option data settings, there is a means for reading the option data settings; This method reads the contents of option data before using the device, performs the necessary processing on the read contents, and then sequentially writes them to the option settings storage register in the device. It's what I did.

発明の実施例 以下、本発明の一実施例を第2図により説明する。Examples of the invention An embodiment of the present invention will be described below with reference to FIG.

第2図は本発明の一実施例であるデータ処理装置のオプ
ションデータ取り込み部のフロック図である。
FIG. 2 is a block diagram of an option data importing section of a data processing device according to an embodiment of the present invention.

21はオプシ四ン項目を設定するスイッチ28及びプル
アンプ抵抗27等で成っているオフ シmン設定部、2
2はオノシ膳ン設定部21で設定したオプションデータ
を基に装置動作を決定する制御回路等より成るLSI、
23はオブシシン設定項目処理部25がものオプション
データな記憶1−るオプン日ン設足項目記憶レジスタ1
24はオプシ厘ン設1fi521のオフシ田ン内答を読
み取ったり、オプション設定項目記憶レジスタ23ヘオ
プシ9ンテータを書き込んだりするのに使用するインタ
ーフー−ス、25は第1シ1ン設定fA21の設定内容
を読み・設足項目毎に必要な処理を行なった後、オプシ
璽ン設定項目記憶レジスタ26にセントする迄の一連の
処理を実行するオプン冒ン設定項目処理部、29はオグ
シ1ン設定項目処理部25がもの1h令を解読し、指示
されたスイッチ28の内容ンイ/メーフェース24上に
ビットシリアルに送出する制御を行なうスキャンインタ
フェース制御部である。26はオプシ習ン設定項目記憶
レジスタ26からの出方信号を受け・装置動作を決定す
る装置動作決定回路である。データ処理装置内では、装
置動作決定回路26の出刃信号を用い、指示された処理
が行なわれる。なお、以上によれば、L8122111
1にインターフェース24用のピン及び回路が必要とな
るが、このピンはLSIの診断な容易にするために一般
的に設けているピンや回路(LSI内レジスタにスキャ
ンイン、スキャンアウトするためのピンや回路)を利用
する。
Reference numeral 21 denotes an off-switch setting section consisting of a switch 28 for setting optional items, a pull amplifier resistor 27, etc.;
2 is an LSI consisting of a control circuit etc. that determines the operation of the device based on the option data set by the onoshizen setting section 21;
23 is an optional data storage register 1 for the optional setting item processing section 25.
Reference numeral 24 denotes an interface used for reading the input information of the option setting item 1fi521 and writing the option input to the option setting item storage register 23, and 25 refers to the setting of the first scene setting fA21. After reading the contents and performing the necessary processing for each setting item, an open setting item processing unit executes a series of processes until it is stored in the optional setting item storage register 26. 29 is an automatic setting item processing unit. The item processing section 25 is a scan interface control section that controls the decoding of the 1h command and transmitting the specified contents of the switch 28 onto the interface 24 in a bit serial manner. 26 is a device operation determining circuit that receives an output signal from the optional learning setting item storage register 26 and determines the device operation. In the data processing device, the instructed processing is performed using the cutting signal from the device operation determining circuit 26. According to the above, L8122111
1 requires a pin and circuit for the interface 24, but this pin is a pin and circuit that is generally provided to facilitate LSI diagnosis (a pin for scanning in and out of registers in the LSI). and circuits).

次に本実施例の動作説明を行なう。Next, the operation of this embodiment will be explained.

データ処理装置の電源オン時やイニシャルマイクロプロ
グラムロード時、オグシW/設定項目処理fM!、25
は、あらかじめ決められた手1謹に従い、スキャンイン
タフェース制御部29を介してオプションデータ21の
設定内容を読み取る動作を開始する。この読み取り動作
が終了すると、読み取ったオクシ望ン設定項−毎に、め
らかじめ決められた処理を実行する。この決められた処
理とは、読み出したデータを反転したり、演算を行なっ
たり等の処理内容である。
When the data processing device is powered on or the initial microprogram is loaded, Ogusi W/setting item processing fM! , 25
starts the operation of reading the setting contents of the option data 21 via the scan interface control section 29 according to a predetermined procedure. When this reading operation is completed, a predetermined process is smoothly executed for each desired setting item read. The predetermined processing includes processing such as inverting read data and performing calculations.

この処理が終わると、オプシ■ン設定項目処理部25は
最後にオプションデータをオフシーン設定項目記憶レジ
スタ23に書き込んでいく。
When this process is completed, the option setting item processing section 25 finally writes the option data into the off-scene setting item storage register 23.

オプシW/設定項目配憶レジスタ23へ全てのオプショ
ンデータを設定し終ると、装置は使用可能な状態となる
When all option data has been set in the option W/setting item storage register 23, the device becomes ready for use.

発明の効果 以上述べた様な本発明にあっては、次の如き効果を得る
ことができる。
Effects of the Invention With the present invention as described above, the following effects can be obtained.

(1)オプションデータからの設定内容を示す信号線を
、直接、装置内回路に引き込む必要がない為、LSIや
パッケージのピンネックが解消され、少数のLSIやパ
ンケージで装置が実現できる。
(1) Since there is no need to directly lead the signal line indicating the setting contents from the option data into the circuit within the device, pin necks in LSIs and packages are eliminated, and the device can be realized with a small number of LSIs and pancakes.

【図面の簡単な説明】 第1図は従来のオプシB7設定部と装置動作決定部間の
インターフェース概念図、第2図は本発明の一実施例を
示す図である。 第2図において、 21・・・オプシ層ン設定部 22・・・LSI 23・・・オフシ璽ン設定項目記憶レジスタ24・・・
インターフェース 25・・・オプシ肩ン設定項目処理部 26・・・装置動作決定回路 29°°゛スキヤンインタフ工−ス制御部′7  1 
  図
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a conceptual diagram of an interface between a conventional Option B7 setting section and a device operation determining section, and FIG. 2 is a diagram showing an embodiment of the present invention. In FIG. 2, 21...option layer setting unit 22...LSI 23...offset setting item storage register 24...
Interface 25...Optional setting item processing unit 26...Device operation determining circuit 29°° Scan interface control unit'7 1
figure

Claims (1)

【特許請求の範囲】[Claims] 装置使用前にあらかじめ設定しておく必要のあるオプシ
璽ン設定部を有するデータ処理装置において、前記オプ
シ曹ン設定部の設定内容を読み取り、当該設定内容に必
要な処理を加えるオブシ厘ン設定項目処理部と、当該オ
プシーン設定項目処理部からの出力を記憶しておくオプ
ション設定項目記憶レジスタとを具備したことを特徴と
するデータ処理装置。
In a data processing device that has an option setting section that needs to be set in advance before using the device, an option setting item that reads the settings of the option setting section and adds necessary processing to the settings. A data processing device comprising: a processing section; and an option setting item storage register that stores an output from the option setting item processing section.
JP57061055A 1982-04-14 1982-04-14 Data processor Pending JPS58178428A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57061055A JPS58178428A (en) 1982-04-14 1982-04-14 Data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57061055A JPS58178428A (en) 1982-04-14 1982-04-14 Data processor

Publications (1)

Publication Number Publication Date
JPS58178428A true JPS58178428A (en) 1983-10-19

Family

ID=13160131

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57061055A Pending JPS58178428A (en) 1982-04-14 1982-04-14 Data processor

Country Status (1)

Country Link
JP (1) JPS58178428A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61112428U (en) * 1984-12-25 1986-07-16

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5313818A (en) * 1976-07-23 1978-02-07 Toshiba Corp Signal transmission system
JPS5368938A (en) * 1976-12-01 1978-06-19 Mitsubishi Electric Corp Interface circuit by serial transmission
JPS5676822A (en) * 1979-11-27 1981-06-24 Ricoh Co Ltd Control system for input/output device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5313818A (en) * 1976-07-23 1978-02-07 Toshiba Corp Signal transmission system
JPS5368938A (en) * 1976-12-01 1978-06-19 Mitsubishi Electric Corp Interface circuit by serial transmission
JPS5676822A (en) * 1979-11-27 1981-06-24 Ricoh Co Ltd Control system for input/output device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61112428U (en) * 1984-12-25 1986-07-16

Similar Documents

Publication Publication Date Title
JPS58178428A (en) Data processor
JP2961754B2 (en) Parallel processing unit of information processing device
JPH0535487A (en) System for loading operation system
JP2747154B2 (en) I / O processor
JP2639927B2 (en) Test method for control device in data processing system
JP2884620B2 (en) Digital image processing device
JPH05290589A (en) Semiconductor integrated circuit
JPS6312035A (en) Information processor
JPH0554666A (en) Memory device
JPH0325539A (en) Storage device
JPS63147269A (en) Test system for drawing reading device
JPH05342117A (en) Channel device
JPH023147B2 (en)
JPH02307149A (en) Direct memory access control system
JPH0362218A (en) Electronic disk subsystem
JP2000148574A (en) Device and method for register control
JPS60252400A (en) Voice synthesizer
JPS6217844A (en) Information processor
JPH058646U (en) Memory device
JPS60250435A (en) Information processor
JPS6125180B2 (en)
JPH04127253A (en) Down load control system
JPS5918748B2 (en) Pseudo-error rewriting method
JPH01304556A (en) Memory control circuit
JPS5918749B2 (en) Pseudo error sending method