JPS58175860A - Semiconductor memory unit - Google Patents

Abstract

PURPOSE:To enlarge the storage capacitance value to about two times without enlarging the chip area by a method wherein the capacitors for storage of two memory cells are formed by stacking in the same region on a semiconductor substrate. CONSTITUTION:At the memory unit provided with the plural number of memory cell consisting of an insulated gate field effect transistor MOST and the capacitor for storage on the semiconductor substrate, the capacitors for storage of at least two memory cells are formed stacking mutually in the same region on the semiconductor substrate. Namely, the capacitor 1a for storage on one side is constituted of a region 12a connected to the drain 22a of the MOST, and a word line 4b facing thereto through an insulating film 11. Moreover, the capacitor 1c for storage on another side is constituted by making a poly-silicon layer 32c formed on the word line 4b interposing an insulating film 14 between them, and being connected to the drain 22c of the MOST as an electrode on one side, and by making a poly-silicon word line 4d formed interposing an insulating film 15 between them as an electrode on another side.

Description

DETAILED DESCRIPTION OF THE INVENTION This eleventh article relates to a semiconductor memory device VC using MO8O8 transistors O8T).

Random access memory (RAM) using 141 MO8Ts and 1 capacity per 1-bit message cell
is well known, and FIG. 1 shows its circuit configuration. In the figure, (1m) and (xb) are storage capacities for storing the data of included,
Switching MOBT for protruding or holding a
, (3a) is a first memory cell consisting of a storage capacitor (11) and a switching MO8T (2a);
1)) is a word line to which a signal for controlling the on/off of the storage capacitor (lb) (Sa&) bar 2b) is supplied; (k);
(5b) are memory cells (mu).

(lb) bit line transmitting data, (6a) bar 6'
b) are the parasitic capacitances of Il(5m) and 5b), respectively.

In order for this circuit to operate stably, the word line (4a)
, (4b) When the Tic voltage is applied δ, that is, when reading the memory cell, bit 41 (5a)
It is desirable that the amplitude of the voltage appearing at
It is determined by the capacitance, the parasitic capacitance (6a), and the capacitance (ab) and the magnitude of the voltage.

) The read voltage amplitude AV to M (5a) and (5b) is given by the following equation.

IV, @@ ('v8o-V,.) /(1+ (o
V/a, )) Here, 08 is the memory HA valley (la),
(1b) Volume 1k value, Om is the permeable capacity (aaL(ab
) o capacitance value, vgo and Via if respectively storage capacity (-) bar 1b) of the continuation section and bit line (
5a) and (5b) are the voltage values.

Above formula force (o, Vso, VBO, On constant and LI
It turns out that in order to increase Jvl, Oa should be made thicker.The capacitance value O11 of the O storage capacitor is normally formed on a semiconductor substrate on which a memory cell is formed, and is made of a dangerously insulating saponified film. Most of it is determined by the area, thickness δ, and K.

FIG. 3 is a flat FkJ diagram showing 4 bits of a memory cell according to the prior art, and FIG. 5 is a cross-sectional view taken along the gate single layer line in FIG.
Parts corresponding to the circuit diagram in Figure 1 are given the same reference numerals. Hereinafter, subscripts a and b to distinguish between memory cells (3a) and (3b) will be omitted unless necessary. - forms the p-type semiconductor substrate, (2), and @ forms the source and drain regions of the switching MO8 (2) of the n-type impurity diffusion region 14. The α trout is an n-type region extending from the drain region (2), and a polysilicon layer constituting the word line (4b) is opposed to the n-type forehead region α through an insulating oxide film Nil layer, and is a memory capacitor ( la).

Word # (41)) is also made of a polysilicon layer and is a switching MO8? (2!L) gate electrode is formed, and the storage capacitor (1!L) of the adjacent memory cell (3b) is formed.
b) is connected to one electrode. +II is an insulating oxide film that covers the entire surface, and (ls8.) bar ab) is a bit line provided thereon in a direction perpendicular to the word line (4a) and bar 4b), and the source region (2Xa) t ( 21b
)It is connected to the.

Now, in such a conventional configuration, in order to increase the storage capacity value Cs as described above, the storage capacity Ill (11
It is necessary to increase the area of the memory cell (1ll) or reduce the thickness of its insulating oxide film (1ll), but the former is necessary because the memory cell (1ll) that occupies most of the chip area is
(a) This results in an increase in area and a decrease in yield. Furthermore, the latter method leads to a decrease in chip reliability due to a decrease in dielectric strength.

This invention was made in view of the above points, and it has made the area of the chip and the thickness of the insulating oxide thin film almost the same as that of the conventional chip, and has more than doubled the memory capacitance value 08. The purpose is to stabilize the operation of memory cells.

Figure 34I4 is a plan view showing one embodiment of this invention, and Figure 5 is the 4rI! The cross-sectional view taken along the Marma line of J, FIG. 6, and the 1Mγ view are plan views corresponding to the cross-sections taken along the 1-M line and the ■-■ line in FIG. 5, respectively.

This example includes memory cells (3m), (Sb), (3c).
) and (3i) for 4 bits. Is the storage capacity (theory) of the memory cell formed at the lower left of FIG. 4 a switching MOI of 3? (2a) Drain region (Da)
(above) and the first layer facing each other via an insulating oxide film [1% HIl].
The word line (4b) is connected to the switching MO8 terminal (21) of the memory cell (3b) formed in the upper right corner of the fourth cell.
)) is connected to the gate electrode. (32G) is a relatively thick insulating oxide 151 above word Ml (4b).
The drain region (12a) of the switching MO8T (20) of the memory cell (shi) formed in the upper right corner of FIG.
) by the embedded connection part M! storage capacity (1
constitute one electrode of o). Further, the third layer polysilicon word line (4A), which is formed via an insulating oxide thin film and constitutes the other electrode of this storage capacitor (lc), is connected to the memory cell (4A) formed at the upper left of Fig. 44. It is also connected to the gate electrode of the switching MOBY (21). That is, the memory capacity it (la) of the memory cell (k) is formed between the second layer polysilicon layer (32a) and the third layer polysilicon word line (red). Insulating oxide II covering the entire surface (word above II! (4a
) A bit line (c) etc. are provided in a direction perpendicular to the bar 4b).

This bit line (cross) is the switching MO8'l' (2
m) source chain acid (21m) and switching gO8
? (2o) is connected to the source region (company 0) via a contact hole.

The plan view of this embodiment in FIG. 4 is drawn using the same dimensional rules as the plan view of the conventional example in FIG. 2, and the memory cell iiO product per 2 bits is substantially the same. Comparing these storage capacity values Oa, we find that if S is the area of the storage capacity [11] in the conventional example shown in Figure 2, then in this embodiment shown in Figure #I4, the area of one storage capacity for adjacent memory cells is 1. .98. The area of the other storage capacity is 2.6S, and in any case, a storage capacity value Cs that is approximately twice that of the conventional one is obtained.
This makes the operation of the memory cell more stable.

As described above in detail and as follows, in the semiconductor memory device of the present invention, the storage capacity of at least two adjacent memory cells is formed by overlapping each other on the same chain on the semiconductor substrate, so that the storage capacity of at least two adjacent memory cells is formed by overlapping each other on the same chain acid on the semiconductor substrate. The storage capacitance value can be approximately doubled or more based on the memory cell area, and the operation of the memory cell can be stabilized. Furthermore, if the storage capacitance value is kept constant, the area of the memory cell per bit is reduced, and the device can be miniaturized while maintaining constant operational stability.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a semiconductor memory device to which the present invention is applied, and FIG. 2 is a plan view showing the configuration of four pits of a memory cell according to the prior art. Fig. 84 is a plan view showing an embodiment of the present invention, Fig. 5 is a sectional view taken along the marma line of Fig. 784, and Fig. 6f! A and FIG. 7 are three-dimensional views corresponding to the Ifr plane in the ■-W fiber and ■-■ wire numbers of FIG. 5, respectively. In the figure, (la), (lb)-- are ki-meiyo-ro, (2a), (ab)-- are MO8T, (c), (
sb)-- are memory cells, (4a) and (4b) rivers are word castles, and (5m) and (5b) are bit lines. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Shin Kuzuno - (1 other person) Figure 1 Figure 2 Figure 3 ['2I Figure 4 Figure 5 Figure 1

Claims (1)

[Claims] (The main electrode of 111i11 is on bit #!, gate iga
is connected to the word line IIl 411 and the insulated gate electric field m
A memory cell consisting of an S transistor, one electrode connected to the eighth main electrode of the insulated gate field effect transistor, and the other electrode connected to the eighth word line, is provided on a semiconductor substrate. 9. A semiconductor memory device characterized in that a plurality of memory cells are arranged, and the storage capacitors of at least two of the memory cells are formed overlapping each other in an area on the semiconductor substrate.