JPS63244769A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To miniaturize a cell by a method wherein a trench is provided in a semiconductor substrate, a transfer transistor section and a bit line contact section are buried in the trench, and a capacitor section is provided to surround the two sections. CONSTITUTION:A capacitor section is constituted of a diffusion layer 33, capacitor insulating film 34, and capacitor electrode 35 and, at its middle, a trench 36 is provided so deep as to reach a semiconductor substrate 31. On the inner surface of the trench 36, a gate insulating film 37 is formed, whereon a transfer transistor gate electrode 38 is built. On the semiconductor substrate 31, at the bottom of the trench 36, a diffusion layer 39 opposite in conductivity type to the semiconductor substrate 31 is formed. In the trench 36 wherein the gate electrode 38 exists, a conducting layer 41 to serve as a bit line is connected to the diffusion layer 39 through the intermediary of an insulating film 40. The conducting layer 41 also extends over the capacitor electrode 35 through the intermediary of an insulating layer 42. With the transfer transistor section and bit line contact section being buried in the trench 36 provided in a semiconductor substrate 31, and with a capacitor section being positioned to surround them, a cell may be miniaturized in dimensions.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) This invention provides at least one MIS (metal
1nsulator 5ea1conductor)
Or M I M (setal 1nsulato
The present invention relates to a semiconductor memory device having a capacitor (R metal ) and a transistor (MI'S), and particularly relates to a DRAM.

(Prior Art) A conventional semiconductor memory device will be explained using FIG. FIG. 5 is a sectional view showing an example of the configuration of a conventional DRAM cell. - Semiconductor substrate 11 on conductive type semiconductor substrate 11
A diffusion layer 12 of opposite conductivity type is formed, and a MIS capacitor is formed by the capacitor insulating film 13 and the capacitor electrode element A thereon. A transfer transistor consisting of source/drain regions 14 and 15 and a gate electrode 16 is formed in series in this capacitor. A bit line 18 is connected to the source/drain electrode 15 via a contact 17.

By the way, in the DRAM having the above-described structure, the capacitor section 19, the transfer transistor 20, and the bit line contact section 21 are arranged horizontally, so in order to make the cell smaller, each part must be made smaller. . However, if the capacitor section 19 etc. are made smaller in this way, the storage capacity will be reduced, the reliability of the transistor will be reduced, and the contact 18's P
Problems such as difficulty in EP arise. Therefore, the fifth
In the configuration shown in the figure, there is a limit to the miniaturization of cells.

(Problems to be Solved by the Invention) As mentioned above, in the conventional semiconductor memory device,
Since the capacitor section, transfer transistor, and bit line contact section are lined up horizontally, attempting to make the cell smaller will result in a decrease in storage capacity, a decrease in transistor reliability, and
There is a limit to the miniaturization of cells because of problems such as difficulty in PEPing contacts.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor memory device in which cells can be made smaller without causing problems such as a decrease in storage capacity, a decrease in reliability of transistors, and difficulty in PEP of contacts.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention provides a groove on a semiconductor substrate, and embeds a transfer transistor section and a bit line contact section in this groove. , by arranging a capacitor section around it, the cell can be miniaturized.

(Function) According to such a configuration, it is possible to miniaturize the cell without reducing the size of each part, thereby causing problems such as a decrease in storage capacity, a decrease in reliability of the transistor, and difficulty in PEP of contacts. This allows the cells to be made smaller.

(Embodiments) Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a sectional view showing the structure of an embodiment of the present invention. In the figure, 31 is a semiconductor substrate, and 32 is an element isolation region. 33 is a diffusion layer formed in the surface region of the semiconductor substrate 31 and having a conductivity type opposite to that of the semiconductor substrate 31. 3
4 is a capacitor insulating film formed on this diffusion layer 33. 35 is a capacitor electrode formed on this capacitor insulating film 34.

In the center of the capacitor section formed by the diffusion layer 33, capacitor insulating film 34, and capacitor electrode 35,
A groove 36 reaching the semiconductor substrate 31 is formed. A gate insulating film 37 is formed on the inner surface of this groove 36 . A gate electrode 38 of a transfer transistor is formed on the gate insulating film 37 inside the trench 36 . Further, a diffusion layer 39 of a conductivity type opposite to that of the semiconductor substrate 31 is formed in the surface region of the semiconductor substrate 31 at the bottom of the semiconductor substrate 36 . Inside the groove 36 in which the gate electrode 38 is formed, a conductor layer 41 forming a bit line is formed so as to be connected to the diffusion layer 39 via an insulating film 40 . This conductor layer 41 also extends over the capacitor electrode 35 with an insulating film 42 interposed therebetween.

Note that the bit line made of the conductive pair layer 41 is as shown in the figure.
Although not shown, the word line extends in the horizontal direction of the figure.
A gate electrode 38 is present extending perpendicularly to the plane of the paper.

It has a so-called cross-point cell structure in which a cell for one bit is formed at the intersection of a word line and a bit line. The information charge is transferred to the conductor layer 41. Diffusion layer 42. The signal is transmitted to the diffusion layer 33 through the channel region 43 of the transfer transistor.

As described above, in this embodiment, the transfer transistor section and the bit line contact section are buried in the trench 36 provided on the semiconductor substrate 31, and the capacitor section is arranged around the trench, thereby achieving a fine cell structure. It was designed to make the

According to such a configuration, the cell can be made smaller without reducing the size of the capacitor section, etc., thereby causing problems such as a decrease in storage capacity, a decrease in reliability of the transistor, and difficulty in PEP of contacts. This allows the cells to be made smaller.

Also, if a hole is made in the capacitor part, the gate electrode 38,
Bit line contact portions and the like can be formed in self-alignment with the openings.

Furthermore, even if there is misalignment between the opening and the isolation region,
Another feature is that the capacitance of the capacitor does not change.

FIG. 2 is a sectional view showing the structure of another embodiment of the invention. In the previous embodiment, a planar capacitor was used as the capacitor, but in this embodiment, a stacked capacitor is used. In the figure,
Reference numerals 51 and 52 designate capacitor electrodes of this stacked capacitor, which are made of polysilicon, for example. 53 is a capacitor insulating film. Note that in FIG. 2, parts that perform the same functions as those in FIG. 1 are given the same reference numerals.

FIG. 3 is a sectional view showing the configuration of still another embodiment of the present invention. This embodiment also uses a stacked type capacitor, but the effective area of the capacitor is expanded by adding pleats to the capacitor electrode. In the figure, 61.6
A capacitor electrode 2 of this stacked capacitor is made of polysilicon, for example. 63 is a capacitor insulating film. Note that in FIG. 3, parts that perform the same functions as those in FIG. 1 are given the same reference numerals.

The stacked capacitor shown in FIG.
Although it is described in No. 022, here, for reference,
An example of the manufacturing method will be briefly explained with reference to FIG.

First, as shown in FIG. 4(a), impurity ions are implanted into the surface region of the semiconductor substrate 71 to form an impurity diffusion layer 33. After this, a silicon oxide film 7 is formed on the semiconductor substrate 71.
2 is formed, and further an element isolation region 73 is formed by, for example, the Locos method.

Then, a silicon nitride film 74 is formed on the silicon oxide film 72 and the element isolation region 73.

Next, as shown in FIG. 4(b), the silicon nitride film 74 and the silicon oxide film 72 are selectively removed by, for example, photoetching.

Next, as shown in FIG. 4C, the silicon oxide film 72 is selectively removed by, for example, isotropic etching.

Next, as shown in FIG. 4(d), polysilicon 75 containing phosphorus is deposited on the inner surface of the hollow and the upper surface of silicon nitride film 74. Next, as shown in FIG.

Next, as shown in FIG. 4(e), the gate electrode 61 is formed by removing the partial polysilicon 75 other than the lower side of the silicon nitride film 74 by, for example, the RIE method.

Next, as shown in FIG. 2(f), the silicon nitride film 74 is
After peeling off, the silicon oxide film 72 is selectively removed using, for example, NH4F solution. Thereafter, a capacitor insulating film 63 is formed on the surface of the capacitor electrode 61 by, for example, thermal oxidation treatment.

Finally, as shown in FIG. 2(g), the capacitor electrode 6
A capacitor electrode 62 is formed by depositing polysilicon containing phosphorus so as to fill the inside of the capacitor 1, and then buttering the polysilicon.

Although several embodiments of this invention have been described above, this invention is not limited to these embodiments, and it goes without saying that various other modifications can be made without departing from the gist of the invention. It is.

[Effects of the Invention] As described above, according to the present invention, a cell can be made smaller without causing problems such as a decrease in storage capacity, a decrease in transistor reliability, and difficulty in PEP of contacts.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the configuration of an embodiment of the present invention, and FIG.
The figure is a sectional view showing the structure of another embodiment of the invention, FIG. 3 is a sectional view showing the structure of still another embodiment of the invention, and FIG. 4 is an example of a method for manufacturing the capacitor shown in FIG. 3. FIG. 1 is a sectional view showing the structure of a conventional semiconductor memory device. 31... Semiconductor substrate, 32... Element isolation region, 33
39... Diffusion layer, 34, 53.63... Capacitor insulating film, 35.51, 52, 61.62... Capacitor electrode, 36... Groove, 37... Gate insulating film, 3
8... Gate electrode, 40.42... Insulating film, 43.
...Channel area. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Figure 2 Figure 3 Figure 5 Figure 4

Claims (2)

[Claims] (1) In a semiconductor memory device having at least one MIS or MIM capacitor and an MIS transistor, a groove that penetrates the capacitor portion and reaches the semiconductor substrate, a gate insulating film formed on the inner surface of the groove, and the groove a gate electrode formed on the gate insulating film; an impurity region of a conductivity type opposite to that of the semiconductor substrate formed at the bottom of the trench; and a region in contact with the impurity region and extending inside the trench. What is claimed is: 1. A semiconductor memory device comprising: a conductor layer; (2) The semiconductor memory device according to claim 1, wherein the capacitor electrode of the MIM capacitor is made of polysilicon.