JPS58174A - Monolithic hybrid thyristor - Google Patents
Monolithic hybrid thyristorInfo
- Publication number
- JPS58174A JPS58174A JP9938981A JP9938981A JPS58174A JP S58174 A JPS58174 A JP S58174A JP 9938981 A JP9938981 A JP 9938981A JP 9938981 A JP9938981 A JP 9938981A JP S58174 A JPS58174 A JP S58174A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- thyristor
- conductivity type
- type
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011521 glass Substances 0.000 claims abstract description 10
- 239000004065 semiconductor Substances 0.000 claims abstract description 7
- 238000002161 passivation Methods 0.000 claims abstract description 6
- 239000002131 composite material Substances 0.000 claims description 14
- 238000000926 separation method Methods 0.000 claims description 5
- 238000002955 isolation Methods 0.000 claims description 3
- 239000000758 substrate Substances 0.000 abstract description 9
- 238000000034 method Methods 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 2
- 241000218645 Cedrus Species 0.000 description 1
- 235000010575 Pueraria lobata Nutrition 0.000 description 1
- 241000219781 Pueraria montana var. lobata Species 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 210000000554 iris Anatomy 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000011435 rock Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/7428—Thyristor-type devices, e.g. having four-zone regenerative action having an amplifying gate structure, e.g. cascade (Darlington) configuration
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は一つの半導体基板に２個のサイリスタを形に
作られたものを外部接続することによって構成されてい
た。しかし、これでは実装容積−大きくなるので、上記
２つのサイリスタを個々のチップの形で形成した上で、
これらを１個のノ（ツケージに組み込んで複合サイリス
クとすることによって装置のコンノくクト化が計られて
いる。DETAILED DESCRIPTION OF THE INVENTION The present invention was constructed by externally connecting two shaped thyristors to one semiconductor substrate. However, this requires a large mounting volume, so the two thyristors mentioned above are formed in the form of individual chips, and then
By incorporating these into a single cage to create a composite system, the system can be made more compact.
纂１図はこの従来の複合サイ１ノスタの構成を示す断面
図で、（１）は主サイリスタ、（２）は補助サイ１ノス
タであり、主サイリスタ（１）はｐ形エミッタ（ｐ、、
）層＋ｌＩｌ 、 ｎ形ベース（ｎＢ□）層ａｉ、ｐ形
ペースペースＱ）層◇樽およびｎ杉エミッタ（ｎ ）
層ｏ彎からなり、ｐ、１層（１１）には１
１ｉ＃１ｍＪａｌ 、 ｎ Ｉｍｊ１４）には陰極０’
ｌ ｒ ９３１１層（１濁にはゲート極１
σ力が形成されそれぞれ陽極端子Ａ、陰極端子Ｋｌ、ゲ
ート端子Ｇ１が引出されている。ａ８）ｉｔ周知のガラ
スパッシベーション膜である。補助サイリスタ（２）も
全く同様の構成で、ｐ１□１層’ｌＪ ｒ ｎ Ｂ２層
（イ）、ｐ、２層＠およびｎｍｚ Ｊ−鱒からなり、ｐ
、２層（ロ）には陽極＠ｌ ｎＮ２層■には陰極に）＋
ｐＢｚ層ｎＫはゲート極（ロ）が形成され、それぞれ
陽極端子（主サイリスタと共通） Ａ＋陰極端子に２．
ゲート電極Ｇ２が引出されている。＠はガラスパッシベ
ーション膜である。そして、この主サイリスタ（１）と
補助サイリスタ（２）とは図に一点鎖線で示すように一
つのパッケージに収容されている。Figure 1 is a cross-sectional view showing the configuration of this conventional composite thyristor, in which (1) is the main thyristor, (2) is the auxiliary thyristor, and the main thyristor (1) is a p-type emitter (p, ,
) layer + lIl, n-type base (nB□) layer ai, p-type pace space Q) layer ◇ barrel and n cedar emitter (n)
It consists of a layer o curve, p, 1 layer (11) has 1 1i#1mJal, n Imj14) has a cathode 0'
l r 9311 layer (a gate electrode 1 σ force is formed in the first layer, and an anode terminal A, a cathode terminal Kl, and a gate terminal G1 are drawn out, respectively.a8) It is a well-known glass passivation film. The auxiliary thyristor (2) has exactly the same structure, consisting of p1□1 layer'lJ r n B2 layer (a), p, 2 layer @ and nmz J-Trout, p
, the second layer (b) has an anode @l nN2 layer ■ has a cathode) +
A gate electrode (B) is formed in the pBz layer nK, and 2.
Gate electrode G2 is drawn out. @ is a glass passivation film. The main thyristor (1) and the auxiliary thyristor (2) are housed in one package as shown by the dashed line in the figure.
しかし、近来さらにストロボ装置の小形軽量化、史ＶＣ
は低価格化が要求され、特に比較的光量の少ないカメラ
組み込みストロボ装置用として小形複合サイリスタが要
望されている。However, in recent years, strobe devices have become smaller and lighter.
There is a demand for lower prices, and there is a particular demand for small composite thyristors for use in camera-embedded strobe devices that emit relatively little light.
この発（７）は以上のような点に鑑みてなされたもので
、一枚の半導体基板内に２個のサイリスタを形成するこ
とによって小形化した複合サイリスタを提供することを
目的としている。This proposal (7) was made in view of the above points, and aims to provide a compact composite thyristor by forming two thyristors in one semiconductor substrate.
第２図はこの発明の一実施例を示す断面図で、従来例と
同一または相当部分は同一符号で示した。FIG. 2 is a sectional view showing an embodiment of the present invention, in which the same or corresponding parts as in the conventional example are designated by the same reference numerals.
この実施例の複合サイリスタ（３）は陽極（７）を共通
して主サイリスタと補助サイリスタとを一枚の半導体基
板に形成したもので、主サイリスタは用層Ｈｒ ｎ、、
層（嗜。The composite thyristor (3) of this embodiment has a main thyristor and an auxiliary thyristor formed on a single semiconductor substrate, with an anode (7) in common, and the main thyristor has a common anode (7).
Layer (preference)
ｐ 層０３）およびｎ１１層（１４１の４層構造からな
り、ｎ ｍ １層ＢＢ！
表面に形成された陰極（１〜からは陰極端子に１が、Ｔ
’＋ｆａ＋＋３）表面に形成されたゲート極０ηからは
ゲート端子由が引出されている。補助サイリスタはｐｌ
□層Ｑυ、ｎ、２層（イ）。p layer 03) and n11 layer (consisting of 4-layer structure of 141, nm 1 layer BB! cathode formed on the surface (from 1 to 1 is the cathode terminal, T
'+fa++3) A gate terminal is drawn out from the gate electrode 0η formed on the surface. Auxiliary thyristor is pl
□Layer Qυ, n, 2nd layer (a).
ｐＢ２ＭＨ！３およびｎ ｍ ２層（ハ）の４層構造か
らなり、ｎ、２層（ハ）表面に形成された陰極（ホ）か
らは陰極端子に２が、ｐ、２層（ハ）表面に形成された
ゲート極（財）からはゲート端子Ｇ２が引出されている
。各ｐｎ接合の露出端縁はガラス膜（至）および−によ
ってパッシベーションされており、ｎ ｓｓ層（１匂と
ｎ ｍ ｚ層四との間はｐ形分離拡散層（３υとガラス
膜■とによつ、て電気的に分離されている。このモノリ
シック複合サイリスタ（３）も図に一点鎖線で示すよう
にパッケージに収容され各端子Ａ ｅ Ｋ１ ＃に！
ｅＧｌ 、Ｇ２が引出されている。pB2MH! It consists of a four-layer structure of 3 and nm 2 layers (c), from the cathode (e) formed on the surface of the n, 2 layer (c), 2 is formed on the surface of the p, 2 layer (c) to the cathode terminal. A gate terminal G2 is drawn out from the gate electrode. The exposed edge of each pn junction is passivated by a glass film (1) and -, and between the n ss layer (1) and the nm z layer 4 is a p-type separation diffusion layer (3υ and the glass film This monolithic composite thyristor (3) is also housed in a package as shown by the dashed line in the figure, and connected to each terminal A e K1 #!
eGl and G2 are drawn out.
次に、この実施例の製造方法を概説する。１１１３図（
イ）〜（ホ）はその製造工程の主要段階における状態を
示す断面図で、まず、第３図（イ）Ｋ示すようにｎ形シ
リコン基板曽の第１の主面からその一部にホウ素を選択
拡散してｐ形分離拡散層６乃を形成する。Next, the manufacturing method of this example will be outlined. Figure 1113 (
A) to (E) are cross-sectional views showing the state at the main stages of the manufacturing process. First, as shown in FIG. is selectively diffused to form a p-type isolation diffusion layer 6.
次に１１３図（ロ）に示すように、やはシ周知の拡散方
法で第１の主面部全面にｐ形層（３１ａ）を、第２の主
面部全面にｐ形層（至）を、更にそのｐ形層（至）の表
面部の一部にｎ形層−を形成し、ｐ−ｎ−ｐ−ｎ４層構
造とする。次に、菖３図（ハ）に示すように、ｎ形層（
ロ）の略中央部にその表面からｎ形層■、その下のｐ形
層（至）、更にその下のｎ形層（２）を経てｐ形分離拡
散層（ロ）に達するメサ溝（イ）を形成し、ｎ形層■。Next, as shown in FIG. 113 (b), by a well-known diffusion method, a p-type layer (31a) is formed on the entire first main surface, a p-type layer (31a) is formed on the entire second main surface, Further, an n-type layer is formed on a part of the surface of the p-type layer (toward) to form a p-n-p-n four-layer structure. Next, as shown in Figure 3 (C), the n-type layer (
A mesa groove (b) extending from the surface to the n-type layer (2), the p-type layer (2) below it, the n-type layer (2) below it, and the p-type isolation diffusion layer (b) approximately in the center of the n-type layer (b). A) forms an n-type layer ■.
ｐ形層（至）およびｎ形層（至）をそれぞれ２つの部分
に分割する。続いて、ｊ［３図に）に示すように、メサ
溝（転）から左右にそれぞれ所要距離離れた位置に、両
主面のｐ形層（２）および磐の互いに対応する表面部位
からｎ形層に）の一部が残る程度に各ｐｎ接合を貫いて
メサ溝（４１）を形成する。そして、第３図（ホ）に示
すように、メサ１ｌｌ−および（４１）にそれぞれガラ
スパッシベーション膜■および（至）を施し、ダイシン
グによってメサ溝（４１）の図示Ｘ−Ｘ臘部で分割する
と、ｐ形層（３１ａ）が２つの２Ｍ０層（ＩＩ）および
ｐ、２層（２）に分かれ、ｎ形層（２）がｎ ｍ Ｉ層
ａ四およびｎ ｍ ２層（イ）に分かれ、ｐ形層−がｐ
、１層α場およびＩ’１２層＠に分かれ、かつｎ形層−
がｎ□層幀およびｎｍｚ層（財）に分かれ、それぞれ主
サイリスタ（１）および補助サイリスタ（２）を構成す
るようになる。これに各電極および端子をとシつけ、パ
ッケージングを施すと第２図に示したこの実施例の複合
モリシックサイリスタが得られる。The p-type layer (to) and the n-type layer (to) are each divided into two parts. Next, as shown in Figure 3, p-type layers (2) on both main surfaces and n-type layers from the corresponding surface parts of the rock are placed at positions a required distance away from the mesa groove (turn) to the left and right, respectively. A mesa groove (41) is formed through each pn junction to such an extent that a portion of the (forming layer) remains. Then, as shown in FIG. 3 (E), glass passivation films (1) and (2) are applied to mesa 1ll- and (41), respectively, and the mesa groove (41) is divided by dicing at the X-X end of the mesa groove (41). , the p-type layer (31a) is divided into two 2M0 layers (II) and the p,2 layer (2), and the n-type layer (2) is divided into an n m I layer a4 and an nm two layer (a), The p-type layer is p
, divided into 1 layer α field and I'12 layer @, and n-type layer -
is divided into an n□ layer and an nmz layer, which constitute a main thyristor (1) and an auxiliary thyristor (2), respectively. By attaching each electrode and terminal to this and performing packaging, the composite molythic thyristor of this embodiment shown in FIG. 2 is obtained.
以上実施例では、ｐゲートサイリスタを陽極共通にした
形で構成したが、各部の半導体伝導形を逆にすることに
よって、ｎゲートサイリスタの陰極共通の形で構成する
こともできる。また、メサ婢ノパツシペーションには、
ガラス以外ニフェス。In the embodiments described above, the p-gate thyristors are configured with a common anode, but by reversing the semiconductor conduction type of each part, it is also possible to configure the n-gate thyristor with a common cathode. In addition, Mesa Unopatsipation includes:
Nifes other than glass.
酸化シリコン、窒化シリコンなどを用いることもでき、
各種代替品がめる０更に、バツケージングは複合サイリ
スタのみならず周辺回路部品も一緒にパッケージングす
れば、応用装置の小形化が促進される。Silicon oxide, silicon nitride, etc. can also be used.
Furthermore, by packaging not only the composite thyristor but also peripheral circuit components together, the miniaturization of the applied device will be facilitated.
勿論、この複合サイリスタはストロボ装置用に限らず広
く他の用途にも利用できる。Of course, this composite thyristor can be used not only for strobe devices but also for a wide range of other uses.
以上説明したように、この発明では主サイリスタおよび
補助サイリスタを１枚の半導体基板内に形成したので複
合サイリスタを小形化することができ、これを用いた応
用回路装置の小形、軽量。As explained above, in the present invention, since the main thyristor and the auxiliary thyristor are formed in one semiconductor substrate, the composite thyristor can be downsized, and the applied circuit device using the same can be made smaller and lighter.
低価格化が可能で、信頼性の向上も期待できる。It is possible to lower the price and expect improved reliability.
第１図は従来の複合サイリスタの構成を示す断面図、第
２図はこの発明の一実施例の構成を示す断面図、＃！３
図（イ）〜（ホ）はこの実施例の製造工程の生簀段階に
おける状況を示す断面図である。
図において、（”）は第１サイリスタのｐｍ層（第１伝
導形エミツタ層）、０１は第１サイリスタのｎ。
層（第２伝導形ペース層の第１の部分）、Ｑ場は第１サ
イリスクのｐｍ層（第１伝導形ベース層の第１の部分）
、０４は第１サイリスタのｎ１層（第２伝導形ニオツタ
層の篤１の部分）、（２）は菖２サイリスタの９１層（
第１伝導形エミツタ）、（２）は第２サイリスタのｎ１
層（第２伝導形ベース層の第２の部分）、輪は第２サイ
リスタの９１層（第１伝導形ベース層の１１２の部分）
、（２）は第２サイリスタのｎ１層（第２伝導形エミツ
タ層の館２の部分）、（ロ）は分離領域、（３１ａ）砿
、（至）および（至）はそれぞれ両サイリスタ分離前の
ｐ１層ｐｎ１層、ｐｍ層およびｎ１層、褥はメサ溝、（
至）はガラスパッシベーション膜である。
なお、図中同一符号は同一または相当部分を示す０
代理人 葛針傷−（外１名）
第１１
第２図
第゛３１′２１FIG. 1 is a sectional view showing the structure of a conventional composite thyristor, and FIG. 2 is a sectional view showing the structure of an embodiment of the present invention. 3
Figures (A) to (E) are cross-sectional views showing the situation at the cage stage of the manufacturing process of this example. In the figure, ('') is the pm layer (first conduction type emitter layer) of the first thyristor, 01 is the n layer (first part of the second conduction type paste layer) of the first thyristor, and the Q field is the first conduction type emitter layer. Cyrisk PM layer (first part of first conductivity type base layer)
, 04 is the n1 layer of the first thyristor (the part 1 of the second conductivity type Niotsu layer), (2) is the 91 layer of the irises 2 thyristor (
(1st conduction type emitter), (2) is n1 of the second thyristor
layer (the second part of the second conductivity type base layer), the ring is the 91st layer of the second thyristor (the 112th part of the first conductivity type base layer)
, (2) is the n1 layer of the second thyristor (part 2 of the second conductive emitter layer), (b) is the separation area, (31a) is the area before separation of both thyristors, (to) and (to) are respectively p1 layer, pn1 layer, pm layer and n1 layer, the fold is a mesa groove, (
(to) is a glass passivation film. In addition, the same reference numerals in the figures indicate the same or equivalent parts. 0 Agent Kudzu needle wound - (1 other person) 11 Figure 2 ゛31'21
Claims (3)
、第１伝導形ペース層および第２伝導形エミツタ層が順
次重ねて形成された４層半導体構造を有し、上記第１伝
導形エミツタ層の一部から上記第２伝導形ベース層内に
突出する第１伝導形の分離領域、および上記第２伝導形
エミツタ層の表面の上記分離領域に対応する部分から上
記第２伝導形エミツタ層、上記第１伝導形ペース層およ
び上記第２伝導形ベース層を貫通して上記分離領域に達
するメサ溝が形成され、上記第１伝導形エミツタ層を共
有し上記分離領域および上記メサ溝によって電気的に分
離された上記第２伝導形ベース層、上記第１伝導形ペー
ス層および第２伝導形エミツタ層の各組１の部分からな
る第１のサイリスタと各組２の部分からなる第２のサイ
リスタとが構成されたことを％徴とするモノリシック複
合サイリスタ。(1) It has a four-layer semiconductor structure in which a first conductivity type emitter layer, a second conductivity type base layer, a first conductivity type paste layer, and a second conductivity type emitter layer are stacked in sequence, and the first conductivity type A separation region of the first conductivity type that protrudes into the second conductivity type base layer from a part of the emitter layer, and a portion of the surface of the second conductivity type emitter layer corresponding to the separation region that extends into the second conductivity type emitter layer. a mesa groove is formed passing through the layer, the first conductivity type paste layer and the second conductivity type base layer and reaching the isolation region; A first thyristor comprising portions of each set 1 of the second conductivity type base layer, the first conduction type space layer and the second conduction type emitter layer, which are electrically separated; and a second thyristor comprising portions of each set 2. A monolithic composite thyristor consisting of a thyristor and a thyristor.
施されたことを特徴とする特許請求の範囲第１項１己載
のモノリシック複合サイリスタ○(2) A monolithic composite thyristor according to claim 1, paragraph 1, characterized in that the inner surface of the mesa groove is coated with 75 layers of tsusivation film.
を特徴とする特許請求の範囲第２項舊己載のモノリシッ
ク複合サイリスク。(3) A monolithic composite silice according to claim 2, characterized in that a glass film is used as the passivation film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9938981A JPS58174A (en) | 1981-06-24 | 1981-06-24 | Monolithic hybrid thyristor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9938981A JPS58174A (en) | 1981-06-24 | 1981-06-24 | Monolithic hybrid thyristor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58174A true JPS58174A (en) | 1983-01-05 |
Family
ID=14246142
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9938981A Pending JPS58174A (en) | 1981-06-24 | 1981-06-24 | Monolithic hybrid thyristor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58174A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5387805A (en) * | 1994-01-05 | 1995-02-07 | Metzler; Richard A. | Field controlled thyristor |
| JP2002538627A (en) * | 1999-02-26 | 2002-11-12 | ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング | Multilayer diode and method for manufacturing the multilayer diode |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50783A (en) * | 1973-05-02 | 1975-01-07 | ||
| JPS5034179A (en) * | 1973-07-27 | 1975-04-02 | ||
| JPS5127985A (en) * | 1974-09-03 | 1976-03-09 | Asahi Optical Co Ltd | Roshutsukeikairo oyobi roshutsukei |
-
1981
- 1981-06-24 JP JP9938981A patent/JPS58174A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50783A (en) * | 1973-05-02 | 1975-01-07 | ||
| JPS5034179A (en) * | 1973-07-27 | 1975-04-02 | ||
| JPS5127985A (en) * | 1974-09-03 | 1976-03-09 | Asahi Optical Co Ltd | Roshutsukeikairo oyobi roshutsukei |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5387805A (en) * | 1994-01-05 | 1995-02-07 | Metzler; Richard A. | Field controlled thyristor |
| JP2002538627A (en) * | 1999-02-26 | 2002-11-12 | ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング | Multilayer diode and method for manufacturing the multilayer diode |
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