JPS58172706A - Programmable logical controller - Google Patents

Abstract

PURPOSE:To perform coding simply without altering a relay circuit, logical expression, etc., by storing an operation output while shifting up or down a shift register by one bit in case of an input instruction or specific logical operation instruction. CONSTITUTION:According to the address of the input instruction or logical operation instruction, an input address selecting circuit 20 selects an input point and the shift register 50 consists of one-bit registers. In case of the input instruction, a logical arithmetic circuit 30 supplies the input signal selected by the circuit 20 as it is or its inverted signal to the register 50 for a one-bit shift. Only in case of the specific operation instruction, the input point signal selected by the circuit 20 and the data of the register 50 are ANDed or ORed and the result is supplied to the register 50, which is then shifted by one bit contrarily to the input instruction.

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a programmable logic controller capable of coding using the reverse Borland method.

[Technical background of the invention and one point in between]

Conventionally, when a given formula or circuit diagram is am, when a sequence program is created by conducting an rNIL meeting based on the formula or circuit, the following problems arise.

■A command is required to store the state of performance in memory, and since it is necessary to insert commands into the program as necessary, the programming line must be constantly conscious of the memory, which requires a large amount of memory. This has the disadvantage that the 11th speed is slow.

Since it is necessary to generate and insert an instruction to be stored in the memory at the stage of converting it into the zero-order machine language, or to carry out an equivalent internal procedure, the processing speed of the memory is inferior.

(2) Since temporary storage processing is performed in the total IN1 using the software intagritator, the calculation speed of instructions is slowed down, and there is 18JI-, which affects the overall processing speed.

[Purpose of the Invention] 杢'8 Ming was made in view of the above ml Sanekiyo, so a given formula l/m can be used even if the relay circuit etc. It is an object of the present invention to provide a programmable logic controller that can be simply coded without having to carry out the following steps, and without requiring a continuation of the process of temporarily registering fIa in the process.

[Month of invention]

The present invention is equipped with an n-bit shift register, and in the case of an input Kinto or tri divine rhinoceros computation instruction, the /shift register is shifted between upper or upper registers by 1 bit and 7 notes to store an output. This is a programmable logic controller that couples the above objectives.

[Fruits and Feeds of the Invention] The first problem is to draw a diagram that minimizes the overall I4 configuration of the programmable logic controller according to the present invention.

Note that the table below is a simple example of the structure of an instruction manual necessary to explain the first problem, the controller.

In FIG. 1, 10 is an output address selection circuit that selects the output point specified by the address field of the output instruction 0LJT, and 20 is an input instruction IN% logic rewriting instruction AND or OR.
The input address selection circuit 30 selects the input point t specified in the address section of
AN of two signals 4!1131#32 signal in case of R
D or OR is taken, and the signal of the unity is output from signal #33, and the Ig Q of cicada 31 to be trusted when the input is N is
t: This is a logic circuit that waits for the signal t1 to output the signal 4I33 as it is or inverted. 40 is human power 6
In the case of the 6th order IN, a 77t pulse is sent to shift the 7th register 50t-1 bits to the right before the eastward of the combination, and it is used for commands such as 6th order AND or OR. 2 and the address field is correct, it points to a specific address such as 0. - When the aVC instruction is executed, shift register 6
This is a shift pulse generation circuit that generates a pulse that shifts one bit to the left with respect to 0FC. The shift register 50 has n
The most significant bit is set in register 5) ((1
, and register SRJ in F rlt=.

SR2,...SRn and 1 pin) kt is numbered 1. You can choose n4d type 7, but usually up to 1 is sufficient. This register 5ROf, after receiving the output of Isakana Yuhigashi of Gori Gihana 1pJM30, Ichiri @ Shin11ro 30's 1-
1! ! It becomes one input of Sadatoge, and in the case of J off instruction OUT, its condition is the address part of small point instruction OUT: m J,! Now, output address selection time! %JO
From kC, ^(J( is output to the point where
The input of the 0 signal line 31 is set to 8R1, and in the conventional case, a switch is used to switch the input point selected by the input address selection circuit 20 to the input of the signal @@31 of the Jiauripo circuit 30. be. The situation in the figure is smaller than that of Toshiya.

Next, the operation of the programmable logic controller configured as described above will be explained with reference to the second and third problems. In addition, the relay circuit as the 2nd ward V Mami-〇Aya connection, the 3rd bad is the upper 8 self IJ mA 11
This shows the behavior of the 77 register coded based on this and the ai5% execution by Nobutoshi Hono, and 1jANQ+ in the figure is a taste of OR. First, as an example, consider the circuit diagram of 1g2 diagram and the formula t, where o = a (
(b−c)+d(e+f)) will be described. G is an output relay, and a-f are input contacts.

Now, in order to demonstrate the given example, according to the circuit diagram or formula 11, (119th, IN-a contacts aC/). This contact aO state is the input address selection circuit 20 - switch 60 - signal @31 - prison door circuit 30-1 No. a3
3-register BROO is set in register SRO through the register BROO path, thereby shifting registers 5RO-8Rn one bit to the right.

121 Next, a branch point in a circuit, - () in a mathematical formula.

There are (). At this time, use the input command IN again.
11e Insert the manual contacts in the same way as in 1. As a result, the register SRO is in a low state, and the register S
The state of M@a is set in RI.

(, 3) Since the human power contact point C is an AND with the human power contact point, it is set as A N D -c.
The input address series 1] becomes one input of the threshold buried chain nose circuit 30 through the route of 1M20-switch 60-false code-31, and the signal from the register SRO @31 becomes one input of the circuit 30. is input as ``d''.The LC button which is ANDed by this -FM uraitch circuit 30 is transferred to the register BRO via false code 33.At this time, the /st register 50#i shift is inputted. Since this is not done, register BRO has manual contacts b-c and register SR.
The input contact a state of J& is set.

(41) Next, read the state of the input contact d of the previously branched part. Since this is a manual command IN, the shift register 50 is shifted one pit to the right, and the register 8RIJ has the state of the input contact d.
Contact 1)-C is on Registor SRI, and point a is on resistor 8R2! The order is d1.

(3) Next IC, execute instruction and address for branching
-e. At this time, resistor E3HO has contacts θ,
Contact d is connected to register 8RJ, contact b is connected to register BR2.
-c, the state of the register 5R3VC/d contact a is set to 1;

(6) Next, OR the e and f. In this case, 131
(!: θ+f1 in register 5FLO for IIJ)
Since the other registers 8R1, . . . are not shifted, they remain in the same state as the previous one. .

(7) Next, the other ends of contacts e and f are connected to one end of P. In this case, the same process as that for ilf branched previously is performed. In other words, at this stage, d and (a0f) are ANDed, but the address field at this time is specified as d), which specifies the 7-foot register 5o./) In Fig. 3, register 8RJ I have given the second name to this. This address can be distinguished by a value that does not exist at the input/output point, a value defined as θ, or an extension of the instruction.
-).

According to the Ichirichodon command, when the address part is special electric, the switch 60 is switched to the right, and the register BRO and register 8RJ become the manual power of -rihera nose turn M3θ. In other words, the register 5ROV is θ+f1, and d is set in the register SR7, so the -crossing nose circuit 3o is set to A.
The actual value of ND-8hx is determined by d(.+f)t- from LC and outputted from the signal line 33. And this signal 113
The output 1 of J is set in register SRO, but the output 1 of register J is set to register SRO, and the output of register 8ROtlCdd (e+, f
), b-c is set in register SRJ, and pin is set in register 8R2.

(The parts that branched out before Kyoji are b-c and d (ear)
Return the OR of The instruction and address are 0R-8RJ, and is passed through the same path as in (7), and after that, a is set in register 5Rottcr (b-c) + d (ear) and register 8RJ.

υ) Next, take the AND between the above connections and contact a. AN
D-8R1 connects register SRO and V-) I'BR.
1 and t:I are ANDed by the logic circuit 30,
The value of the result is set in register SRO. Therefore, the register BRO is in a state where it should output the necessary reduction result.

At 0.am, the state of the register BRO is set to 0 point by the selection of the output address selection path 10 from the instruction and address 0UT-GK.

By the way, if the above expression is written in Borland notation, expressions enclosed in polygon parentheses can also be expressed without parentheses. For example, in FIG. 2, it is expressed as G=sa+*bc@d+of. However, . is AND1+ is OR. In Borland notation, the operator is written before the operator, but the 弦子 is written after the operator.
In reverse Borland notation, G=abc *def+e
+e becomes. The purpose of this book is to demonstrate reverse Borland notation.

It should be noted that, in order to congratulate the up-and-comers on their coding, the most common way to input a program is to enter a relay circuit or one-piece system using a CRT or keyboard, but in this case, the VC is Machine dI K & 1!
The assemblers and compilers that do this will also be converted to 4LA. If you do this, you won't have to issue commands to stop the game from happening in the middle of a situation where you're in a dilemma. In addition, the present invention
It can be implemented in tmkK form as long as it does not overlook the purpose of iN.

[Self-spread young fruit J, -""' Above, i+a: L- According to the present invention, a given relay circuit diagram or one-piece type can be drawn down with a fixed hand 1m without deforming it. This allows coding to be performed without the need for special knowledge or ingenuity in grogging. In addition, there is no need to temporarily store the part in branch or parentheses (@) in the memory, etc., and there is no need for this procedure, which also improves processing speed. Programmable logic is a programmable logic system that has the effect that the correspondence with the circuits, formulas, etc. that will be added or modified in each volume can be understood by focusing only on that part, and there is no risk of affecting other parts. controller can be provided.

[Brief explanation of drawings]

The first section is a configuration diagram showing one implementation column of the programmable logic controller according to the present invention, FIG. 2 is a sequence circuit diagram to explain it as an aggregate column, and FIG. 3 is a behavioral relationship between coding and shift registers. FIG. 10... Output address selection circuit, 20... Input address selection circuit, 30..., 1 Cooking l'Iji numbing circuit,
40...Shift pulse teacher circuit, 50.../Futre/
Star, 6e... changeover switch. Applicant's agent Patent attorney Takeshi Suzue Hikosai 1wA Blade 2v! A 3rd figure

Claims (1)

[Claims] The input instruction M9 is an input address selection circuit that selects an input point according to the address of a logic operation instruction, and an n (nU-alignment) bit shift consisting of a bit-by-bit register. In the case of a ^tl input command, the input point signal selected by the 111th manual address selection circuit is supplied as it is or its inverted signal is supplied to the 7-foot register to shift it by 1 bit, and also a specific nil register process is performed. Only in the case of the Jll instruction, the input address selection circuit selects the input address signal and n
AND or O with the data in the il s pi shift register.
A programmable logic controller which takes R and supplies it to the shift register to shift the shift register by 1 bit, contrary to the case of the input command.