JP3193830B2 - Arithmetic circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processor (hereinafter referred to as D) for numerical operation processing and signal processing.
(Hereinafter abbreviated as SP).

[0002]

2. Description of the Related Art The principle of calculating a path metric and selecting a path will be described with reference to FIG. FIG.
It is a trellis diagram showing the state transition from time t of the coding rate 1/2 and the constraint length 4 to time t + 1. In general, the number of states for a constraint length k is 2 ^k−1 . In the case of FIG. 7, since k = 4, the number of states is 2 ^4-1 = 2 ³ = 8. In FIG. 7, S0 (t),..., S7 (t) indicate the state at time t, and S0 (t + 1),.
Indicates a state at time t + 1. Here, state S0
, S7 (t) are represented by P0 (t),..., P7 (t), and the branch metric obtained from the received signal at time t + 1 is represented by Bm (t +
1) (m is an arbitrary integer). For example, state S0 (t +
The path metric P0 (t + 1) in 1) is given by the following equation (1) or (2): P0 (t + 1) = P0 (t) + B0 (t + 1) (1) P0 (t + 1) = P1 (t) − B0 (t + 1) (2) Two P0 (t + 1) obtained by calculating
Among them, those with high likelihood.

[0003] Here, referring to FIG.
1 will be described in detail.
First, the arithmetic circuit calculates P0 (t), P1 (t) and B0 (t
+1), and the equations (1) and (2) are calculated to obtain two P0 (t + 1). Then, a value of P0 (t + 1) having a high likelihood is selected from the two obtained P0 (t + 1), and bit data “0” or “1” of which one is selected is stored in the register. Here, the state S0 (t
+1),..., S7 (t + 1) are denoted by b0,. Next, the arithmetic circuit calculates P0 (t),
The values of P1 (t) and B0 (t + 1) are held as they are, and the equation P4 (t + 1) = P0 (t) -B0 (t + 1) (3) P4 (t + 1) = P1 (t) + B0 (t + 1) ( 4) is calculated to obtain two P4 (t + 1). Then, of the two obtained P4 (t + 1), P4 having a high likelihood
The value of (t + 1) is selected, and the selected identification code “0” or “1” is stored in the register. As described above, if the path metric of the state S4 (t + 1) is calculated immediately after calculating the path metric of the state S0 (t + 1), the same data P0 (t) used when calculating the path metric in the state S0 (t + 1) is obtained. , P1 (t), B0
There is no need to input (t + 1) again. Similarly, path metrics P1 (t), P5 (t), P3
(T) and P7 (t) are calculated. Therefore, P0 (t), P4 (t),
P1 (t), P5 (t), P2 (t), P6 (t), P
Bit data is stored in the order of 3 (t) and P7 (t). At this time, the order in which the bit data is stored is b
0, b4, b1, b5, b2, b6, b3, b7.

[0004]

However, when a path is selected, the bit data stored in the shift register includes b0, b1, b2, b3, b4, b5, b6,
Must be read in the order of b7. for that reason,
The bit data stored in the shift register is represented by b0, b
There is a problem that a program for rearranging in the order of 1, b2, b3, b4, b5, b6, and b7 is required.

An object of the present invention is to perform hardware processing without performing a program processing for rearranging output data of a shift register when a path is selected.

[0006]

An arithmetic circuit according to the present invention includes a first adder / subtractor for inputting a first signal and a second signal, performing addition or subtraction, and outputting a first operation result signal;
The third signal and the fourth signal are input and the third signal and the fourth signal are input.
Select one of the signals and output the first selection signal
First selecting means for performing, the second signal and the first
Inputting the second signal and the first operation
Select one of the calculation result signals and set the second selection signal
Second selection means for outputting, the first selection signal and the
Inputting a second selection signal and the first selection signal
The third signal and the second selection signal are the second signal.
Addition or subtraction at the time of the signal, the first selection signal is
The fourth signal and the second selection signal is the first signal
Subtraction is performed at the time of the operation result signal to obtain the second operation result signal.
Second adding / subtracting means for outputting the fourth signal,
Operation result signal, the third signal and the second signal
And the fourth signal calculated as
The fourth calculation result signal and the first calculation result signal
Input the sign signal of the signal of
Select the first operation result signal when
The second signal and the third signal when the value of
Selecting the fourth signal calculated with the signal, and selecting the third signal
And third selection means for outputting a signal .

[0007]

[0008]

[0009]

In the arithmetic circuit configured as described above,
Second addition / subtraction operation of outputs of the first and second selection means
The path metric is output according to the result of the means.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of an arithmetic circuit according to the present invention will be described below with reference to the drawings. Here, FIG. 1 is a block diagram showing a detailed configuration of the first embodiment.

The arithmetic circuit according to the present invention comprises a data bus 1, a first addition / subtraction circuit 21, a second addition / subtraction circuit 22, a comparison circuit 3, a first shift register 4, a first selector 5, , A multiplexer 6.

The data bus 1 is connected to a first adding / subtracting circuit 21 and a second adding / subtracting circuit 22.
Reference numerals 22 are connected to the comparison circuit 3 and the first selector 5, respectively. The comparison circuit 3 is connected to a first shift register 4 and a first selector 5, and the first shift register 4 is connected to a multiplexer 6. The first selector 5 and the multiplexer 6 are connected to the data bus 1.

Next, the operation of the first embodiment of the arithmetic circuit according to the present invention will be described with reference to FIGS. 2 and 7, and the multiplexer 6 will be described in detail. FIG. 2 shows the coding rate 1 /
2 is a flowchart showing the operation of the arithmetic circuit of the present invention from time t to time t + 1 of the constraint length 4.

First, the first addition / subtraction circuit 21 receives the path metric P0 (t) and the branch metric B0 (t + 1) from the data bus 1, and the second addition / subtraction circuit 22 receives the path metric P1 (t) from the data bus 1. ) And the branch metric B0 (t + 1). Then, the first addition / subtraction circuit 21 calculates the expression P0 (t) + B0 (t + 1) to obtain the path metric P0 (t + 1), and the second addition / subtraction circuit 22 calculates the expression P1 (t) + B1 (t + 1) (= P1
(T) -B0 (t + 1), that is, B1 (t + 1) =-
B0 (t + 1)) to calculate the path metric P0 (t +
1) is obtained (step 1). The comparison circuit 3 receives the path metric P0 (t + 1) from the first addition / subtraction circuit 21 and the second addition / subtraction circuit 22, and receives the two path metrics P0.
The likelihood of (t + 1) is compared and the likelihood is compared. Then, P0 (t + 1) having a high likelihood is determined as a path metric. Here, the comparison circuit 3 outputs “0” or “1” as a comparison result. For example, when the likelihood of P0 (t + 1) input from the first addition / subtraction circuit 21 is high, “0” is output.
And outputs P0 input from the second addition / subtraction circuit 22.
If the likelihood of (t + 1) is high, “1” is output. Here, the comparison circuit 3 outputs b0 (the data length is
1 bit). The first shift register 4 receives the comparison result from the comparison circuit 3 and simultaneously shifts the currently input data one bit at a time and stores n bits (n is an arbitrary integer) (steps 2 and 3). Here, for example, in the case of a 16-bit fixed-point DSP, a 16-bit register is used. Here, since the number of states is 8, the comparison result is stored for 8 bits. The first selector 5 receives the comparison result from the comparison circuit 3, and the comparison result of P0 that has been determined to be high by the comparison circuit 3 is high.
(T + 1) is selected and output to the data bus 1 (step 5).

Similarly, the arithmetic circuit calculates the path metric from P4 (t + 1) → P1 (t + 1) → P5 (t + 1) →
P2 (t + 1) → P6 (t + 1) → P3 (t + 1) → P
7 (t + 1).

When the above operation is performed, the comparison result is stored in the first shift register 4 as b0 → b4 → b1 → b5 →
It is stored in the order of b2 → b6 → b3 → b7. here,
The multiplexer 6 reads the data stored in the first shift register 4 in the order of the address numbers 0 → 2 → 4 → 5 → 1 → 3 → 5 → 7 as shown in FIG. Then, the data is b0 → b1 → b2 → b3 → b4 → b5 → b6
→ Output to the data bus 1 in the order of b7 (steps 4 and 7). Next, a second embodiment of the arithmetic circuit according to the present invention will be described with reference to the drawings. Here, FIG. 4 is a block diagram showing a detailed configuration of the second embodiment, and the same reference numerals are given to the same and corresponding parts as in FIG.

The arithmetic circuit of the present invention comprises a data bus 1, a first addition / subtraction circuit 21, a second addition / subtraction circuit 22, a comparison circuit 3, a first shift register 4, and a first selector 5. , A multiplexer 6, and a second selector 51.

The data bus 1 is connected to a first adding / subtracting circuit 21 and a second adding / subtracting circuit 22.
Reference numerals 22 are connected to the comparison circuit 3 and the first selector 5, respectively. The comparison circuit 3 is connected to the first shift register 4 and the first selector 5, the first shift register 4 is connected to the multiplexer 6 and the second selector 51, and the multiplexer 6 is connected to the second selector 51. ing. Then, the first selector 5 and the second selector 51
Are connected to the data bus 1.

Next, the operation of the second embodiment of the arithmetic circuit according to the present invention will be described. In each of the circuit units denoted by the same reference numerals as in FIG. 1, the same operation as in the first embodiment is performed, and therefore, the operation of the second selector 51 will be described below.

The second selector 51 receives b0 → b1 → b by a control signal output from an instruction decoder (not shown).
The outputs of the multiplexer 6 arranged in the order of 2 → b3 → b4 → b5 → b6 → b7 and b0 → b4 → b1 → b5 → b2
The first shift register in the order of → b6 → b3 → b7
4 is selected.

Since the second embodiment of the present invention is configured as described above, b0 → b1 →
The output from the multiplexer 6 in the order of b2 → b3 → b4 → b5 → b6 → b7 and b0 → b4 → b1 → b5
First shift consisting of → b2 → b6 → b3 → b7
The output from the register 4 can be selected.

Next, a third embodiment of the arithmetic circuit according to the present invention will be described with reference to the drawings. Here, FIG. 5 is a block diagram showing a detailed configuration of the third embodiment, which is the same as FIG.
Corresponding parts are denoted by the same reference numerals.

The arithmetic circuit of the present invention comprises a data bus 1, a first addition / subtraction circuit 21, a second addition / subtraction circuit 22, a comparison circuit 3, a second shift register 41, and a third shift register 42. , A first selector 5, a third selector 52, and a fourth selector 53.

The data bus 1 is connected to a first adding / subtracting circuit 21 and a second adding / subtracting circuit 22.
Reference numerals 22 are connected to the comparison circuit 3 and the first selector 5, respectively. The comparison circuit 3 is connected to the first selector 5 and the third selector 52, and the third selector 52 is connected to the second shift register 41 and the third shift register 42, and the second shift register 41 and the third The third shift register 42 is connected to the fourth selector 53. The first selector 5 and the fourth selector 53 are connected to the data bus 1.

Next, the operation of the third embodiment of the arithmetic circuit according to the present invention will be described. In each of the circuit units denoted by the same reference numerals as those in FIG. 1, the same operation as in the first embodiment is performed, so that the second shift register 41, the third shift register 42, the third selector 52, and the The operation of the fourth selector 53 will be described.

The comparison circuit 3 calculates the comparison result as b0 → b4 → b
Output in the order of 1 → b5 → b2 → b6 → b3 → b7.
The third selector 52 alternately outputs the input comparison result to the second shift register 41 and the third shift register 42.
Output to First, the third selector 52 sets the comparison result b
0 is output to the second shift register 41, and the second shift register 41 shifts the stored data by one bit and stores the comparison result b0. Next, the third selector 5
2 outputs the comparison result b4 to the third shift register 42, and the third shift register 42 shifts the stored data by one bit and stores the comparison result b4. When the above operation is performed, the second shift register 41 stores the comparison result in the order of b0 → b1 → b2 → b3, and the third shift register 42 stores the comparison result in the order of b4 → b5 → b6 →
Stored in the order of b7. Then, the fourth selector 53
Outputs the comparison result stored in the second shift register 41 and the third shift register 42 to the data bus 1. First, the fourth selector 53 outputs the comparison results b0 to b3 stored in the second shift register 41,
Next, the fourth selector 53 sets the third shift register 42
And outputs the comparison results b4 to b7 stored in. Then, the comparison result is displayed on the data bus 1 as b0 → b1 → b2 → b
They are output in the order of 3 → b4 → b5 → b6 → b7.

Since the third embodiment of the present invention is configured as described above, it is possible to process a data length twice as long as that of the arithmetic circuit formed by one shift register. Further, since a plurality of shift registers are provided, there is no need to provide a memory (not shown) for saving the path metric and the comparison result when the storage capacity of one shift register reaches the limit.

Next, a fourth embodiment of the arithmetic circuit according to the present invention will be described with reference to the drawings. Here, FIG. 6 is a block diagram showing a detailed configuration of the fourth embodiment, which is the same as FIG.
Corresponding parts are denoted by the same reference numerals.

The arithmetic circuit of the present invention comprises a data bus 1, a second addition / subtraction circuit 22, a third addition / subtraction circuit 23, a first selector 5, a fifth selector 54, and a sixth selector 55. , A first shift register 4 and a multiplexer 6. The data bus 1 is connected to the second adder / subtracter 22, the fifth selector 54 and the sixth selector 5
5, the fifth selector 54 and the sixth selector 55 are connected to the third addition / subtraction circuit 23. The third addition / subtraction circuit 23 is connected to the first shift register 4, the first selector 5, and the fifth selector 54, and the second addition / subtraction circuit 22 is connected to the first selector 5 and the sixth selector 55
Is connected to The first shift register 4 is connected to the multiplexer 6, and the multiplexer 6 and the first selector 5 are connected to the data bus 1.

Next, the operation of the fourth embodiment of the arithmetic circuit according to the present invention will be described. In each of the circuit units denoted by the same reference numerals as those in FIG. 1, the same operation as in the first embodiment is performed. Less than,
The operation of the third addition / subtraction circuit 23, the fifth selector 54, and the sixth selector 55 will be described in detail with reference to FIG.

The fifth selector 54 receives the path metric P0 (t) from the data bus 1 and
3 and the sixth selector 55 receives the branch metric B0 (t + 1) from the data bus 1 and outputs it to the third addition / subtraction circuit 23. Then, the third addition / subtraction circuit 23
Calculates the equation P0 (t) + B0 (t + 1), finds the path metric P0 (t + 1), and outputs the found P0 (t + 1) to the first selector 5 and the fifth selector 54.
The second addition / subtraction circuit 22 outputs a path metric P1 (t) and a branch metric B0 (t +
1) to calculate the equation P1 (t) -B0 (t + 1) to obtain the path metric P0 (t + 1).
(T + 1) is replaced by the first selector 5 and the sixth selector 55
Output to

Fifth selector 54 and sixth selector 5
5 output path metrics to the third addition / subtraction circuit 23, and the third addition / subtraction circuit 23 outputs (P0 (t + 1) input from the fifth selector 54)-(P0 (t + 1) input from the sixth selector 55). )). Then, the third addition / subtraction circuit 23 determines whether the result of the calculation is plus (+) or minus (−), and outputs the result to the first shift register 4 and the first selector 5. The first selector 5 outputs the path metric P0 (t + 1) to the data bus 1 according to the result of the third addition / subtraction circuit 23. Then, the comparison result is stored on the data bus 1 by the multiplexer 6 in the order of b0 → b1 → b2 → b3 → b4 → b5 → b
The data is output in the order of 6 → b7.

Since the fourth embodiment of the present invention is configured as described above, there is no need to provide a comparison circuit for selecting one path metric from two path metrics, and the amount of the comparison circuit is eliminated. Power consumption and circuit scale are reduced.

Since the arithmetic circuit of the present invention is configured as described above, it is not necessary to perform a program process for rearranging the output data of the shift register when selecting a path, and a process for selecting a path. Can be completed in a short time. In addition, there is no comparison circuit.
Power consumption and circuit size are reduced.
You.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of an arithmetic circuit according to the present invention.

FIG. 2 is a flowchart showing the operation of the arithmetic circuit of the present invention.

FIG. 3 is a diagram illustrating the operation of the multiplexer of the present invention.

FIG. 4 is a block diagram showing a configuration of a second embodiment of the arithmetic circuit of the present invention.

FIG. 5 is a block diagram showing a configuration of a third embodiment of the arithmetic circuit of the present invention.

FIG. 6 is a block diagram showing a configuration of a fourth embodiment of the arithmetic circuit according to the present invention.

FIG. 7 is a trellis diagram illustrating an operation of a path metric calculation.

[Explanation of symbols]

 21, 22, 23 Addition / subtraction circuit 3 Comparison circuit 4, 41, 42 Shift register 5, 51, 52, 53, 54, 55 Selector 6 Multiplexer

Continuation of front page (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 7/00 G06F 7/24 H03H 17/02 681 H03M 13/23

Claims (2)

(57) [Claims] A first signal and a second signal are input and added.
Calculation or subtraction and outputs the first calculation result signal
One addition / subtraction means,The third signal and the fourth signal are input and the third signal and the fourth signal are input.
Select one of the signals and output the first selection signal
A first selection means to Inputting the second signal and the first operation result signal
Any one of the second signal and the first operation result signal
Selecting means for selecting one of the two and outputting a second selection signal
When, Inputting the first selection signal and the second selection signal
The first selection signal is the third signal and the
Addition or subtraction when the second selection signal is the second signal
The first selection signal is the fourth signal and the
Subtract when the second selection signal is the first calculation result signal
And outputs the fourth signal as a second operation result signal.
Second addition / subtraction means, A first operation result signal, the third signal, and the second signal;
And the fourth signal obtained by calculating the
The fourth signal and the first operation result signal calculated
The sign signal of the fourth signal is input, and the value of the sign signal is negative.
Select the first operation result signal when indicating a value, and sign
When the value of the signal indicates a positive value, the second signal and the second signal
Select the fourth signal calculated with the third signal, the third signal
Third selection means for outputting a selection signal; Composed of
An arithmetic circuit characterized by the above. (2)The code signal is input and the
Shift register means for storing; Receiving the code signal stored in the shift register means;
Multiplexer means for forcing and rearranging in a predetermined order; To
2. The operation according to claim 1, further comprising:
circuit.