JPS58172283U

JPS58172283U - Pulse correction circuit

Info

Publication number: JPS58172283U
Application number: JP6842682U
Authority: JP
Inventors: 佐藤　人志
Original assignee: 日本電気株式会社
Priority date: 1982-05-11
Filing date: 1982-05-11
Publication date: 1983-11-17

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

第１図は公知のダイアル式Ｈ型レピータに使用されてい
る公知のパルス修正回路の回路図である。第２図は第１図のパルス修正回路の動作を示す各部波形
のタイミング図である。第３図は本考案によって構成し
たパルス修正回路の回路図である。第４図は第３図のパルス修正回路の正常動作を示す各部
波形のタイミング図である。第５図は第３図のパルス修
正回路に正極性パルスノイズが加えられたときの各部波
形のタイミング図である。第一６図は第３図のパルス修
正回路に負極性パルスノイズが加えられたときの各部波
形のタイミング図である。１・・・入力端子、２．３・・・単安定マルチバイブレ
ータ、４・・・ＡＮＤゲート、５・・・ＯＲゲート、６
・・・出力端子、７．９・・・抵抗器、８．１０・・・
キャパシタ。FIG. 1 is a circuit diagram of a known pulse correction circuit used in a known dial type H-type repeater. FIG. 2 is a timing diagram of waveforms of various parts showing the operation of the pulse correction circuit of FIG. 1. FIG. 3 is a circuit diagram of a pulse correction circuit constructed according to the present invention. FIG. 4 is a timing diagram of waveforms of various parts showing normal operation of the pulse correction circuit of FIG. 3. FIG. 5 is a timing chart of waveforms of various parts when positive pulse noise is added to the pulse correction circuit of FIG. 3. FIG. 16 is a timing chart of waveforms of various parts when negative pulse noise is added to the pulse correction circuit of FIG. 3. 1... Input terminal, 2.3... Monostable multivibrator, 4... AND gate, 5... OR gate, 6
...Output terminal, 7.9...Resistor, 8.10...
capacitor.

Claims

[Scope of utility model registration request]

a first monostable multivibrator for inverting the state at the rising edge of an input pulse; and an AND gate for performing a logical product of the inverted signal of the output sent from the first monostable multivibrator and the input pulse. and a second monostable multivibrator for inverting the state at the falling edge of the input pulse, and an output of the AND gate and the second monostable multivibrator.
an OR gate for performing a logical sum with the output of the monostable multivibrator; and mutual wiring for inhibiting each other's operation by an inverted signal of the output of the first and second monostable multivibrators; first and second monostable multi-handed vibrators; □ first and second delay circuits that are individually provided and capable of individually adjusting the pulse width of the output to determine the output pulse width of the OR gate; A pulse modification circuit comprising: a pulse modification circuit configured to absorb chattering and noise contained in the input so as to be able to extract a stable output from the OR gate.