JPS58170832U - semiconductor equipment - Google Patents

semiconductor equipment

Info

Publication number
JPS58170832U
JPS58170832U JP6842282U JP6842282U JPS58170832U JP S58170832 U JPS58170832 U JP S58170832U JP 6842282 U JP6842282 U JP 6842282U JP 6842282 U JP6842282 U JP 6842282U JP S58170832 U JPS58170832 U JP S58170832U
Authority
JP
Japan
Prior art keywords
semiconductor equipment
semiconductor chip
metal substrate
plastic
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6842282U
Other languages
Japanese (ja)
Inventor
山岸　始男
伸一 伊藤
Original Assignee
富士電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士電機株式会社 filed Critical 富士電機株式会社
Priority to JP6842282U priority Critical patent/JPS58170832U/en
Publication of JPS58170832U publication Critical patent/JPS58170832U/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案の対象の一例のモールド形半導体装置の
斜視図、第２図はそのリードフレームの支持体部の従来
例の平面図、第３図は同じく側面図、第４図は本考案の
一実施例によるリードフレーム支持体部の平面図、第５
図はその一部拡大図、第６図は同じく側面図である。 １・・・リードフレーム支持体、１１・・・支持面、３
・・・プラスチック、４・・・半導体チップ、５・・・
細溝。FIG. 1 is a perspective view of a molded semiconductor device as an example of the object of the present invention, FIG. 2 is a plan view of a conventional example of the support portion of the lead frame, FIG. 3 is a side view, and FIG. A fifth plan view of a lead frame support portion according to an embodiment of the invention.
The figure is a partially enlarged view, and FIG. 6 is a side view. DESCRIPTION OF SYMBOLS 1... Lead frame support body, 11... Support surface, 3
...Plastic, 4...Semiconductor chip, 5...
narrow groove.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 金属基板上に半導体チップを装着し、プラスチックモー
ルドしてなるものにおいて、金属基板の半導体チップ支
持面に縦横に走る細溝が設けられたことを特徴とする半
導体装置。1. A semiconductor device comprising a semiconductor chip mounted on a metal substrate and molded in plastic, characterized in that narrow grooves running vertically and horizontally are provided on the semiconductor chip supporting surface of the metal substrate.
JP6842282U 1982-05-11 1982-05-11 semiconductor equipment Pending JPS58170832U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6842282U JPS58170832U (en) 1982-05-11 1982-05-11 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6842282U JPS58170832U (en) 1982-05-11 1982-05-11 semiconductor equipment

Publications (1)

Publication Number Publication Date
JPS58170832U true JPS58170832U (en) 1983-11-15

Family

ID=30078205

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6842282U Pending JPS58170832U (en) 1982-05-11 1982-05-11 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS58170832U (en)

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