JPS58168273A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce the area of a P-N-P-N type memory cell and to improve the switching speed of the cell in a semiconductor memory having the cells by employing as a wiring layer a buried layer and forming vertically all transistors forming the P-N-P-N type elements. CONSTITUTION:Transistors Q1, Q2, Q3 forming a P-N-P-N type half cell are all formed in a vertical type in a structure having an N-P-N type transistor QD for driving a word line. a P type buried layer 22 forming a wiring layer of a word line W<+>1, memory cells MC-1, 1 formed on the layer 22 and a P-N-P type transistor QS formed at the periphery of the memory cell formed on an N type semiconductor substrate 21, thereby accelerating the switching and reducing the irregular characteristics. Since the layer 22 is used as the wiring layer of the word line W<+>1, the metal wirings are reduced that much, two contacting windows per memory cell can be eliminated, the yield can be improved, and the area of the cell can be readily reduced.

Description

[Detailed Description of the Invention] (υ The technical field of the invention is related to semiconductor memory fi&amp;
The present invention relates to a semiconductor memory device having a 7-type memory.

Background of the technology, commonly used bipolar semiconductor devices
In devices, memory cells with diode loads or Schittky barrier diode (SBD) loads are widely used.
It is known that the holding voltage Rt/
This is because it is necessary to increase the resistor rIc value for the 9th time when J-reducing, and therefore it becomes difficult to reduce the cell pile.

Therefore, in recent years PNP) Tunister load or NPN) j
PNPN type memory cell I” with resistor load tV
L-type memory cells are attracting attention, but it is generally known that I"L-type memory cells cannot achieve the same operation as PNPN-type memory cells. (3) Conventional technology and problems, conventional type 0 shown in the PNPN type memory cell diagram of
111121m shows the PNPN type memory cell 1I51jlI of FIG. The 1mth memory cell is.

The formation field is formed on the PM111 semiconductor substrate (P-19''Ul) 11, and is insulated by the isolation film (ISO) 1g and 19, and the part that overlaps with the half cell in the circuit shown in Fig. 2 is in the important area. is formed oPJilt@@1
1, a high-KN type sinking layer 12 is formed, and an N type depression area 13 is formed on the columnar layer 12. Two P shadow areas 14° 1s are formed in the N shadow area 13 circle. Field/P-type territory J
ll+! In the 15th yen, two N-type restraint areas 16 and 17 are formed within the half cell, as shown in 〇 218.

11111 oPNP in which three junction pairs Qb -Qm -Qs act as transistors
The type transistor QI has an input region in the P% region 141.

N shadow region 13t pace region, P type region, area 15; oNPN type transistor Q*B formed as a rector region;
The N-type magic area 13 is the collector area, the P-shape area II is the base area, and the N-type shadow area 171 is formed as the entreta area. 'Base area, N shadow area 16
The OP type area 14 is shaped as the entutta area.
．． Contact SR through? 1IIO Akebono 118 W”K
MIN 'Ii tL b o N N area 17 butterfly, connected to second tis*w'''' through contact imt-1
ONN area 16 contact) II 7th I, 4 issued and continued to bit repeat BLt ◇N, shape area 13
Butterfly, Kokutuff) 111 to be derived to point 0, P shadow area 15 companies,;
, @2F11A (DPNPNNP memory cell uses a PNP transistor /Q> as a load, compared to a diode/resistance load type memory cell) However, it can be considered as nine memory dragons.

As schematically shown in Figure 3 of the PNPN type memory cell, the PNP) transistor Qro and the NPN transistor Qs share the pace collector junction and are shown at 1.11112 m. Therefore, it is important to consider the collector current in the equivalent circuit generated using a transistor and the pace electric current.
J ability, *ii, 1st > and 2nd snw,
As shown in Fig. 4, the voltage and electrical properties of the PNPN capacitors constituting the half cell between w'''' are often determined by the negative polarity.・(@
Negative depending on the structure! ! Therefore, it is clear that there are two stable current values for the same voltage value in the characteristic of #I2- PNPN type memory cell in Figure 4. Use two *iitw”
, w- holds the on-state half cell and the off-state half cell t<j out.

At around t, * conventional 1tC) PNPN type memory cell K
As for Thln, it is impossible to use the bulk as a single layer like in the case of I'' L-type memory cells.

*taw, w″″t: The more the wiring must be disposed through one contact layer, the more disadvantageous it is to reducing the cell stack.

1R9, transistor Q as shown in $11all
Although xsQ1 is formed vertically, the transistor is formed horizontally, which tends to cause variations in characteristics, causing a problem in switching speed during writing to 41.

143 Purpose of Yasui The main purpose of the present invention is to solve the problems of the conventional type described in WB and to provide a fast conductor memory device having a PNPN memory cell t-, in which a castle layer is used as a wiring layer and a PNPNyR
By forming the transistors forming the transistors in a horizontal and vertical configuration, it is possible to reduce the width in the horizontal direction and improve the switching speed.

(5) Structure of the Invention In the present invention, a group of pairs of the word line of the broom l connected to the 8-word l1IIIA-link and the 20th saliva line connected to the holding current source, a pair of bit-wrapped O wires, and a memory cell tA provided at each intersection of the pair of axillary bits and the pair of wrinkle bits, each of the scissor memory cells being provided.

In a semiconductor memory device having a pair of 0PNPN elements arranged in parallel with the threshold of the mosquito $11 and the second @ line, the wrinkled cell 0PNPN type element is formed on a -conductivity type semiconductor substrate. However, on the interconducting layer of the opposite conductivity type, there is a l! The PNPN type element is formed in a first region of one conductivity type formed on the embedding layer, and a first region of one conductivity type formed on the first region, and a first region of one conductivity type formed on the first region.
I2 region, third and fourth regions of one conductivity type formed 8j1i apart from each other on the 1g2 region; The 8th and 4th regions each have a predetermined OVmμ on the m plane.
0- Must be a dispersion layer for any-7FO 1-*Mold. A semiconductor memory device is provided as a semiconductor memory device as a detailed explanation of the invention (63).
l, as shown in FIG. The fifth page shows a schematic circuit diagram of the ``O'' conductor memory device.

Happy 6! In a, a water-containing section E1- of the fifth semiconductor memory device on the substrate is shown.
Word 1 of jlI2 that continues to hold electricity tILIII
11W* -...Hx*@O where you can endure the threshold Kll with the crocodile
0 memory cell MC- containing memory khMC-1,j
1. J is 19, pit pair BL1 and BLt-...B
0 memory cell MC-1 . Each piece of j is j121i
A pair of 0% bits connected to the same equivalent path as the PNPN type memory cell connected to the VK has a pit-to-clamp m
Step BCI~BC- and beep) m drive circuit BDt~BD,
〇 Each word embroidery drive transistor QDO pace is connected to W! - Haruka Select Shin 41W L S + '...WL
8n is the mark, mS is the bit-driver rotation jlBD, and the bit layer selection code BLSt...BLSrn is applied to the bit-driver rotation jlBD, ~BD.
A common bit flag level signal BCL is supplied to all sides of Ct to BC-.
, 1 on the substrate is shown in j16FjA.

In the sixth layer, an NPN type transistor QDl for one word spelling formed on an N type semiconductor substrate 11I (N-8UBn 21) is provided.
P-type field layer 22. #I[tliW1 forming the alignment layer. Memory cell MC-1 formed on the implanted layer 22
, 1, and a PNP transistor Q formed around memory cell 0 are shown. The field layer is a high-chain impurity layer that is used as an interconnection layer to increase the conductivity.The memory cells MC-1 and 1 in Figure IIs are of the PNPN type consisting of a pair of half cells as described above. 0 which is a cell
Each half cell O is divided by an isolation 17 area ISO and formed within a large area. This isolation affected area is the cell P4MC-5,j (J = 1-IXII) When dividing into cells, if the interlayer is not separated and n cell rows are separated, in the heat, even 1m interlayer is separated. like,
Isolation adventure t#! In the large area divided into mleO, the N shadow area 23 is merged into 71122 upper KJi
ll@'gt'L, the P shadow region 24 is formed on the N layer region 23, and the N shadow regions 25 and 26 are formed with each other like the P shadow region 24. Equivalence shown in the second - PNP) transistor Q1 in the circuit is a P-type field layer 22
It is formed by the N type region 23 and the P shadow region 24, and the NP
N2 resistor Q, has N shadow area 23. The NPN transistor Q is formed by the P shadow region 24 and the N shadow region 25, and the NPN transistor Q is formed by the N type shadow region 23. P shadow area 24 and N shadow area 2
◎N shadow area of Kakki formed by 5 23. P shadow area 2
4. The N-shaded regions 25 and 26 are connected to the metal wiring through the contact window on the narrow side opposite to the N-type group 1i[21. The oN-type inertial region 25 connected to the P shadow region 24 of is connected to the bit-Ol. The N shadow area 26 is #IIl! 0 embedding layer 2 connected to W
2 is-! The memory cell MC- is connected to fillW1+.
1 and j, and is connected to the metal wiring in the contact hole CH, and is further connected to the vine of the transistor QD.Thus, a buried wiring layer is formed. .

rx, PN in the i11E61m semiconductor memory device
Transistor Q*-Qw- constituting a PN type half cell
Since Qs is all vertically shaped, it has faster switching than K, and the variation in characteristics is smaller.

Since NlI22, which includes 1 run and 2 terms, is used as the layer W7O, when the amount of metal interconnections decreases, the memory cell will become empty and the two contact layers will become wasteful, which will improve the yield and improve the cell design. It is easy to reduce the product.

Next, a semiconductor memory device as a second practical example of the present invention is shown in FIGS. 7, 8, and 9. FIG. 7 shows a memory cell O equivalent to -1I (Als
P and the schematic II formation IBJ are shown in the 0-circuit 8- to the line 7.
1111e (44-body memory steel system) constructed using the memory cells shown in the figure.
*Xi' M
Damn it L jb.

The PNPN type memosa memory cell 28 (NPN, unlike 0%) transistor QI' shown in H7tlJ(2) is used as a load transistor -, PNP)? Injista Ql
It is *g to be held on or in an old school. Therefore, in the semiconductor memory device using the 7th memory cell, as shown in the 8th memory cell, the positive side II
...W + +5 electricity! Who I8 is connected and the third
IWJ... NPN for driving words in town? Njisume Q
DKll+! ! I'm vomiting @ like this, 1s8 #
In P conductor memory reconnaissance, for the one shown in Figure 5,
The polarity of the signal line and the 4ii nature of the transistor are reversed. Therefore, in the configuration on the basic structure shown in No. 9, the conductivity type is reversed between N type and P type, compared to 4 OK in No. 6. Therefore, the semiconductor device of the second practical example As a variation within the second implementation of the III era, the m-containing layer 22' is used as the wiring layer.
W 111110rj! 0 (7) Effects of the Invention According to the present invention, it is important to reduce the cell area taI, and the PNPN type memory 7 has improved switching speed and less variation in characteristics. A semiconductor memory device that can be used can be provided

[Brief explanation of drawings]

11th! ! ; A is a cross section m1iv showing a PNPN memosa memory cell in a conventional semiconductor monolithic memory device. FIG. 2 shows the □PNPN type memory cell @ of the 111g1 T times mTe1a. 1/X3- is a diagram showing a schematic configuration of the equivalent gangway meeting in FIG. 2; FIG. 4 is a diagram showing the voltage and current characteristics of a PNPN type element. FIG. 5 Line 1 is a schematic diagram of a semiconductor memory device as a first example of the present invention. Happy [-shares,,@S-〇tei Configuration of conductor storage device [Wf shown]
tm fat? No. 711 A diagram showing a PNPN type memosa memory cell circuit and a general configuration in a semiconductor memory device as a second embodiment of the present invention. No. 8111 is a schematic circuit of a semiconductor storage device as a second example.
mt=. III OV! A is a cross-sectional view showing an example of a PNPN type memosa memory cell in the semiconductor memory device of the eighth garden.O (Explanation of symbols) 11: P type semiconductor substrate, 12: N layer stacking layer. 13.16, 17: N shadow area, 14, 15: P shadow area. 18.19 Near isolation board, 21: N-type semiconductor substrate. 22; P shaped field inclusion layer, 23, 25, 26: N shadow area. 24: P shadow region, 21': P type semiconductor substrate. 22'; N type buried layer. 23', 25', 26': P shadow area, 24': N shadow area. ISO; 8BD Niji ■ Tsutonaka / Bar Replacement A Diode〇Applicant Fujika Co., Ltd. Patent Application Agent Patent Attorney Akira Aomi Patent Attorney Kazuyuki Nishidate Patent Attorney A3 Yuki Male Patent Attorney Yama Cho 11-111! 1 En 12 Figure 4 (A) (B) Figure 7 (B) v! J81! I

Claims (1)

[Claims] 1. 9. II connected to the drive circuit! Amemaro and holding power ll! The memory cells 11L and II memory 7 include a group of pairs with the 20 words connected to the keyaki, a group of pairs of bits, and a memory cell provided at the intersection of the iim pair and one pair of armpit bits. , 1! in parallel to the threshold of the lIl and the second word line!
In a semiconductor memory device having lN0PNPN type elements connected to each other. The PNPN type element line element of the memory cell is formed on a semiconductor substrate of a conductivity type, and is formed in a single area circle with S current in an isolation region on an implanted layer of a nine-opposite conductivity type.
The PN type bulkhead is formed by forming a JII region of one conductivity type formed on the shelving layer, a II region of the opposite conductivity type formed on the scissors L region, and a second region of the opposite conductivity type formed on the second region. has a third and lI4 region of one conductivity type, and the first and eleventh
2, 313 and lI41m are arranged in the lII direction so that the predetermined connections can be made, respectively, and the wrinkled layer is a wiring layer for any one of the two cases. t
-Characteristics. Semiconductor memory device - 2. Semiconductor memory device according to claim 1, characterized in that the jllll inclusion layer is divided into pairs of pairs - 3. l [- conductivity type is N type The opposite conductivity type is P type. *e Semiconductor memory device according to claim 1. 4@- The conductivity type is P type, and the opposite conductivity type is N type. Semiconductor storage device 0 according to item 1 of IIS of Claim 41