JPS61204961A - Semiconductor circuit apparatus - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION A. INDUSTRIAL APPLICATION The present invention relates to the integration of multiple interconnected current control devices in a semiconductor substrate.

- As the density of devices on a single semiconductor substrate increases, the integration of various circuit configurations and functions.

The ability to be interconnected into integrated semiconductor units has become advantageous in terms of speed and reduced footprint.

B. Prior Art Attempts have been made in the art to form circuits of multiple interconnected devices in integrated substrates. This attempt is made in a single plane, requires fewer interconnections, and
The advantages are that shorter device spacings are not required and fewer connections are required within and outside the semiconductor substrate. U.S. Patent Nos. 3,619,740, 3,639,813, and 40
No. 72,868 is an example of integration in which active devices with different performance characteristics are interconnected and placed side by side in a planar surface of a semiconductor substrate.

(Problems to be Solved by the Invention This invention has been made in consideration of the above-mentioned circumstances.) It is an object of the present invention to provide a novel semiconductor circuit device in which devices are arranged vertically. . .

1) Means for solving the zero problem The present invention provides two current paths in a semiconductor crystal.
This is the circuit integration principle of arranging the circuits in series and parallel to the surface. The flow path has a separate connection at the other end. Adjacent to the surface of the semiconductor crystal, the flow path is connected to the current flowing through it. It is arranged so that it is affected by the =+1 stage of crystallization.

41. Away from the surface of the semiconductor crystal. The current path (-) is defined as the current flowing through
They are arranged in a row.

The construction principle of the present invention provides for single-site integration of all active and passive column circuit devices between two points at different potentials in the circuit in the same occupied area.

E. EXAMPLE 1 FIG. 1 is a schematic diagram illustrating the structural principle of the present invention. A surface layer 1 and an intermediate layer 2 are placed on the base layer 3. For ease of explanation, structures with specific interfels characteristics and conductivity types will be described; however, in light of the principles described herein, one skilled in the art will be able to apply the present invention to various structures using semiconductor principles. It should be applicable. Each layer is epitaxial in the east crystal and has alternating conductivity types, forming an il-I'l junction at interfaces 4 and 5.

This structure uses two current paths stacked in monthly rows for the surfaces in layer 1 and layer 2. Layer 1 has surface 7
Contact point inside 6. #2 is provided with independent and separate ohmic contacts for each layer, such as contact 8. A common ohmic contact 9 is provided to connect the current paths in layers 8 and 2 by ohmic connection. The function of contact 9 is to provide an output point at a node in the circuit path. Depending on the circuit being integrated, the contacts 9 do not necessarily have to be present on the surface of the packaged integrated circuit.

That is, the current path in layer 1 where surface 7 is exposed can be adapted to current control modifications applied externally to the semiconductor crystal. Such amendments.

This is done, for example, by field effect transistor gates or by optical carrier generation. Each of these can influence carrier migration and carrier concentration in the atomization region of layer 18. The exposed area of layer 1 in a good example is the insulation gate I between contacts 6 and 9 - electric field 1 - transistor
Corresponds to Masu Yanel. Thus, the current in layer 1 is the inversion layer current at surface 7 adjacent to the insulating gate 1- applied to layer 1.

The current path in the layer 2 is such that the current flowing therein is influenced by the internal conditions of the crystal, such as the volume conductivity. In addition to the resistivity of 1.3, which is incorporated in the form of druping, the current flowing in layer 2 is determined by the interface Lt p 芙) at the 'R position (,=reI) at the gastric surface 4 and 5. i-junction-pJ・
)ru)1. I'm going to give you a cow, fl notification territory (or number J.

13 layers of monkeys with L=2. Due to the electrocardiographic properties of the current, there is a non-linear characteristic between the contacts of +1. : $-show 1
゜Layer 1 can act as a p-n junction gate of depression sculpting effect 1...Landisk in layer 2.

The construction principle of the invention is that the current control device is placed directly with another device or load between two points with different potentials in the circuit, and the output point is placed in a series path between the two devices. Particularly applicable to circuit integration.

In such circuit branches, output signals are generated between devices, such as between a controller and a load.

In case of vertical integration of such circuit branches as shown in FIG. 1 is made between contacts 8 and 9 in layer 2.

A typical circuit that connects circuit branch devices in series between two points with different potentials and extracts a signal from the branch node is as follows:
It is an inverter type logic circuit. In this type of circuit, a control device and a load device are connected in series in the circuit. The controller in this case is an "always-off" device, such as a Enhancement 1-type field effect transistor (FET), and the load is an "always-on" device, such as a depletion-type junction FET, with layer 1 serving as the integrated gate. ” type device. A unipolar signal, such as a power supply voltage, is applied to the control device,
The current flowing through the control and load devices in series is enhanced. This causes a non-linear decrease in the output voltage at the nodes between the devices.

The integration and performance of such circuits are shown in Figures 2 and 3.
It is shown in Figure 4.

For convenience of explanation and continuity with subsequent explanations,
Although this description selects specific conductivity types and types of control devices, it will be apparent to those skilled in the art that considerable variations in doping, semiconductor material type, and current control mechanisms are possible in light of the principles described herein. It should be.

Referring to FIG. 2, this schematic diagram shows an n-channel FET
This is an example of an inverter type circuit. In FIG. 2, the three layers 1.2.3 may be part of a larger substrate not shown here; all three layers are epitaxial at each interface, and there are no p-types between adjacent regions. - constitutes a single crystal with n junctions 4 and 5. A first low resistance ohmic contact 6, designated as nl, is provided on surface 5 for providing an ohmic connection to the inversion layer below the gate on surface 7. A second low resistance ohmic region 8, denoted as n''', is located at the contact point 6 at the interface of layers 2 and 3.
It is formed near F of. A third low resistance region 9 is arranged on the surface 7 at a spacing 11 sufficient to accommodate the control electrode. Region 9 is shown as n2. In the example integration of FIG. 2, region 9 extends through layer 1 and forms an ohmic contact with layer 2. Region 9 also forms an ohmic contact with the dashed region 1 of the p layer. This is insulating oxide 1
formed by extracrystalline effects such as the potential on the gate, shown schematically as 12, on the upper side of 3, and with a p-type thick conductor on its underside, as in enhancement mode field effect transistors known in the art. Invert the layer to n-type.

The structure of FIG. 2 is manufactured from a P-type substrate as follows. A long linear n0 contact 8 is formed in the p-type substrate by masking techniques and diffusion or ion implantation well known in the art.
form. The mask is removed and the n-type 2 and bilayer 1 are epitaxially grown to the desired thickness and doped by metal organic evaporation or molecular beam epitaxy methods well known in the art. Using normal masking and attachment methods, n+
Region 6, gate insulator 13 and gate electrode 12 are formed. Again, in this technology, n
+ Contact 9 is formed.

In FIG. 2, the control electrodes for the paths in layer 1 are shown schematically as field effect transistor gates. The function of gate 12 is to influence the carriers and thereby contact 6 in layer 1 as in the case of a semiconductor device FET channel.
and 9. In FIG. 2, the positive potential on gate 12 creates an n-type inversion layer at the interface between p-type layer 1 and insulator 13. In FIG.

The type of control function used here is usually dictated by the reactivity of the integrated circuit. A preferred and particularly advantageous structure according to the invention is described here.

This is accomplished by isolating the metal gate member 12 from the surface by an insulating layer, typically an oxide, resulting in a FET structure known in the art as a MOSFET.

In the path through layer 1, a good type of gated controller is an enhancement field effect transistor, and the p-doping level in region 1 results in a moderate signal on the terminal leading to gate 12. The conductivity of the semiconductor near the interface between layer 1 and insulator 13 is adjusted to be n-type. For enhancement-type devices, current flows only when a positive signal on the gate is present. In devices called n-channel devices, where the channel region is n-type, the carriers are electrons, which have higher mobility;
Therefore the speed is greater. The use of dopants of opposite electrical polarity provides a p-channel device, which can also be used in accordance with the principles of the present invention.

The current flowing in layer 2 between contacts 8 and 9 is:

Contact type field effect transistor (JFE1゛) of the technology
The operation similarly depends on the carrier concentration and thickness of layer 2 and the potential along the boundary p-'n junction. That is, the current flowing through layer 2 is non-linear and becomes approximately constant when a large voltage is applied between terminals 8 and 9.

In the inverter type circuit described here, layer 2 is layer 1
Acts as a load for the enhancement type boundary effect transistor current control device inside.

The structure of the present invention thus provides circuit flexibility and backing density advantages when integrated. The flexibility and advantage of this structure is that the conductivity between the independent ohmic contacts and the common ohmic contact can be controlled externally by introducing a signal to the surface, and the p-n
The resistance or space charge associated with the junction allows signals to reach the common contact and to control the conductivity of the central region between the independent ohmic contacts and the common ohmic contact.

Referring now to FIG. 3, a typical circuit branch is illustrated in which active and passive components are connected in series between two points at different potentials. The circuit shown here is a FET enhancement type or depletion type inverter circuit. The inverter circuit of FIG. 3 has the same reference numerals as the structural elements of FIG.

Referring simultaneously to FIGS. 2 and 3, in this circuit the load device 2 is an n-channel in layer 2 of FIG.
It is a JFET transistor. The train electrodes are contacts 8 and are connected via conductors 5. The common contact 9 is connected to the source electrode of the JFET and the JFET.
Serves as an output point to contact 16 for both ET and MOSFET. The MOSFET uses contact 6 as a source electrode connected via conductor 14 to a reference potential or ground. The inverted portion of layer 1 below gate 12 is a MOSFE
Acts as an n-channel of T. The output point in Figure 3 is conductor 16
, and the input point is J in the 6th layer 2 leading to the gate 12.
The conductivity of the FET channel is determined by the interface 4 common to Ml and 2.
is controlled by the potential of the p-n junction of and the voltage between terminals 8 and 9. This interface serves as the J FET gate electrode as described in the circuit diagram of FIG. A positive signal applied at gate 12 turns on the MOSFET, thereby moving the potential at output 16 towards ground, resulting in the opposite signal - to that applied at gate 12.

The advantages and flexibility of the present invention will be further illustrated in the context of composite output characteristic curves of various devices in a stacked circuit path. The performance of each current path device is summarized in the current-voltage (D-V) characteristic curve of FIG. In FIG. 4, curves A and C indicate the case where the gate ``2'' is ``on'', that is, 1, and the case where the gate ``2'' is ``off'', that is, 0.
This is the transfer characteristic of MOSFET in the case of Curve B is the transfer characteristic of the J FET for the current path in layer 2.

The ten signal is the threshold V. The performance when applied to gates 1-2 follows the curve AL = (1'' of gates 1-12).
When Y is O, the performance is V on curve C. That is, clearly defined thresholds and saturation limits are established. .

Several alternatives will occur to those skilled in the art based on the principles of the present invention. The structure itself has been discussed as silicon with an inversion layer, but it can also be applied to intermetallic semiconductors of Groups II and V and It can also be constructed from an alloy thereof, such as a GaAs/GaAs heterojunction structure.

This type of structure is usually created using molecular beam epitaxy techniques. In such a structure, the control device in layer 1 is connected to either the gate 12 or the p-GaAs layer 1 on the surface 7 and the epitaxial AQGaAs region and the epitaxial GaAs layer 1 on the surface 7.
This becomes the A s area. Layer 2 will be n-GaAs, and layer 3 will be semi-insulating GaAs. That is, the control device is a 1-transistor (I (EMT)) with high electron mobility, and the load device is a J FET.

In another variation, the gate 12 is
-GaAs layer and epitaxial AQGaAs epitaxial n''GaAs or metal.

layer] is A Q Ga on the semi-insulating GaAs base layer 3
It becomes epitaxial with A5. Contact point 6, L3.9 becomes n'. The resulting structure consists of a HEMT controller and a HEMT controller.
It becomes an MT load device.

Other features involve the introduction of carriers into the surface 7 by light.

Advantages of the present invention are more particularly useful in the integration of device arrays. In such an array.

The overall circuit uses a number of building block subcircuits assembled as functional elements.

A large number of building block elements, such as discrete bit storage units, are wired in a pattern such as a square grid,
An example is a memory array, which is a multi-bit memory of fixed size and accessibility.

The structural advantages of the present invention in the integration of such building block circuits are explained in connection with FIGS. 5, 6 and 7.

A complete conventional cross-coupled bistable storage cell with addressing gates is shown in FIG. This circuit consists of a control device and a load connected in series between 0 and a reference potential or ground as shown in FIG. Two inverter-type circuit branches whose outputs are cross-coupled and interconnected to a storage device. In FIG. 5, the output points are connected to the X-square signal via a controller responsive to the Y-square signal. The symmetry of such circuits makes it particularly easy to apply the principles of the invention.

Referring now to FIG. 6, the individual regions corresponding to this structure are shown in plan view, and FIG. 7 shows a cross-sectional view of the structure of FIG.

When FIGS. 5, 6, and 7 are viewed together, the integration advantages of the present invention can be clearly seen.

In FIG. 5, conductor 20 is the Y-square line of the array.

The X rectangular conductors 21 and 22 are connected to the X logic function and the X
One inverter branch circuit, carrying a signal representing a logic function, includes devices 23 and 24 in series, and the other branch circuit includes devices 25 and 26. The output of the inverter is cross-coupled to the gate of the control device in the other branch. Addressing FET device and output FET device 2
7 and 28 include gates 29 and 30 for detecting the signal on conductor 20 and providing an output signal to conductors 21 and 22 on a change of state.

Next, referring to FIG. 6, there is shown a plan view of each region of a semiconductor crystal when the circuit of FIG. 5 is manufactured by applying the structural principle of the present invention. In order to make it immediately clear how advantageous the principles of the invention are for the integration of symmetrical circuits, the corresponding contacts of the symmetrical parts are marked with the letter A.

In FIG. 6, the contact 6 of FIGS. 1 and 2 is shown in the center, but it has a contact directly below it that serves as the ground connection or reference potential connection as shown in FIGS. 3 and 5. 8, which is indicated by a broken line. There is another common contact 9, 9A, for the 20th branch, which is placed on both sides of the contact 6. Gate 12 is also the same as 12
There is one more as A, each placed on either side of the contact and directly adjacent to the contact on the exposed portion of the layer between contacts 6 and 9 and 9A. That is, the cross-coupling 31 and "3 i
A is now very simple, crossing only one gate and contact 6 to couple each gate to the common contact of the other branch. Addressing FET transistor and output FET transistors 27 and 28 are respectively the sixth
The gates of these transistors, located at the left and right ends of the figure, are marked 29 and 3o, respectively;
It is located above the exposed portion of the semiconductor bond between 7 and 9 and 28 and 9A. The power line 8 is a buried n''' area, but is contacted around the periphery of the semiconductor chip, as is standard practice in the art.

The cross-sectional view of FIG. 7 shows the stack from another direction. As shown in FIG. 7, both the surface current path conductor 6 connected to a reference potential or ground and the lower current path conductor 8 connected to the ground serve symmetrical branches of the storage circuit. You should be careful. In Figures 6 and 7, all field effect transistors 24.26.2
7.28 is a MO3FET device, and p in the dashed area
They operate by inverting the conductivity to n-type and are arranged in symmetrical positions. Load devices 23 and 25 are layer 2
In the lower current path between the n4'' contact 8 and the contacts 9 and 9A, the present invention preferably includes two layers 1.2.3 each with a thickness of about 1 micron. and is carried out in silicon doped with arsenic for n-doping and boron for p-doping to about 101' atoms/ce, respectively.For long lines, as is commonly done, , before epitaxially growing the various layers.

Contacts 8 can be provided by providing a layer of phosphorus or arsenic on the base layer 3. As shown in FIG. 1, electrical connections can be made by removing a portion of the layer in the desired area, usually around the chip.

contact 6 by diffusing phosphorus or arsenic into the surface.
will be established. The same applies to contacts 32 and 33. Common contacts 9 and 9A are provided by through implantation or diffusion of phosphorus or arsenic prior to the shallow diffusion for 6.32.33.

Gate 12. I2A, 29, 30 are insulators 13 and 1
3 Place metal or polysilicon on top of A (
Zuru. All wiring is provided by masking and aluminum or polysilicon deposition as is well known in the art.

In the device described above, the surface current path and the buried current path are connected by a common ohmic contact. A vertically integrated structure suitable for integrating branch circuit paths between two potential points. Both current paths have separate ohmic contacts, and the current in the surface path can be controlled by extracrystalline means.

F9 Effects of the Invention As described above, according to the present invention, circuits having common connection point terminals can be easily integrated in the vertical direction.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of the structural principle of the present invention. FIG. 2 is a schematic diagram of an inverter type integrated circuit using the construction principle of the present invention. FIG. 3 is a logic circuit diagram of the structure of FIG. 2. FIG. 4 is a schematic wiring diagram of the circuit shown in FIG. 2. FIG. 6 is a plan view of the integration of the circuit of FIG. 5 based on the construction principle of the invention. FIG. 7 is a cross-sectional view of the circuit integration of FIG. 5 based on the construction principle of the invention. 1...Surface layer, 2...Intermediate layer, 3...Base layer, 6.8.9...Contact 712...Gate. Applicant International Business Machines Corporation Sub-Agent Patent Attorney Sawa 1) Toshio V□
V('V

Claims (1)

[Claims] a base body, a central layer formed on the substrate, an upper layer formed on the central layer, and an ohmic first connection portion integrally formed in common with the central layer and the upper layer; a second ohmic connection formed on the upper layer at a predetermined distance from the first connection; and a second ohmic connection formed at a predetermined distance from the first connection and at least in contact with the central layer. a third ohmic connection portion; and current control means disposed close to the surface of the upper layer between the first connection portion and the second connection portion; A semiconductor circuit device, wherein different potentials are supplied to the connecting portions, and an output is obtained from the first connecting portion in accordance with an input from the current control means.