JPS58166042U - third day case - Google Patents

third day case

Info

Publication number
JPS58166042U
JPS58166042U JP6356182U JP6356182U JPS58166042U JP S58166042 U JPS58166042 U JP S58166042U JP 6356182 U JP6356182 U JP 6356182U JP 6356182 U JP6356182 U JP 6356182U JP S58166042 U JPS58166042 U JP S58166042U
Authority
JP
Japan
Prior art keywords
case
lead frame
day case
day
base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6356182U
Other languages
Japanese (ja)
Inventor
島村　美博
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP6356182U priority Critical patent/JPS58166042U/en
Publication of JPS58166042U publication Critical patent/JPS58166042U/en
Pending legal-status Critical Current

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  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の１実施例を示す模型図、第２図は従来
のサーディツプケースを示す模型図、第３図は本考案の
１実施例を示すリードフレームの　□模型図、第４図は
従来のリードフレームを示す模型図。第５図はサーディ
ツプケースのベース。第６図は本考案の一実施例を示す
模型図で上方より見た場合である。 図において、１，１５．３２はベース、２〜１３．１６
〜２７はサーディツプケースの各ピン、　　、１４．２
８，２９，３０．３１はアイランドを示す。 ／Fig. 1 is a model diagram showing an embodiment of the present invention, Fig. 2 is a model diagram showing a conventional surdip case, and Fig. 3 is a model diagram of a lead frame showing an embodiment of the present invention. Figure 4 is a model diagram showing a conventional lead frame. Figure 5 shows the base of the cerdip case. FIG. 6 is a model diagram showing an embodiment of the present invention, viewed from above. In the figure, 1, 15.32 is the base, 2 to 13.16
~27 are each pin of the cer dip case, , 14.2
8, 29, 30.31 indicate islands. /

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ベース、リードフレーム、キャップを含んで構成される
ＩＣサーディツプケースにおいて、前記リードフレーム
上にＩＣチップを設置する場所を設け、該ＩＣのサブス
トレートとケースのグランドピンとを電気的に短絡させ
る手段を有することを特徴とするサーディツプケース。In an IC circuit case including a base, a lead frame, and a cap, a means is provided for installing an IC chip on the lead frame, and electrically shorts the substrate of the IC and a ground pin of the case. A cerdip case characterized by having.
JP6356182U 1982-04-30 1982-04-30 third day case Pending JPS58166042U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6356182U JPS58166042U (en) 1982-04-30 1982-04-30 third day case

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6356182U JPS58166042U (en) 1982-04-30 1982-04-30 third day case

Publications (1)

Publication Number Publication Date
JPS58166042U true JPS58166042U (en) 1983-11-05

Family

ID=30073661

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6356182U Pending JPS58166042U (en) 1982-04-30 1982-04-30 third day case

Country Status (1)

Country Link
JP (1) JPS58166042U (en)

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