JPS59132661U - Insulating substrate for hybrid integrated circuits - Google Patents
Insulating substrate for hybrid integrated circuitsInfo
- Publication number
- JPS59132661U JPS59132661U JP2663483U JP2663483U JPS59132661U JP S59132661 U JPS59132661 U JP S59132661U JP 2663483 U JP2663483 U JP 2663483U JP 2663483 U JP2663483 U JP 2663483U JP S59132661 U JPS59132661 U JP S59132661U
- Authority
- JP
- Japan
- Prior art keywords
- conductive layer
- hybrid integrated
- insulating substrate
- integrated circuits
- insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Insulated Metal Substrates For Printed Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図ａ、 ｂは従来構造図及び回路形成説明図、第
２図ａ、 ｂは本考案の一実施例構造及びその回路形
成説明図である。図において、１は金属基体、２、 ５
． ７は絶縁層、３． ６． ８は導電層、３−１．３
−２．８−１．８−２は導電区域、８−３は接地区域、
９は半田である。1A and 1B are diagrams of a conventional structure and an explanatory diagram of circuit formation, and FIGS. 2A and 2B are diagrams of an embodiment of the structure of the present invention and an explanatory diagram of its circuit formation. In the figure, 1 is a metal base, 2, 5
．． 7 is an insulating layer; 3. 6. 8 is a conductive layer, 3-1.3
-2.8-1.8-2 is a conductive area, 8-3 is a grounding area,
9 is solder.
Claims (2)
第２導電層を順次積層すると共に前記第２導電層の所要
部を回路用接地（アース）区域とし、且つ、前記接地区
域と前記第１導電層を電気的に接続したことを特徴とす
る混成集積回路用絶縁基板。(1) An insulating layer, a conductive layer, a second insulating layer, and a second conductive layer are sequentially laminated on a metal substrate, and a necessary part of the second conductive layer is used as a circuit grounding (earth) area, and the grounding An insulating substrate for a hybrid integrated circuit, characterized in that the area and the first conductive layer are electrically connected.
削除して第１導電層を露出せしめ該露出部を介して接地
区域と電気的に接続するようにしたことを特徴とする実
用新案登録請求の範囲第１項記載の混成集積回路用絶縁
基板。(2) Parts of the second conductive layer and second insulating layer on the metal base are removed to expose the first conductive layer, and the first conductive layer is electrically connected to the ground area through the exposed portion. An insulating substrate for a hybrid integrated circuit according to claim 1 of the utility model registration claim.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2663483U JPS59132661U (en) | 1983-02-25 | 1983-02-25 | Insulating substrate for hybrid integrated circuits |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2663483U JPS59132661U (en) | 1983-02-25 | 1983-02-25 | Insulating substrate for hybrid integrated circuits |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59132661U true JPS59132661U (en) | 1984-09-05 |
Family
ID=30157547
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2663483U Pending JPS59132661U (en) | 1983-02-25 | 1983-02-25 | Insulating substrate for hybrid integrated circuits |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59132661U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH036096A (en) * | 1989-06-02 | 1991-01-11 | Matsushita Electric Works Ltd | Circuit board |
| WO1999052337A1 (en) * | 1998-04-03 | 1999-10-14 | Sumitomo Metal Mining Co., Ltd. | Printed-circuit board with bypass capacitor for mounting integrated circuit, and method of manufacture |
| JP2010087128A (en) * | 2008-09-30 | 2010-04-15 | Sanyo Electric Co Ltd | Circuit device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS475718U (en) * | 1971-02-09 | 1972-09-19 |
-
1983
- 1983-02-25 JP JP2663483U patent/JPS59132661U/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS475718U (en) * | 1971-02-09 | 1972-09-19 |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH036096A (en) * | 1989-06-02 | 1991-01-11 | Matsushita Electric Works Ltd | Circuit board |
| WO1999052337A1 (en) * | 1998-04-03 | 1999-10-14 | Sumitomo Metal Mining Co., Ltd. | Printed-circuit board with bypass capacitor for mounting integrated circuit, and method of manufacture |
| JP2010087128A (en) * | 2008-09-30 | 2010-04-15 | Sanyo Electric Co Ltd | Circuit device |
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