JPS58166034U - 半導体製造装置 - Google Patents
半導体製造装置Info
- Publication number
- JPS58166034U JPS58166034U JP1982064246U JP6424682U JPS58166034U JP S58166034 U JPS58166034 U JP S58166034U JP 1982064246 U JP1982064246 U JP 1982064246U JP 6424682 U JP6424682 U JP 6424682U JP S58166034 U JPS58166034 U JP S58166034U
- Authority
- JP
- Japan
- Prior art keywords
- cavity
- semiconductor manufacturing
- manufacturing equipment
- substrate
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Moulds For Moulding Plastics Or The Like (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
め要約のデータは記録されません。
Description
第1図は絶縁形樹脂モールド型半導体装置の一例を示す
部分透視平面図、第2図は第1図A−A面図、第3図は
樹脂モールド装置の一例を示す側−面図、第4図は本考
案による樹脂モールド装置の側断面図、第5図及び第6
図は第4図装置の動作を説明する側断面図を示す。
−1・・・・・・基板、2・・・・・・半導体ペレッ
ト、5・・・・・・樹脂モールド部、8・・・・・・キ
ャビティ、9・・・・・・可動片。
部分透視平面図、第2図は第1図A−A面図、第3図は
樹脂モールド装置の一例を示す側−面図、第4図は本考
案による樹脂モールド装置の側断面図、第5図及び第6
図は第4図装置の動作を説明する側断面図を示す。
−1・・・・・・基板、2・・・・・・半導体ペレッ
ト、5・・・・・・樹脂モールド部、8・・・・・・キ
ャビティ、9・・・・・・可動片。
Claims (1)
- 半導体ベレン“トを固定した基板をキャビティ内゛ に
位置決め固定し、樹脂を充填して、゛半導体ペレット並
びに基板を樹脂にて被覆するものにおいて、上記基板の
裏面とキャビティ内面の間隔を規制する可動片をキャビ
ティ内に突出退入自在に慇けたことを特徴とする半導体
製造装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1982064246U JPS58166034U (ja) | 1982-04-30 | 1982-04-30 | 半導体製造装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1982064246U JPS58166034U (ja) | 1982-04-30 | 1982-04-30 | 半導体製造装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58166034U true JPS58166034U (ja) | 1983-11-05 |
Family
ID=30074286
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1982064246U Pending JPS58166034U (ja) | 1982-04-30 | 1982-04-30 | 半導体製造装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58166034U (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02114542A (ja) * | 1988-10-24 | 1990-04-26 | Rohm Co Ltd | 半導体装置におけるモールド部の成形装置 |
-
1982
- 1982-04-30 JP JP1982064246U patent/JPS58166034U/ja active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02114542A (ja) * | 1988-10-24 | 1990-04-26 | Rohm Co Ltd | 半導体装置におけるモールド部の成形装置 |
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