JPS58164267A - Manufacture of thin film silicon transistor - Google Patents

Manufacture of thin film silicon transistor

Info

Publication number
JPS58164267A
JPS58164267A JP57047975A JP4797582A JPS58164267A JP S58164267 A JPS58164267 A JP S58164267A JP 57047975 A JP57047975 A JP 57047975A JP 4797582 A JP4797582 A JP 4797582A JP S58164267 A JPS58164267 A JP S58164267A
Authority
JP
Japan
Prior art keywords
thin film
substrate
film
transparent substrate
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57047975A
Other languages
Japanese (ja)
Inventor
Takeo Yamada
山田 彪夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP57047975A priority Critical patent/JPS58164267A/en
Publication of JPS58164267A publication Critical patent/JPS58164267A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Shift Register Type Memory (AREA)

Abstract

PURPOSE:To improve the yield and the reliability of a silicon transistor by slightly etching the surface of a transparent substrate, and then forming thin film Si transistor through an insulating film of a sole layer or multilayer of different purity and composition from those of the substrate. CONSTITUTION:The surface of a soda glass substrate 7 is slightly etched with HF diluted solution, the gate film 9 of a CVD SiO2 and a P-added polysilicon electrode are formed, and with the gate electrode as a mask P is implanted in high density. The CVD SiO2 film is covered, a window is opened, and metal wirings 10 of Al-Si alloy are attached. After the surface is slightly etched and cleaned in this manner, an insulating film of CVD SiO2, PSG, or Si3N4 of different composition from the transparent substrate in high purity is superposed in a sole layer or multilayer, and a thin film Si transistor is formed through the insulating film, thereby eliminating the invasion of contamination into the substrate, preventing the leakage of the surface of the substrate, stabilizing the initial characteristics and improving the yield.

Description

【発明の詳細な説明】 本発明は石英板あるいはソーダガラス、ネウケイ酸ガラ
ス等の透明基板上に形成される多結晶シリコン、あるい
はアモルファスシリコンの薄膜シリコントランジスター
に関するものである。近都情報化社金といわれる中でコ
ンビ凰−ター関連機赫の発展には目ざましいものがあり
、これにともない表示装置も従来からのOR’!’にか
わるものとして平面ディスプレーの開発も盛んに行なわ
れている。特に平面ディスプレーでは液晶を用いたもの
が低電力、低電圧ならびに受光タイプとしてO見易すさ
の面で時計電卓にはもとより家電製品。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a thin film silicon transistor of polycrystalline silicon or amorphous silicon formed on a transparent substrate such as a quartz plate, soda glass, or neusilicate glass. In the midst of the so-called "neighborhood information society," there has been a remarkable development in combination printer-related equipment, and along with this, display devices have also changed from the conventional OR'! Flat displays are being actively developed as an alternative to '. In particular, flat displays that use liquid crystals are low power, low voltage, and light-receiving types, making them easy to read, making them useful not only in watch calculators but also in home appliances.

自動車用パネルとしても巾広く用いられてきている。It has also been widely used in automobile panels.

又現在ORTに替る安価な平面ディスプレーとして注目
されているものに薄膜トランジスターのアクティブマト
リクスによって液晶を駆動する方式が検討されている。
Furthermore, a system in which liquid crystal is driven by an active matrix of thin film transistors is currently being considered as an inexpensive flat display that is attracting attention as an alternative to ORT.

これは透明基板上にスイッチング用薄膜トランジスタ回
路をマトリクス状に形成しこの基板と他の透明ガラス板
間に液晶を封入した両像表示用のディスプレーパネルで
ある。
This is a display panel for dual-image display, in which switching thin film transistor circuits are formed in a matrix on a transparent substrate, and liquid crystal is sealed between this substrate and another transparent glass plate.

従来報告されている一般的な薄膜シリコントランジスタ
の構造は第1図の如く先ず透明基板1上ニ多1i1F晶
シリコンあるいはアモルファスシリコン等の薄膜シリコ
ン2をIMIILIII&ホシエッチングによりトラン
ジスタWI或部のみを残し他の薄膜シリコンを除去する
The structure of a conventionally reported general thin film silicon transistor is as shown in FIG. 1. First, a thin film silicon 2 such as 1I1F crystal silicon or amorphous silicon is deposited on a transparent substrate 1 by IMIILIII and photo etching, leaving only a certain part of the transistor WI. Remove the thin film of silicon.

次に該薄膜シリーン表面に酸化主1を熱酸化方式あるい
は071)方式にて形成し*酸化膜上にゲート電極用の
薄膜シリ;ンを堆積しホトエツチングによりゲージ電極
を形成する。ゲージ電極は不純物を含有する薄膜シリコ
ンを直接堆積する方法か、あるいは薄膜シリコンを堆積
後不純物を熱拡散し配線抵抗を下げる工夫がなされる。
Next, an oxide film 1 is formed on the surface of the thin film silicon by a thermal oxidation method or a 071) method, and a thin film silicon for a gate electrode is deposited on the oxide film, and a gauge electrode is formed by photoetching. The gauge electrode is formed by directly depositing a thin silicon film containing impurities, or by depositing a thin silicon film and then thermally diffusing the impurities to lower the wiring resistance.

次にイオン打込みを前記ゲー)電極なiスフに行ないソ
ース、ドレイン部を形成後基板主面上に絶縁膜4を堆積
する。
Next, ion implantation is performed on the i-layer of the gate electrode to form source and drain portions, and then an insulating film 4 is deposited on the main surface of the substrate.

次にホトエツチングによりコンタクFホールを開孔した
後金属配線5を廖虞する。
Next, a contact F hole is formed by photo-etching, and then the metal wiring 5 is cut out.

以上の如〈従来の一般的な薄膜シリコントランジスター
の製法は透明基板が石英板あるいはガラス等の絶縁基板
を用いることからトランジスター形成用の薄膜シリコン
を基板主面に直II形成していた。
As described above, in the conventional general manufacturing method of thin film silicon transistors, since the transparent substrate uses an insulating substrate such as a quartz plate or glass, the thin film silicon for forming the transistor is formed directly on the main surface of the substrate.

しかしながらこれら透明基板表面は表面研磨に使用サレ
るアル環す粉末あるいは酸化セリウム等の研磨材が研磨
キズ等の表面凹凸部に付着しておりしかも石英板は別と
してその他のガラス製基板はナトリウムイオンを始めと
する種々の可動イオン及び鉄イオン、Sイオン等の金属
イオンが含有されているため、透明基板表面を一般的な
洗浄をはどこしても前記汚染物等を完全に除去せしめる
ことは不可能である。このため透明基板上に薄膜トラン
ジスタを形成する際に加わる幾多の熱処理過程において
これら不純物が薄膜シリコン内に浸入しTNT特性に悪
影響を及ぼしON電流の低下あるいは071F電流の異
状な増加等初期歩留りの低下は勿論長期信頼性の面でも
問題となる。
However, on the surface of these transparent substrates, abrasives such as aluminum powder or cerium oxide used for surface polishing adhere to surface irregularities such as polishing scratches, and apart from quartz plates, other glass substrates have sodium ions. Because it contains various mobile ions such as iron ions, metal ions such as iron ions, and sulfur ions, it is impossible to completely remove the contaminants even if the surface of the transparent substrate is cleaned in a general manner. It's impossible. For this reason, during the numerous heat treatment processes applied when forming thin film transistors on transparent substrates, these impurities penetrate into the thin film silicon and adversely affect the TNT characteristics, causing a decrease in the initial yield such as a decrease in ON current or an abnormal increase in 071F current. Of course, there is also a problem in terms of long-term reliability.

しかも純度の悪い透明基板においては不純物にょる基板
の表面リークも問題視される。
Moreover, in transparent substrates with poor purity, surface leakage of the substrate due to impurities is also seen as a problem.

そこで本発明はかかる従来の欠点を除去し信頼性の高い
薄膜トランジスタの製造を可能ならしむるものであり以
下本発明を実施例にもとすき説明する。
Therefore, the present invention eliminates such conventional drawbacks and makes it possible to manufacture highly reliable thin film transistors.The present invention will be explained below using examples.

実施例1 92図は本発明による透明基板上に薄膜シリコントラン
ジスタを絶縁膜6を介して形成したものである。
Embodiment 1 FIG. 92 shows a thin film silicon transistor formed on a transparent substrate with an insulating film 6 interposed therebetween according to the present invention.

先ず、透明基板(ソーダガラスを使用)7を充分洗浄し
た後表面を7ツ酸の希釈液にて約10001除去する。
First, after thoroughly cleaning the transparent substrate (using soda glass) 7, the surface was removed with a diluted solution of 70% acid.

そしてown法にて酸化J[6を50oo1%成する。Then, 50001% of oxidized J[6 was formed by the own method.

そしてこのOVD酸化膜6上に多結晶シリコン膜8を5
0001形成しホトエツチングにより蒙多結晶シ9:1
ン膜をFランジスタ形成部のみ残し他を除去する。
Then, a polycrystalline silicon film 8 is formed on this OVD oxide film 6.
0001 formed and photoetched to obtain a polycrystalline crystal of 9:1.
Leave only the F transistor forming part and remove the other parts of the conductive film.

次に前記多結晶シリコン膜上にOVD法にてゲート酸化
膜?120001堆積し、つづいてゲート電極用のリン
ドープ多結晶シリンコンを堆積し、ホトエツチングにて
ゲー)電極を形成する。
Next, a gate oxide film is formed on the polycrystalline silicon film using the OVD method. 120001 is deposited, followed by depositing phosphorus-doped polycrystalline silicon for a gate electrode, and forming a gate electrode by photoetching.

次に前記ゲージ電極をマスクにリンを高濃度にてイオン
打込みする。
Next, using the gauge electrode as a mask, phosphorus is ion-implanted at a high concentration.

ソースドレインの形成されたトランジスタ部を含む透明
基板主面上にO’VD法にて酸化膜を50001堆積し
たのちホトエツチングによりソースドレイン部のコンタ
クトを開孔する。
After depositing 50,000 layers of oxide film by O'VD on the main surface of the transparent substrate including the transistor section where the source/drain is formed, a contact hole for the source/drain section is formed by photoetching.

次に金属配線材としてアルミシリコン合金を基板主面に
スパッタリングしたのちホトエツチングにて金属配線1
0を形成する。
Next, an aluminum silicon alloy was sputtered on the main surface of the substrate as a metal wiring material, and then metal wiring 1 was formed by photo-etching.
form 0.

以上説明の如く本発明は透明基板上に薄膜シリコントラ
ンジスタを形成するに際し先ず透明基板表面層をわずか
エツチング除夫したのち純度の高いしかも透明基板とは
組成の興なる一VD酸化膜を介して薄膜シリコントラン
ジスタを作り込むため基板中の汚染物の浸入を防ぐとと
もに基板表面の不純物による表面リークの防止とも合わ
せ特に初期T1!特性の安定化に大きな効果が得られて
いる。
As explained above, when forming a thin film silicon transistor on a transparent substrate, the present invention first slightly etches and removes the surface layer of the transparent substrate, and then forms a thin film via a VD oxide film of high purity and a composition different from that of the transparent substrate. Since silicon transistors are manufactured, it is necessary to prevent contaminants from entering the substrate, and also to prevent surface leakage due to impurities on the substrate surface, especially in the initial T1! A great effect has been obtained in stabilizing the characteristics.

なお上記ソーダガラス基板の他ホウケイーガラスあるい
は他の透明ガラス基板上についても実施例1と同様の方
法にて薄膜シリコントランジスタ(多結晶シリ;ン及び
アモルファスシリコントランジスタ)を形成した場合て
もやはり同様の特性安定化の確固が得られている。
In addition to the above-mentioned soda glass substrate, even if thin film silicon transistors (polycrystalline silicon and amorphous silicon transistors) are formed on porcelain glass or other transparent glass substrates in the same manner as in Example 1, the same results will be obtained. The stability of the characteristics has been firmly established.

実施例2 透明基板7′を充分洗浄した後表面層を7ツ酸希釈液に
て1ooo1エツチング除去ししかる後基板主面上にホ
スピンガスを用いて約8モルのリンシリケートガラスを
CVD法にて50001堆積し、さらに多結晶シリコン
膜8′を50001形成する。以下の工程は実施例1と
同様である。
Example 2 After thoroughly cleaning the transparent substrate 7', the surface layer was removed by etching 10001 with a diluted 7' acid solution, and then approximately 8 mol of phosphosilicate glass was deposited on the main surface of the substrate by CVD using phospine gas. A polycrystalline silicon film 8' is further formed in a thickness of 50,001. The following steps are the same as in Example 1.

絶縁膜としてリンシリケートガラスを用いることにより
、リンのゲッタ作用により実施例1に増してパシペーシ
買ン属としての効果が大きく初期〒νT特性の安定化は
勿論のこと長期安定性でも大きな効果を得た。
By using phosphorus silicate glass as the insulating film, the getter action of phosphorus has a greater effect as a passivation agent than in Example 1, and a great effect is obtained not only in stabilizing the initial 〒νT characteristic but also in long-term stability. Ta.

実施H5 透明基板7″を先ず充分に洗浄した後7ツ酸希釈液にて
基板表面を&’lロ001エツチング除去し、しかる後
プラズマチッカ属形成炉にてアルゴンペース1−モノシ
ランガスと11ガスを用いて約550℃温度にてチッカ
展を20001堆積しさらに多結晶シリコン膜8jIt
t形威し以下実施例1と同一工程にて薄膜トランジスタ
を形成した。
Implementation H5 First, the transparent substrate 7'' was thoroughly cleaned, and then the surface of the substrate was etched with &'lRO001 using a diluted acid solution, and then argon paste 1-monosilane gas and 11 gas were added in a plasma ticker forming furnace. Then, a polycrystalline silicon film 8jIt was deposited at a temperature of about 550°C.
A thin film transistor was formed using the same steps as in Example 1, including T-type stamping.

本チッカ展はプラズマ中においてモノシランガスを用い
て°形成されるものであり低温にてしかもチッカ膜特有
のち密な膜の形成が可能なことから汚染物の浸入を防止
する目的として非常に有効な手段であり実施例1.2と
同様又はそれ以上の効果が得られている。
This ticker film is formed using monosilane gas in plasma, and it is possible to form a dense film unique to ticker films at low temperatures, making it an extremely effective means for preventing the infiltration of contaminants. Therefore, an effect similar to or better than that of Example 1.2 is obtained.

実施(’: ’ s 2e 5の他透明基板上に形成す
る絶縁膜としてシリカ拡散塗布剤として知られている波
状塗布剤を用いてスピンコードした後400℃前後の温
度にて加熱し絶縁膜を形成する方法あるいは、液状のl
リイミド樹脂をスビンフートシ絶縁膜を形成する方法に
ついても試みてみたがそれぞれ特性安定化への効果がみ
られている。
Implementation (': ' In addition to s 2e 5, the insulating film is formed on a transparent substrate by spin-coding using a wavy coating agent known as a silica diffusion coating agent, and then heating it at a temperature of around 400°C to form an insulating film. Method of forming or liquid l
We have also tried methods of forming an insulating film using reimide resin, and each method has been found to be effective in stabilizing the characteristics.

実施例4 本発明による薄膜シリコントランジスタを用いてアクテ
ィブマトリクスを構成した例を説明する。
Example 4 An example in which an active matrix is constructed using thin film silicon transistors according to the present invention will be described.

第S図の如く透明基板11を7ツ酸希釈液にて約100
0xl1両エツチングした後0’VD法にて酸化膜12
を堆積したのち多結晶シリコン膜15を堆積したのちホ
トエツチングにてトランジスタ部を除き他の多結晶シリ
コン膜を除資する。
As shown in FIG.
After etching both 0xl1, the oxide film 12 is etched using the 0'VD method.
After depositing a polycrystalline silicon film 15, photoetching is performed to remove the transistor portion and remove the other polycrystalline silicon film.

次に前記多結晶シリコン膜の上層にCVD法にてゲート
酸化膜14を形成し、つづいてゲート電極用のリンドー
プ多結晶シリコン膜15を形成したのちホトエツチング
にてゲート配線部を形成する次に高濃度のリンをイオン
打込みしソースドレイン部を形成する。
Next, a gate oxide film 14 is formed on the polycrystalline silicon film by the CVD method, followed by a phosphorus-doped polycrystalline silicon film 15 for the gate electrode, and then a gate wiring portion is formed by photoetching. A source/drain portion is formed by ion implantation of phosphorus at a high concentration.

次に基板主面上にown法にて酸化膜16・を堆積後ホ
トエツチングにてフンタクトホールな開孔する。
Next, an oxide film 16 is deposited on the main surface of the substrate by the own method, and then a direct hole is formed by photoetching.

次に透明導電膜を約l5001スパツタリングしてホト
エツチングののち透明電極唱7を形成する。
Next, a transparent conductive film is sputtered by about 1500 cm, and after photo-etching, a transparent electrode layer 7 is formed.

次に金属配線用のアル曙シリプン合金をスパッタリング
したのちホトエツチングを行ないソースラインのみ金属
配41118を形成する。
Next, after sputtering AlAkebono silicon alloy for metal wiring, photoetching is performed to form metal wiring 41118 only on the source line.

以上の如く本発明は透明基板を用いて形成される簿膜シ
リコントランジスターの製造に関し先ず透明基板表面に
固着しているアルミナあるいは酸化セリウム等の研磨材
や研磨時に用し′)られる接着材等を7ツ酸の希釈液に
てエツチング除去するため基板表面の汚れが後工程にて
トランジスター内部に浸入することを防止していること
と、さらに透明基板内部より拡散される夏aイオンある
いは1・、Ou等の金属イオンは基板表面にあらかじめ
形成される絶縁膜によりトランジスタ内部への拡散を防
止している。
As described above, the present invention relates to the production of a thin film silicon transistor formed using a transparent substrate. First, the polishing material such as alumina or cerium oxide fixed to the surface of the transparent substrate and the adhesive used during polishing are used. Etching is performed using a dilute solution of 7-acid to prevent dirt on the substrate surface from penetrating into the inside of the transistor in the subsequent process, and furthermore, it is possible to prevent dirt on the surface of the substrate from penetrating into the inside of the transistor in the subsequent process. Metal ions such as O are prevented from diffusing into the transistor by an insulating film formed in advance on the substrate surface.

このため、本発明による薄膜シリコントランジスタのT
??特性は従来方式に較べ格段と安定化されており基板
内の特性のバラツキも非常に減少している。
Therefore, the T of the thin film silicon transistor according to the present invention is
? ? The characteristics are much more stable than those of the conventional method, and the variation in characteristics within the substrate is also greatly reduced.

又上記の方法にて形成した薄膜シリコントツ/ジスタを
用いてなるアクティブマトリクス基板において薄膜シリ
コントランジスターの!νT特性は安定しており信号電
流のON10 ?ν比は104以上と良好であった。し
かもアクティブマFリクス基板を用いた液晶表示パネル
による評価においても表示特性は良好であり特に従来方
式にて製造された表示パネルと比べて表面リークは皆無
であり、画素ごとの明暗のむら、あるいは両面の場所に
よる表示むら等及び欠陥の発生等において、顕著な差が
見られることからも本発明は薄膜シリコントランジスタ
ーの特性安定化に及び長期信頼性の向上に大きく寄与す
るものといえる。
Also, in an active matrix substrate using thin film silicon transistors/transistors formed by the above method, thin film silicon transistors can be formed! The νT characteristics are stable and the signal current ON10? The ν ratio was 104 or more, which was good. Moreover, the display characteristics were good in evaluations using liquid crystal display panels using active matrix F substrates, and there was no surface leakage compared to display panels manufactured using conventional methods, and there was no unevenness in brightness or darkness for each pixel, or both sides. It can be said that the present invention greatly contributes to stabilizing the characteristics and improving the long-term reliability of thin film silicon transistors since there are noticeable differences in display unevenness and the occurrence of defects depending on the location.

なお実施例において透明基板上に形成する絶縁膜はすべ
て単層にて用いているが例えばOVD法による酸化膜を
単層で用いるより先ずリンシリケートガラスを形成後連
続してノンドープの酸化M[I形成した2層絶縁属の方
が不純物のパシベーシ曹ン効果はより効果が得られるこ
とは云うまでもなく、さらにノンドープ酸化層にてリン
シリケートガラスを両面からはさみ込み5層方式ではさ
らにその効果をあげることも確認されている。
In the examples, all the insulating films formed on the transparent substrate are used as a single layer. For example, rather than using a single layer of oxide film by OVD method, phosphosilicate glass is first formed and then non-doped oxidized M[I It goes without saying that the passivation carbon effect of impurities is more effective in the formed two-layer insulating metal, and the five-layer method in which phosphorus silicate glass is sandwiched from both sides in the non-doped oxide layer further improves this effect. It has also been confirmed that it will.

さらに透明基板表面のエツチングに関しては基板の研磨
状態により除去する量を加減する必Vがあるが基板表面
の凹凸を考慮し1ooo1程度が良
Furthermore, when etching the surface of a transparent substrate, it is necessary to adjust the amount to be removed depending on the polishing condition of the substrate.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の製造方式による透明基板上に形成された
薄膜シリコントランジスターの断面構造である。 第2図は本発明によるところの透明基板上に形成された
薄膜シリコントランジスタの断面構造である。 第3図は本発明による薄膜トランジスタをマトリクス状
に透明基板上に構成してなるアクティブマトリクス基板
の1部断面構造である。 1・・・・・・透明基板 2・・・・・・薄膜シリコン 3・・・・・・酸化膜 4・・・・・・絶縁膜 5・・・・・・金属配線 ゛ 6・・・・・・絶縁膜(酸化膜) 7.7/、7#・・自・・透明基板 8.8’、8’・・・・・・多結晶シリコン属!・・・
・・・ゲート酸化膜 10・・・・・・金属配線 11・・・・・・透明基板 12・・・・・・酸化膜 13・・・・・・多結晶シリコン属 14・・・・・・ゲート酸化膜 15・・・・・・多結晶シリコン膜 16・・・・・・酸化膜 17・・・・・・透明電極 1s・・・・・・金属配線 以上 出願人 株式金社諏訪精工舎 代理人 弁理士 最上  務 第3図
FIG. 1 shows a cross-sectional structure of a thin film silicon transistor formed on a transparent substrate using a conventional manufacturing method. FIG. 2 is a cross-sectional structure of a thin film silicon transistor formed on a transparent substrate according to the present invention. FIG. 3 is a partial cross-sectional structure of an active matrix substrate in which thin film transistors according to the present invention are arranged in a matrix on a transparent substrate. 1... Transparent substrate 2... Thin film silicon 3... Oxide film 4... Insulating film 5... Metal wiring ゛ 6... ... Insulating film (oxide film) 7.7/, 7# ... Transparent substrate 8.8', 8' ... Polycrystalline silicon! ...
... Gate oxide film 10 ... Metal wiring 11 ... Transparent substrate 12 ... Oxide film 13 ... Polycrystalline silicon 14 ...・Gate oxide film 15...Polycrystalline silicon film 16...Oxide film 17...Transparent electrode 1s...Metal wiring and above Applicant Kinsha Suwa Seiko Co., Ltd. Attorney Mogami Patent Attorney Figure 3

Claims (1)

【特許請求の範囲】 (1)  透明基板上に薄膜シリコントランジスタ士を
形成するにあたり先ず前記透明基板をわずか表面エツチ
ングしたのち譲透明基板上に絶縁膜を介して薄膜シリラ
ントランジスタを形成することを特徴とする薄膜シリ;
ントツンジスタの製造方法。 (J)  透明基板上&:廖威する絶縁属はOvng化
膜、リンシリケーFガラス、チッカ膜郷の絶縁膜が単層
あるいは多層で構成することを特徴とする特許請求の範
8第−項記戦の薄膜シリコントランジスタの製造方法。 (8)  透明基板上に廖處される絶縁膜は前記透明基
板とは純度ならびに組成を興にして形成することを特徴
とする特胛曽求o*sg−項記載の薄膜シリコントラン
ジスタの製造方法。
[Scope of Claims] (1) In forming a thin film silicon transistor on a transparent substrate, the surface of the transparent substrate is first slightly etched, and then a thin film silicon transistor is formed on the transparent substrate via an insulating film. Features of thin film silicon;
Method of manufacturing nttunjista. (J) On the transparent substrate &: Claim 8, characterized in that the active insulating material is composed of a single layer or a multilayer insulating film of Ovng chemical film, phosphor silicate F glass, or Tikka film. A method for manufacturing thin film silicon transistors. (8) The method for manufacturing a thin film silicon transistor as described in the above paragraph, characterized in that the insulating film formed on the transparent substrate is formed by considering the purity and composition of the transparent substrate. .
JP57047975A 1982-03-25 1982-03-25 Manufacture of thin film silicon transistor Pending JPS58164267A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57047975A JPS58164267A (en) 1982-03-25 1982-03-25 Manufacture of thin film silicon transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57047975A JPS58164267A (en) 1982-03-25 1982-03-25 Manufacture of thin film silicon transistor

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP34344091A Division JPH0779166B2 (en) 1991-12-25 1991-12-25 Method of manufacturing thin film transistor

Publications (1)

Publication Number Publication Date
JPS58164267A true JPS58164267A (en) 1983-09-29

Family

ID=12790311

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57047975A Pending JPS58164267A (en) 1982-03-25 1982-03-25 Manufacture of thin film silicon transistor

Country Status (1)

Country Link
JP (1) JPS58164267A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0215669A (en) * 1988-07-01 1990-01-19 Ricoh Co Ltd Semiconductor device
WO1995034916A1 (en) * 1994-06-15 1995-12-21 Seiko Epson Corporation Manufacture of thin film semiconductor device, thin film semiconductor device, liquid crystal display device, and electronic device
US5834827A (en) * 1994-06-15 1998-11-10 Seiko Epson Corporation Thin film semiconductor device, fabrication method thereof, electronic device and its fabrication method
US6352883B1 (en) 1991-02-22 2002-03-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for forming the same
US6458200B1 (en) 1990-06-01 2002-10-01 Semiconductor Energy Laboratory Co., Ltd. Method for fabricating thin-film transistor

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5029620A (en) * 1973-07-03 1975-03-25
JPS5045465A (en) * 1973-08-28 1975-04-23
JPS558026A (en) * 1978-06-30 1980-01-21 Matsushita Electric Ind Co Ltd Semi-conductor device manufacturing method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5029620A (en) * 1973-07-03 1975-03-25
JPS5045465A (en) * 1973-08-28 1975-04-23
JPS558026A (en) * 1978-06-30 1980-01-21 Matsushita Electric Ind Co Ltd Semi-conductor device manufacturing method

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0215669A (en) * 1988-07-01 1990-01-19 Ricoh Co Ltd Semiconductor device
US6458200B1 (en) 1990-06-01 2002-10-01 Semiconductor Energy Laboratory Co., Ltd. Method for fabricating thin-film transistor
US7018874B2 (en) 1990-06-01 2006-03-28 Semiconductor Energy Laboratory Co., Ltd. Method for fabricating thin-film transistor
US6740547B2 (en) 1990-06-01 2004-05-25 Semiconductor Energy Laboratory Co., Ltd. Method for fabricating thin-film transistor
US6717180B2 (en) 1991-02-22 2004-04-06 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for forming the same
US6352883B1 (en) 1991-02-22 2002-03-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for forming the same
US6335542B2 (en) 1994-06-15 2002-01-01 Seiko Epson Corporation Fabrication method for a thin film semiconductor device, the thin film semiconductor device itself, liquid crystal display, and electronic device
KR100306527B1 (en) * 1994-06-15 2002-06-26 구사마 사부로 Manufacturing method of thin film semiconductor device, thin film semiconductor device
US6017779A (en) * 1994-06-15 2000-01-25 Seiko Epson Corporation Fabrication method for a thin film semiconductor device, the thin film semiconductor device itself, liquid crystal display, and electronic device
US5858819A (en) * 1994-06-15 1999-01-12 Seiko Epson Corporation Fabrication method for a thin film semiconductor device, the thin film semiconductor device itself, liquid crystal display, and electronic device
US5834827A (en) * 1994-06-15 1998-11-10 Seiko Epson Corporation Thin film semiconductor device, fabrication method thereof, electronic device and its fabrication method
US6972433B2 (en) 1994-06-15 2005-12-06 Seiko Epson Corporation Fabrication method for a thin film semiconductor device, the thin film semiconductor device itself, liquid crystal display, and electronic device
WO1995034916A1 (en) * 1994-06-15 1995-12-21 Seiko Epson Corporation Manufacture of thin film semiconductor device, thin film semiconductor device, liquid crystal display device, and electronic device

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